CN103922273A - Method for manufacturing laminated composite MEMS(Micro-electromechanical Systems)chips and laminated composite MEMS chip - Google Patents
Method for manufacturing laminated composite MEMS(Micro-electromechanical Systems)chips and laminated composite MEMS chip Download PDFInfo
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Abstract
The invention discloses a laminated composite MEMS(Micro-electromechanical Systems)chip and a manufacturing method thereof. The method comprises the following steps: firstly, manufacturing a first MEMS wafer and a silicon perforation wafer, and bonding the first MEMS wafer and the silicon perforation wafer to obtain a sealing wafer; manufacturing an insulating layer and a metal layer on the sealing wafer to form a metalized sealing wafer, and bonding a second MEMS wafer onto the metalized sealing wafer to obtain a laminated composite MEMS wafer; finally, and cutting the laminated composite MEMS wafer to obtain the laminated composite MEMS chip. The method fully utilizes the area of the silicon perforation wafer, and at least one upper sealing cavity and at least one lower sealing cavity are respectively formed in the upper side and the lower side of the silicon perforation wafer. MEMS structures are arranged in the sealing cavities, the signals of the MEMS structures in the sealing cavities are led out through the metal layer, and shield metal layers are arranged among signal lines and are used for isolating interference among the electric signals of different MEMS structures. The laminated composite MEMS chip can meet the requirement of a composite motion sensor chip on different pressures and has the advantages of small size, high integration level, flexible design and low cost.
Description
Technical field
The invention belongs to MEMS chip fabrication techniques field, specifically relate to a kind of lamination combined type MEMS chip, the invention still further relates to the manufacture method of this lamination combined type MEMS chip.
Background technology
MEMS(Micro-Electro-Mechanical Systems) be the abbreviation of MEMS, MEMS manufacturing technology is utilized Micrometer-Nanometer Processing Technology, semiconductor wafer manufacturing technology particularly, produce various MIniature machinery structures, in conjunction with special-purpose control integration circuit (ASIC), form the MEMS components and parts such as intelligentized microsensor, microactrator, micro-optical device.It is little that MEMS components and parts have volume, cost is low, reliability is high, anti-adverse environment ability is strong, low in energy consumption, intelligent degree is high, easily calibration, advantage easy of integration, be widely used in consumer electronics product (as mobile phone, panel computer, toy, digital camera, game machine, air mouse, remote controller, GPS etc.), national defense industry is (as intelligent bomb, guided missile, Aero-Space, unmanned aerial vehicle etc.) and industrial series products (as automobile, robot, intelligent transportation, industrial automation, environmental monitoring, platform stable is controlled, agricultural modernization, security monitoring etc.), MEMS components and parts become the foundation stone of technology of Internet of things gradually.
Along with portable type electronic product, as the rapid growth in the markets such as mobile phone, panel computer, consumer electronics product has become the biggest market of MEMS components and parts, almost in each portable type electronic product, can use a plurality of MEMS components and parts, take smart mobile phone as example, and it has used gyroscope, accelerometer, altimeter, microphone, digital compass, tuned antenna, wave filter etc.Along with market is more and more stricter to the requirement of MEMS components and parts, should volume little, performance is high, low, combined type MEMS components and parts of price again, particularly the market share of combined type MEMS motion sensor is increasing.Combined type MEMS components and parts are that the function of two or more MEMS components and parts is concentrated in components and parts, as combined type movement sensors such as gyroscope+accelerometer, accelerometer+digital compass, gyroscope+accelerometer+digital compass, they are that the way by encapsulation combines by MEMS chip independently mostly, also have directly three axis accelerometer and three-axis gyroscope chip are made in same MEMS chip, Here it is combined type MEMS motion sensor chip.But in existing product, different MEMS structures is to be all produced on same MEMS layer, be accelerometer and gyroscope, or two different gyrohorizon directions of range are arranged, as Invensense, Bosch, the product of STMicroelectronics etc., because different MEMS structures is utilized same MEMS layer making, design flexibility is poor, and, the operation principle of MEMS gyroscope and accelerometer is different, gyroscope service behaviour under lower pressure is best, generally below 0.001 atmospheric pressure, and accelerometer service behaviour under elevated pressures is best, generally more than 0.1 atmospheric pressure, this just requires MEMS chip to meet both demands simultaneously, being about to MEMS gyroscope arrangement is produced on compared with in low pressure, by mems accelerometer structure fabrication in higher air pressure.The existing pair of pressure MEMS wafer-level packaging of chip method is by the K. Reimer of German Fraunhofer-Institut f ü r Siliziumtechnologie, Ch. Schr der, M. the people such as Wei proposes in < < Dual pressure chip capping technology > > mono-literary composition, to be manufactured with getter in an annular seal space, in another annular seal space, there is no getter, when they enclose the mixture of active gases and inert gas during at wafer bonding in annular seal space, then heat post processing, there is the active gases in the annular seal space of getter to be absorbed, remaining inert gas only, internal pressure is lower, different according to the ratio of mist, pressure can approach vacuum, and do not have active gases in the annular seal space of getter can not be absorbed, and gas pressure can not change, and pressure is higher, reaches so two pressure wafer level packaging objects, and the method need to be used getter, and getter also needs graphically, and cost is higher.
Summary of the invention
The technical problem to be solved in the present invention is to overcome the deficiencies in the prior art, and a kind of manufacture method of lamination combined type MEMS chip is provided, to meet the requirement of MEMS structures different in combined type MEMS chip to different air pressure, different materials; And portable type electronic product is to the minimized requirement of components and parts volume.
Another technical problem that the present invention will solve is to provide a kind of lamination combined type MEMS chip, this chip need to not put into getter in annular seal space, just can meet the requirement of combined type movement sensor chip to different pressures, and this chip size is little, integrated level is high, cost is low, the market competitiveness is strong.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of lamination combined type MEMS chip, comprise the following steps:
(1) the one MEMS disk forms: the material of base plate disk is the monocrystalline silicon in <100> crystal orientation, by general semiconductor processing technology, at base plate disk upper surface growth base plate insulating barrier, its material is silica, pass through gluing, exposure, development, the semiconducter process such as etching etch at least one base plate cavity on backplate surface, the not etched part of plate upper surface becomes base plate seal area and the first silicon post, has base plate insulating barrier to retain on described the first silicon post and base plate seal area surface;
The monocrystalline silicon disk in the heavily doped <100> crystal orientation of a slice twin polishing is bonded on base plate disk upper surface by silicon-silica-bound technique, as a MEMS layer disk, owing to there being base plate insulating barrier on base plate disk, so do not electrically connect between base plate disk and monocrystalline silicon disk; Requirement due to bonding technology, monocrystalline silicon disk thickness is generally at 350-750 microns, thicker than designing requirement, so need by grinding, glossing by its thickness reduction the thickness to designing requirement, generally, at 10-100 microns, form a MEMS layer, then by deep silicon etch technique etching the one MEMS layer, form a MEMS seal area, a MEMS structure and a MEMS conduction region, so just complete the manufacture of a MEMS disk.
(2) silicon perforation disk forms: in silicon perforation wafer substrate, by deep silicon etch technique, etch isolating trenches, by the semiconducter process silica of grow, fill up isolating trenches, formation silica separation layer; Front-side etch in silicon perforation wafer substrate goes out the first cavity, and meanwhile, the not etched part in silicon perforation wafer substrate front forms conductive bond district and sealing bonding region; Wet etching is removed the silica outside isolating trenches, has just completed the manufacture of silicon perforation disk, and the material of silicon perforation wafer substrate is the monocrystalline silicon in the heavily doped <100> crystal orientation of twin polishing, has good electric conductivity.
(3) seal disc forms: by the bore a hole figure of a MEMS layer of pattern alignment the one MEMS disk in disk front of silicon, in the bonding apparatus of setting air pressure, carrying out silicon-silicon bond closes, silicon is bored a hole to disk together with a MEMS wafer bonding, form seal disc, wherein, the first cavity becomes the first vertical electrode spacing, and base plate cavity and the first cavity form lower seal chamber jointly, and a MEMS structure is positioned at lower seal chamber.
(4) metallization seal disc forms: the silicon perforation disk back side in grinding seal disc, expose isolating trenches, and silicon perforation disk is isolated ditch and is divided into the first vertical electrode, seal area and silicon conductive pole;
At deposit the first insulating barrier, cover silicon perforation disk, on the first insulating barrier, etch the first through hole, deposit the first metal layer covers the first insulating barrier, fill the first through hole simultaneously, by the graphical the first metal layer of etch process, obtain the first metal wire and press welding block, the first metal wire and a MEMS structure have just had and have electrically connected, and the signal of a MEMS structure just can be drawn by the first metal layer being connected with silicon conductive pole;
Because a MEMS structure and the 2nd MEMS structure may have different operation principles, for avoiding the signal of telecommunication of the two to disturb, also need layer of metal that their signal of telecommunication is shielded, so need to be on the first metal layer deposit the second insulating barrier, at the second insulating barrier, etch the second through hole, deposit the second metal level covers the second insulating barrier again, fill the second through hole simultaneously, then by graphical the second metal level of etch process, obtain the second metal wire and blind zone, between the second metal wire and the first metal wire, just had and electrically connected, first metal wire one end connects press welding block, between the second metal wire and press welding block, just had and electrically connected, deposit the 3rd insulating barrier on the second metal level, etching the 3rd insulating barrier forms third through-hole, deposit the 3rd metal level on the 3rd insulating barrier, third through-hole is also filled simultaneously, by graphical the 3rd metal level of etch process, obtain the 3rd metal wire, the second vertical electrode and metal sealing district, the 3rd metal level has just had and has been electrically connected to the second metal level, finally by etch process, the second insulating barrier and the 3rd insulating barrier that cover on press welding block are removed, formed pressure welding window, expose press welding block, just manufactured metallization seal disc.
(5) the 2nd MEMS disks form: the manufacture method of the manufacture method of the 2nd MEMS disk and a MEMS disk is similar, by general semiconductor processing technology, take the cover plate disk upper surface growth cover plate insulating barrier that the monocrystalline silicon in <100> crystal orientation is material, the material of cover plate insulating barrier is silica, then pass through gluing, exposure, development, the semiconducter process such as etching etch at least one cover plate cavity, and the not etched part of cover plate upper surface becomes cover plate for sealing district and the second silicon post;
The monocrystalline silicon disk in the heavily doped <100> crystal orientation of a slice twin polishing is bonded in cover plate disk the second Gui Zhuhe cover plate for sealing district by silicon-silica-bound technique, as the 2nd MEMS layer disk, owing to having cover plate insulating barrier on the second surface, Gui Zhuhe cover plate for sealing district, between the 2nd MEMS layer disk and cover plate disk, be not electrically connected to; Due to the requirement of bonding technology, need the 2nd MEMS layer disk be ground to thickness between 10-100 μ m by grinding, glossing, form the 2nd MEMS layer, the thickness of the 2nd MEMS layer can be different from the thickness of a MEMS layer, also can be identical; On the 2nd MEMS layer, corresponding cover plate cavity place etches the second cavity, for the 2nd MEMS structure provides freely movable space and as the second vertical electrode spacing; Finally, by deep silicon etch technique etching the 2nd MEMS layer, form the 2nd MEMS seal area, the 2nd MEMS structure and the 2nd MEMS conduction region, like this, just complete the manufacture of the 2nd MEMS disk;
(6) lamination combined type MEMS disk forms: by the lid surface of the 2nd MEMS disk upward, the 2nd MEMS conduction region and the 2nd MEMS seal area are aimed at respectively the 3rd metal wire and the metal sealing district of metallization seal disc, in the bonding apparatus of setting air pressure, carry out silicon-metal bonding, form lamination combined type MEMS disk, wherein the second cavity and cover plate cavity form upper annular seal space jointly, the 2nd MEMS structure is positioned at annular seal space, between the second vertical electrode on the 2nd MEMS layer and metallization seal disc, form the second vertical electrode spacing, for responding to the 2nd MEMS structure motion in the vertical direction, air pressure in described upper annular seal space can be different from the air pressure in lower seal chamber, also can be identical, so far, the manufacture of lamination combined type MEMS disk completes.
(7) lamination combined type MEMS chip forms: for disk is cut into chip, first control the degree of depth of cutter, the 2nd MEMS disk that is positioned at press welding block top in lamination combined type MEMS disk is cut away, expose press welding block; Then by common disk cutting technique cutting lamination combined type MEMS disk, obtain lamination combined type MEMS chip.
The manufacture method of lamination combined type MEMS chip of the present invention, make full use of the area of silicon perforation disk, descend both sides respectively to form annular seal space and at least one lower seal chamber at least one thereon, in each annular seal space, has a MEMS structure at least, the signal of the MEMS structure in upper-lower seal chamber is drawn by metal level, is having shielded metal layer for isolating the interference between the signal of telecommunication of different MEMS structures between their holding wire.The lamination combined type MEMS chip that utilizes method of the present invention to manufacture, the air pressure in upper-lower seal chamber can difference also can be identical, upper and lower MEMS structure can adopt different thickness, has volume little, flexible design, the advantage that cost is low.
For solving another technical problem of the present invention, the invention provides a kind of lamination combined type MEMS chip, by base plate, the one MEMS layer, silicon perforation integrated layer, the 2nd MEMS layer and cover plate form, on base plate, has a base plate cavity at least, on cover plate, has a cover plate cavity at least, base plate cavity and silicon perforation integrated layer form at least one lower seal chamber, cover plate cavity and silicon perforation integrated layer form annular seal space at least one, the air pressure inside of two annular seal spaces is different, the one MEMS structure is positioned at lower seal chamber, the 2nd MEMS structure is positioned at annular seal space, base plate and a MEMS interlayer have base plate insulator separation, cover plate and the 2nd MEMS interlayer have cover plate insulator separation, described silicon perforation integrated layer comprises silicon perforated layer, at least one layer insulating and one deck metal level at least, in described silicon perforated layer, there is isolating trenches, in isolating trenches, fill separation layer, silicon perforated layer is isolated ditch and is divided into sealing bonding region, the first vertical electrode and silicon conductive pole, sealing bonding region and silicon conductive pole all with a MEMS layer Direct Bonding, between the first vertical electrode and a MEMS structure, there is the first vertical electrode spacing, in described silicon perforated layer, accumulation has insulating barrier, has through hole in insulating barrier, and metal level is distributed on insulating barrier and is filled in through hole simultaneously.A described MEMS layer comprises a MEMS bonding region, a MEMS structure and a MEMS conduction region, a MEMS bonding region and sealing bonding region bonding, a MEMS conduction region and silicon conductive pole bonding.Described insulating barrier has three layers, be respectively the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, described metal level has three layers, be respectively the first metal layer, the second metal level and the 3rd metal level, the first insulating barrier covers in silicon perforated layer, in the first insulating barrier, have the first through hole, the first metal layer is distributed on the first insulating barrier and is filled in the first through hole simultaneously, the first metal layer, for drawing the signal of telecommunication of a MEMS structure, is also drawn the signal of telecommunication of a MEMS structure and the 2nd MEMS structure simultaneously as press welding block; The second insulating barrier is deposited on the first metal layer, in the second insulating barrier, have the second through hole, the second metal level covers on the second insulating barrier and is filled in the second through hole simultaneously, the second metal level disturbs for shielding the signal of telecommunication of the first metal layer and the 3rd metal interlevel, simultaneously for connecting the 3rd metal level and the first metal layer; Deposit the 3rd insulating barrier on the second metal level, in the 3rd insulating barrier, have third through-hole, the 3rd metal level covers on the 3rd insulating barrier and is filled in third through-hole simultaneously, the 3rd metal level is for drawing the signal of telecommunication of the 2nd MEMS structure, for surrounding upper annular seal space, between the second vertical electrode part of the 3rd metal level and the 2nd MEMS structure, there is the second vertical electrode spacing simultaneously.Described the first metal layer is divided into the first metal wire and press welding block by function, and the first metal wire electrically connects by the first through hole and the first vertical electrode and silicon conductive pole, and press welding block is exposed outside the second insulating barrier.Described the second metal level is divided into the second metal wire and blind zone by function, and the second metal wire electrically connects by the second through hole and the first metal wire, and first metal wire one end is connected with press welding block.Described the 3rd metal level is divided into the 3rd metal wire, metal sealing district and the second vertical electrode by function, the 3rd metal wire and the 2nd MEMS layer electrically connect, the second vertical electrode electrically connects by third through-hole and the second metal wire, metal sealing district and the 2nd MEMS floor Direct Bonding.
The combined type MEMS chip that builds up of the present invention has annular seal space and at least one lower seal chamber at least one, separate and the stacked setting in upper-lower seal chamber, air pressure in upper-lower seal chamber can difference also can be identical, different MEMS structures lays respectively in upper-lower seal chamber, between with metal level, come shielded signal to disturb, different MEMS structure fabrications is in same MEMS chip, can meet the requirement of different integrated form MEMS components and parts simultaneously, and it is little to have volume, flexible design, cost is low.
Accompanying drawing explanation
Fig. 1 is the profile of base plate disk.
Fig. 2 is the profile of a MEMS disk.
Fig. 3 is the profile of silicon perforation disk.
Fig. 4 is the profile of seal disc.
Fig. 5 is the profile that forms the seal disc of the first metal layer.
Fig. 6 is the profile that forms the seal disc of the second metal level.
Fig. 7 is press welding block side metal line top view.
Fig. 8 is the profile that forms the seal disc of the 3rd metal level.
Fig. 9 is the profile that bonding has the cover plate disk of the 2nd MEMS layer.
Figure 10 is the profile of the 2nd MEMS disk.
Figure 11 is the profile of lamination combined type MEMS disk.
Figure 12 is the profile that cuts away the lamination combined type MEMS disk of the 2nd MEMS disk.
Figure 13 is the schematic diagram of lamination combined type MEMS chip.
The specific embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
Embodiment mono-
The manufacture method of lamination combined type MEMS chip, comprises the following steps:
(1) the one MEMS disk 100A forms:
The material of base plate disk 101A is the monocrystalline silicon in <100> crystal orientation, by general semiconductor processing technology, the base plate insulating barrier 102 of growing on base plate disk 101A, base plate insulating barrier 102 materials are silica, pass through gluing, exposure, develop, the semiconducter process such as etching etch a base plate cavity 103a at base plate disk 101A upper surface, the part that base plate disk 101A upper surface does not etch away becomes the first silicon post 101a and base plate seal area 101b, as shown in Figure 1, on described the first silicon post 101a and base plate seal area 101b surface all with base plate insulating barrier 102, base plate cavity 103a is comprised of right-hand part and left side, and left side and right-hand part communicate, and the first silicon post 101a is surrounded by base plate cavity 103a,
The monocrystalline silicon disk in the heavily doped <100> crystal orientation of a slice twin polishing is bonded on base plate disk 101A upper surface by silicon-silica-bound technique, form the first bonding face, because base plate disk 101A upper surface has base plate insulating barrier 102, so the first bonding face only provides mechanical connection power, do not provide and electrically connect passage, between base plate disk 101A and monocrystalline silicon disk, do not electrically connect, requirement due to bonding technology, the monocrystalline silicon disk thickness in the heavily doped <100> crystal orientation of twin polishing is generally at 350-750 microns, a MEMS layer 104 than designing requirement is thick, so need be by grinding, glossing is the thickness to designing requirement by its thickness reduction, generally at 10-100 microns, form a MEMS layer 104, then by deep silicon etch technique etching the one MEMS layer 104, form a MEMS seal area 104a, the one MEMS structure 104b and a MEMS conduction region 104c, so just manufactured a MEMS disk 100A, as shown in Figure 2.
(2) silicon perforation disk 200A forms:
In silicon perforation wafer substrate 201, by deep silicon etch technique, etch isolating trenches 202, by the semiconducter process silica of grow, isolating trenches 202 is filled up to formation silica separation layer; Front-side etch in silicon perforation wafer substrate 201 goes out the first cavity 203a, and the not etched part in silicon perforation wafer substrate 201 fronts forms sealing bonding region 201a and conductive bond district 201b; Wet etching is removed the silica outside isolating trenches 202, has just completed the manufacture of silicon perforation disk 200A, as shown in Figure 3.The material of silicon perforation wafer substrate 201 is the monocrystalline silicon in the heavily doped <100> crystal orientation of twin polishing, has good electric conductivity.
(3) seal disc 300A forms:
By the bore a hole figure of a MEMS layer 104 of pattern alignment the one MEMS disk 100A in disk 200A front of silicon, in the bonding apparatus of setting air pressure, carrying out silicon-silicon bond closes, by the second bonding face, bore a hole disk 200A and a MEMS disk 100A of silicon is bonded together, form lower seal chamber 103 and the first vertical electrode spacing 203, as shown in Figure 4, the one MEMS structure 104b is positioned at lower seal chamber 103, has so just completed the manufacture of seal disc 300A.The second bonding face both provided mechanical connection power, and conductive channel is also provided.
(4) metallization seal disc 400A forms:
First the silicon in the grinding seal disc 300A perforation disk 200A back side, until expose isolating trenches 202 back sides, like this, silicon perforation disk 200A is just isolated ditch 202 and is divided into the first vertical electrode 201d, sealing bonding region 201c and silicon conductive pole 201e; Then deposit the first insulating barrier 401 covers silicon perforation disk 200A, on described the first insulating barrier 401, etch the first through hole 402, deposit the first metal layer 403 covers the first insulating barrier 401 and fills the first through hole 402 again, and by the graphical described the first metal layer 403 of etch process, obtain the first metal wire 403a and press welding block 403b, as shown in Figure 5; Like this, the first metal wire 403a and a MEMS structure 104b have just had and have electrically connected.
Because two-layer MEMS structure can have different operation principles, for avoiding the signal of telecommunication of the two to disturb, need layer of metal layer that their signal of telecommunication is shielded, first deposit the second insulating barrier 404 on the first metal layer 403, on the second insulating barrier 404, etch the second through hole 405, deposit the second metal level 406 covers the second insulating barrier 404 and fills the second through hole 405 again, and by graphical the second metal level 406 of etch process, obtain blind zone 406b and the second metal wire 406a, as shown in Figure 6; Like this, the second metal wire 406a and the first metal wire 403a have just had and have electrically connected.In Fig. 6, M portion is the metal line district of press welding block side, its top view as shown in Figure 7, the first metal wire 403a electrically connects with silicon conductive pole 201e by the first through hole 402, the second metal wire 406a electrically connects by the second through hole 405 and the first metal wire 403a, one end of the first metal wire 403a connects press welding block 403b, like this, the second metal wire 406a is just electrically connected to press welding block 403b.
Deposit the 3rd insulating barrier 407 on the second metal level 406 as shown in Figure 6, on the 3rd insulating barrier 407, etch third through-hole 408, deposit the 3rd metal level 409 covers the 3rd insulating barrier 407 again, and filling third through-hole 408, and by graphical the 3rd metal level 409 of etch process, obtain the second vertical electrode 409c, the 3rd metal wire 409a and metal sealing district 409b, as shown in Figure 8, like this, the 3rd metal level 409 has been had and has been electrically connected by third through-hole 408 and the second metal level 406; Finally by etch process, the second insulating barrier 404 and the 3rd insulating barrier 407 that cover on press welding block 403b are removed, formed pressure welding window, expose press welding block 403b, manufactured metallized seal disc 400A, as shown in Figure 8; Described silicon perforation disk 200A, the first insulating barrier 401, the first metal layer 403, the second insulating barrier 404, the second metal level 406, the 3rd insulating barrier 407 and the 3rd metal level 409 have formed silicon perforation integrated layer 410.
(5) the 2nd MEMS disk 500A form:
The manufacture method of the manufacture method of the 2nd MEMS disk 500A and a MEMS disk 100A is similar, using the monocrystalline silicon in <100> crystal orientation as the material of cover plate disk 501A, by general semiconductor processing technology, the cover plate insulating barrier 502 of growing on cover plate disk 501A, the material of cover plate insulating barrier 502 is silica, then pass through gluing, exposure, develop, the semiconducter process such as etching, etch cover plate cavity 503a, the not etched part of cover plate disk 501A upper surface becomes cover plate for sealing district 501a and the second silicon post 501b, on described the second silicon post 501b and 501a surface, cover plate for sealing district all with cover plate insulating barrier 502, cover plate cavity 503a is comprised of left side and right-hand part, and the second silicon post 501b is surrounded by cover plate cavity 503a, then the monocrystalline silicon disk in the heavily doped <100> crystal orientation of a slice twin polishing is bonded on cover plate disk 501A the second silicon post 501b and cover plate for sealing district 501a by silicon-silica-bound technique, form the 3rd bonding face, owing to having cover plate insulating barrier 502 on the second silicon post 501b and cover plate for sealing district 501a, so the 3rd bonding face only provides mechanical connection power, do not provide and electrically connect passage, between monocrystalline silicon disk and cover plate disk 501A, be not electrically connected to, requirement due to bonding technology, the monocrystalline silicon disk thickness of twin polishing is generally at 350-750 microns, the 2nd MEMS layer 504 than designing requirement is thick, so need its thickness reduction to be arrived to the thickness of designing requirement by grinding, glossing, generally, at 10-100 microns, form the 2nd MEMS layer 504, as shown in Figure 9, the thickness of described the 2nd MEMS layer 504 can be different from the thickness of a MEMS layer 104, also can be identical.
Then on the 2nd MEMS layer 504, corresponding cover plate cavity 503a place etches the second cavity 505a; Finally, by deep silicon etch technique etching the 2nd MEMS layer 504, form the 2nd MEMS structure 504b, the 2nd MEMS conduction region 504c and the 2nd MEMS seal area 504a, so just manufactured the 2nd MEMS disk 500A, as shown in figure 10.
(6) lamination combined type MEMS disk 600A forms:
By the cover plate disk 501A surface of the 2nd MEMS disk 500A upward, the 2nd MEMS conduction region 504c and the 2nd MEMS seal area 504a aim at respectively the figure of metallization upper the 3rd metal wire 409a of seal disc 400A and metal sealing district 409c, in the bonding apparatus of setting air pressure, carry out silicon-metal bonding, annular seal space 503, the second vertical electrode spacing 505 and pressure welding area annular seal space in formation, air pressure in described upper annular seal space 503 can be different from the air pressure in lower seal chamber 103, also can be identical; Described the 4th bonding face is except providing mechanical connection power, also for the 2nd MEMS structure 504b and the 3rd metal level 409 provide electrical signal paths; So far, lamination combined type MEMS disk 600A has manufactured, as shown in figure 11.
(7) lamination combined type MEMS chip 700 forms:
For disk is cut into chip, first control the degree of depth of cutter, the 2nd MEMS disk 500A that is positioned at press welding block 403b top in lamination combined type MEMS disk 600A is partly cut away, form the first cut surface, expose press welding block 403b, as shown in figure 12.
Finally, by common disk cutting technique cutting lamination combined type MEMS disk 600A, obtain lamination combined type MEMS chip 700, as shown in figure 13.
Embodiment bis-
The lamination combined type MEMS chip 700 that embodiment mono-makes, as shown in figure 13, by base plate 101, the one MEMS layer 104, silicon perforation integrated layer 410, the 2nd MEMS layer 504 and cover plate 501 form, on base plate 101, there is a base plate cavity 103a, on cover plate, there is a cover plate cavity 503a, base plate cavity 103a and silicon perforation integrated layer 410 form a lower seal chamber 103, cover plate cavity 503a and silicon perforation integrated layer 410 form a upper annular seal space 503, the air pressure inside of two annular seal spaces is different, a described MEMS layer 104 comprises a MEMS bonding region 104a, the one MEMS structure 104b and a MEMS conduction region 104c, the one MEMS structure 104b is positioned at lower seal chamber 103, described the 2nd MEMS layer 504 comprises a MEMS bonding region 504a, the one MEMS structure 504b and a MEMS conduction region 504c, the 2nd MEMS structure 504b is positioned at annular seal space 503, base plate 101 and 104, a MEMS layer have 102 isolation of base plate insulating barrier, cover plate 501 and 504, the 2nd MEMS layer have 502 isolation of cover plate insulating barrier, described silicon perforation integrated layer 410 comprises silicon perforated layer 200, the first insulating barrier 401, the first metal layer 403, the second insulating barrier 404, the second metal level 406, the 3rd insulating barrier 407 and the 3rd metal level 409, in described silicon perforated layer 200, there is isolating trenches 202, the interior filling silica of isolating trenches 202 separation layer, silicon perforated layer 200 is isolated ditch 202 and is divided into sealing bonding region 201c, the first vertical electrode 201d and silicon conductive pole 201e, sealing bonding region 201c and silicon conductive pole 201e all with MEMS layer 104 Direct Bonding, between the first vertical electrode 201d and a MEMS structure 104b, there is the first vertical electrode spacing 203, the first insulating barrier 401 covers in silicon perforated layer 200, in the first insulating barrier 401, have the first through hole 402, the first metal layer is distributed on the first insulating barrier 401 and is filled in the first through hole 402 simultaneously, the first metal layer is divided into the first metal wire 403a and press welding block 403b by function, the first metal wire 403a electrically connects by the first through hole 402 and the first vertical electrode 201d and silicon conductive pole 201e, press welding block 403b is exposed outside the second insulating barrier 404, the signal of telecommunication of the first metal layer for drawing a MEMS structure 104b, also as press welding block 403b, draw the signal of telecommunication of a MEMS structure 104b and the 2nd MEMS structure 504b simultaneously, the second insulating barrier 404 is deposited on the first metal layer, in the second insulating barrier 404, have the second through hole 405, the second metal level covers on the second insulating barrier 404 and is filled in the second through hole 405 simultaneously, the second metal level is divided into the second metal wire 406a and blind zone 406b by function, the second metal wire 406a electrically connects by the second through hole 405 and the first metal wire 403a, the second metal level disturbs for shielding the signal of telecommunication of the first metal layer and the 3rd metal interlevel, simultaneously for connecting the 3rd metal level and the first metal layer, deposit the 3rd insulating barrier 407 on the second metal level, in the 3rd insulating barrier 407, have third through-hole 408, the 3rd metal level covers on the 3rd insulating barrier 407 and is filled in third through-hole 408 simultaneously, the 3rd metal level is divided into the 3rd metal wire 409a by function, metal sealing district 409c and the second vertical electrode 409b, the 3rd metal wire 409a and 504, the 2nd MEMS layer electrically connect, the second vertical electrode 409b electrically connects by third through-hole 408 and the second metal wire 406a, metal sealing district 409c and the 2nd MEMS floor 504 Direct Bonding, the signal of telecommunication of the 3rd metal level for drawing the 2nd MEMS structure 504b, simultaneously for surrounding upper annular seal space 503, between the second vertical electrode part of the 3rd metal level and the 2nd MEMS structure, there is the second vertical electrode spacing 505.
Claims (10)
1. the manufacture method of lamination combined type MEMS chip, step is:
(1) the one MEMS disk forms: at base plate disk upper surface growth base plate insulating barrier, etch at least one base plate cavity, the not etched part of plate upper surface becomes base plate seal area and the first silicon post; By monocrystalline silicon wafer bonding on earth on disc upper surface, as a MEMS layer disk, grinding the one MEMS layer disk to 10-100 μ m, form a MEMS layer, etching the one MEMS layer, form a MEMS seal area, a MEMS structure and a MEMS conduction region, like this, just complete the manufacture of a MEMS disk;
(2) silicon perforation disk forms: in silicon perforation wafer substrate, etch isolating trenches, growth silica fills up isolating trenches, form silica separation layer, then etch at least one first cavity, in silicon perforation wafer substrate, not etched part becomes conductive bond district and sealing bonding region, final etch is removed the silica outside isolating trenches, forms silicon perforation disk;
(3) seal disc forms: a MEMS disk and silicon perforation disk are aimed to bonding in the bonding chamber of setting air pressure, form seal disc, wherein the first cavity and base plate cavity form lower seal chamber jointly, and a MEMS structure is positioned at lower seal chamber;
(4) metallization seal disc forms: the silicon perforation disk on grinding seal disc, expose isolating trenches, and silicon perforation disk is isolated ditch and is divided into the first vertical electrode, seal area and silicon conductive pole; On silicon perforation disk deposit at least one deck insulating barrier cover silicon perforation disk, on insulating barrier, etch through hole, deposited metal covers insulating barrier, while filling vias, then graphical metal level, obtains metal wire and press welding block, finally the insulating barrier covering on press welding block is etched away, expose press welding block, manufactured metallization seal disc;
(5) the 2nd MEMS disks form: at cover plate disk upper surface growth cover plate insulating barrier, etch at least one cover plate cavity, the not etched part of cover plate upper surface becomes cover plate for sealing district and the second silicon post; By monocrystalline silicon wafer bonding to cover plate disk upper surface, as the 2nd MEMS layer disk, grinding the 2nd MEMS layer disk to 10-100 μ m, form the 2nd MEMS layer, on the 2nd MEMS layer, corresponding cover plate cavity place etches the second cavity, and final etch the 2nd MEMS layer forms the 2nd MEMS seal area, the 2nd MEMS structure and the 2nd MEMS conduction region, like this, just complete the manufacture of the 2nd MEMS disk;
(6) lamination combined type MEMS disk forms: metallization seal disc and the 2nd MEMS disk are aimed to bonding in the bonding apparatus of setting air pressure, form lamination combined type MEMS disk, wherein the second cavity and cover plate cavity form upper annular seal space jointly, and the 2nd MEMS structure is positioned at annular seal space;
(7) lamination combined type MEMS chip forms: first in lamination combined type MEMS disk, the 2nd MEMS disk of press welding block top is cut away, expose press welding block, then cut lamination combined type MEMS disk, obtain lamination combined type MEMS chip.
2. the manufacture method of lamination combined type MEMS chip according to claim 1, it is characterized in that: in step (1), bonding technology is silicon-silica-bound, in step (3), bonding technology is silicon-silicon bonding, in step (5), bonding technology is silicon-silica-bound, and in step (6), bonding technology is silicon-metal bonding.
3. the manufacture method of lamination combined type MEMS chip according to claim 1, is characterized in that: the material of the silicon perforation wafer substrate that the monocrystalline silicon disk that step (1) and step (5) are described and step (2) are described is all the monocrystalline silicon in the heavily doped <100> crystal orientation of twin polishing.
4. the manufacture method of lamination combined type MEMS chip according to claim 1, it is characterized in that: the described insulating barrier of step (4) has three layers, be respectively the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, the first insulating barrier covers silicon perforation disk, on the first insulating barrier, etch the first through hole, deposit the first metal layer covers the first insulating barrier, fills the first through hole simultaneously, graphical the first metal layer, obtains the first metal wire and press welding block; On the first metal layer, deposit the second insulating barrier, etches the second through hole at the second insulating barrier, then deposit the second metal level covers the second insulating barrier, fills the second through hole simultaneously, and then graphical the second metal level, obtains the second metal wire and blind zone; Deposit the 3rd insulating barrier on the second metal level, etching the 3rd insulating barrier forms third through-hole, deposit the 3rd metal level on the 3rd insulating barrier, and third through-hole is also filled simultaneously, graphical the 3rd metal level, obtains the 3rd metal wire, the second vertical electrode and metal sealing district.
5. the lamination combined type MEMS chip making according to the manufacture method of the lamination combined type MEMS chip described in any one in claim 1 to 4, is characterized in that: base plate, a MEMS layer, silicon perforation integrated layer, the 2nd MEMS layer and cover plate, consist of; On base plate, has a base plate cavity at least, on cover plate, has a cover plate cavity at least, base plate cavity and silicon perforation integrated layer form at least one lower seal chamber, the one MEMS structure is positioned at lower seal chamber, cover plate cavity and silicon perforation integrated layer form annular seal space at least one, the 2nd MEMS structure is positioned at annular seal space, and upper annular seal space is different with lower seal chamber internal gas pressure, and the 2nd MEMS layer and a MEMS layer are bonded in respectively the silicon perforation upper and lower both sides of integrated layer;
Described silicon perforation integrated layer comprises silicon perforated layer, at least one layer insulating and one deck metal level at least, in described silicon perforated layer, there is isolating trenches, in isolating trenches, fill separation layer, silicon perforated layer is isolated ditch and is divided into sealing bonding region, the first vertical electrode and silicon conductive pole, sealing bonding region and silicon conductive pole all with a MEMS layer Direct Bonding, between the first vertical electrode and a MEMS structure, there is the first vertical electrode spacing; In silicon perforated layer, accumulation has insulating barrier, has through hole in insulating barrier, and metal level is distributed on insulating barrier and is filled in through hole simultaneously;
Between the one MEMS layer and base plate, there is base plate insulator separation, between the 2nd MEMS layer and cover plate, have cover plate insulator separation.
6. lamination combined type MEMS chip according to claim 5, it is characterized in that: a described MEMS layer comprises a MEMS bonding region, a MEMS structure and a MEMS conduction region, the one MEMS bonding region and sealing bonding region bonding, a MEMS conduction region and silicon conductive pole bonding.
7. lamination combined type MEMS chip according to claim 5, it is characterized in that: described insulating barrier has three layers, be respectively the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, described metal level has three layers, be respectively the first metal layer, the second metal level and the 3rd metal level, the first insulating barrier covers in silicon perforated layer, has the first through hole in the first insulating barrier, and the first metal layer is distributed on the first insulating barrier and is filled in the first through hole simultaneously; The second insulating barrier is deposited on the first metal layer, has the second through hole in the second insulating barrier, and the second metal level covers on the second insulating barrier and is filled in the second through hole simultaneously; On the second metal level, deposit the 3rd insulating barrier, has third through-hole in the 3rd insulating barrier, and the 3rd metal level covers on the 3rd insulating barrier and is filled in third through-hole simultaneously.
8. lamination combined type MEMS chip according to claim 7, it is characterized in that: described the first metal layer is divided into the first metal wire and press welding block by function, the first metal wire electrically connects by the first through hole and the first vertical electrode and silicon conductive pole, and press welding block is exposed outside the second insulating barrier.
9. lamination combined type MEMS chip according to claim 7, it is characterized in that: described the second metal level is divided into the second metal wire and blind zone by function, the second metal wire electrically connects by the second through hole and the first metal wire, and first metal wire one end is connected with press welding block.
10. lamination combined type MEMS chip according to claim 7, it is characterized in that: described the 3rd metal level is divided into the 3rd metal wire, metal sealing district and the second vertical electrode by function, the 3rd metal wire and the 2nd MEMS layer electrically connect, the second vertical electrode electrically connects by third through-hole and the second metal wire, metal sealing district and the 2nd MEMS floor Direct Bonding.
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