CN103916128A - Successive-approximation analog-to-digital converter for infrared focal plane readout circuit - Google Patents
Successive-approximation analog-to-digital converter for infrared focal plane readout circuit Download PDFInfo
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- CN103916128A CN103916128A CN201410121000.7A CN201410121000A CN103916128A CN 103916128 A CN103916128 A CN 103916128A CN 201410121000 A CN201410121000 A CN 201410121000A CN 103916128 A CN103916128 A CN 103916128A
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- 238000013461 design Methods 0.000 claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 abstract description 9
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- 238000003331 infrared imaging Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
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- 101100053609 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) YSC84 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
本发明公开了一种用于红外焦平面读出电路的逐次逼近型模数转换器，属于集成电路设计领域，其特征在于：该逐次逼近模数转换器采用三段式结构数模转换器，设计成适用于红外焦平面读出电路阵列芯片的结构，限制其版图宽度，可以使其被用于红外焦平面读出电路行共享结构中，实现了红外焦平面电路需要的小面积、低功耗以及高速高精度。有助于红外焦平面读出电路和模数转换系统的集成，提高红外成像系统的精度，减少芯片间的噪声干扰，提高系统信噪比并且使得后期信号处理更简易。
The invention discloses a successive approximation analog-to-digital converter for an infrared focal plane readout circuit, which belongs to the field of integrated circuit design, and is characterized in that: the successive approximation analog-to-digital converter adopts a three-stage structure digital-to-analog converter, It is designed to be suitable for the structure of the infrared focal plane readout circuit array chip, and its layout width is limited, so that it can be used in the row-sharing structure of the infrared focal plane readout circuit, realizing the small area and low power required by the infrared focal plane circuit. consumption and high speed and high precision. It is helpful for the integration of the infrared focal plane readout circuit and the analog-to-digital conversion system, improves the precision of the infrared imaging system, reduces the noise interference between chips, improves the signal-to-noise ratio of the system and makes the later signal processing easier.
Description
Technical field
The present invention relates to integrated circuit (IC) design technology, specifically refer to a kind of integrated circuit with analog-digital conversion function, it can convert the analog signal of Infrared Detectors front end to digital signal for infrared focal plane array reading circuit.
Background technology
The noiseproof feature of high performance infrared focal plane array is subject to the restriction of its signal chains performance conventionally, and this is due to by cross-talk, clock interference, power supply noise, electromagnetic interference etc., inevitably will introduce the undesirable and unavoidable noise of possibility.Because serial data rate in signal chains is the highest in picture system, therefore will introduce white noise by maximum bandwidth, clocking noise and other capacitive coupling noises also increase with the raising of data transfer rate.The every row of infrared focus plane circuit are joined an ADC, and on the sheet passing through, ADC technology can effectively be improved the impact of these effects; And owing to not needing sheet to simulate line outward, the sensitiveness of disturbing and vibrating is eliminated.Particularly on focal plane, detector signal is sampled more more effective than sheet external square type, on sheet, ADC has not only eliminated some noise mechanism, and can increase signal to noise ratio snr by oversampling technique.
The core of infrared focus plane Digital Transmission chip and key are ADC modules integrated on sheet, on sheet, the resolution of ADC has directly determined the signal to noise ratio of Digital Transmission chip signal output, the conversion speed of ADC has limited the reading speed of Digital Transmission chip signal, thereby has limited the highest frame frequency of digital infrared focal plane device.The design therefore with the ADC algorithm structure of high-resolution and certain conversion speed is the key technology of infrared focus plane Digital Transmission chip development.
Gradual approaching A/D converter has certain advantage aspect the amounting to of area, precision and power consumption, and therefore studies gradual approaching A/D converter and has practical engineering application and be worth realizing high integration, high stability and the high accuracy etc. of infrared system.
Summary of the invention
The analog-digital converter circuit structure that the invention provides a kind of row shared structure that is applicable to infrared focal plane read-out circuit, converts the photosignal of infrared detector array to digital signal and reads.
The present invention realizes by following technological approaches:
The invention discloses a kind of gradual approaching A/D converter for infrared focal plane read-out circuit, adopt 0.35um CMOS technique, via EDA(Electronic Design Automation electric design automation) design software Computer Aided Design, analog circuit adopts full custom circuit design, numeral adopts code to write, automatic placement and routing's design after software synthesis, has mainly realized the quantification to detector signal and has exported wherein:
The 1 this gradual approaching A/D converter that is applicable to infrared focal plane read-out circuit is the improvement structure based on common gradual approaching A/D converter, and its structure as shown in Figure 2, is mainly made up of digital to analog converter, precision comparator and digital control circuit.Wherein digital to analog converter is used for converting the digital signal of digital control circuit output to analog voltage signal, comparator is used for the size of output analog voltage and sampled signal voltage of comparand weighted-voltage D/A converter, and digital control circuit is determined the output digit signals of final analog to digital converter simultaneously by the output of comparator for generation of the supplied with digital signal of digital to analog converter.
The mode of operation of 2 gradual approaching A/D converters is as follows:
It is the string number signal that " 1 " all the other positions are " 0 " that digital control circuit produces first place, is converted to voltage signal big or small by comparator with the sampled signal of input by digital to analog converter.The Output rusults of comparator is input to digital control circuit, for determining the first digital code of output signal of analog to digital converter, comparator be output as " 1 " the first digital code be " 1 ", comparator be output as " 0 " the first digital code be " 0 ".After once relatively finishing, digital control circuit changes inferior digit numeric code into " 1 ", the first digital code is the determined digital code of a upper clock comparator, all the other positions are " 0 ", convert the digital signal of generation to analog signal big or small by comparator with output sampled signal by digital to analog converter, thereby determine digital to analog converter output signal time digit numeric code.Carry out according to this N clock cycle, just can determine the numeral output of N position analog to digital converter.Whole process finishes, and has completed the conversion that a time analog quantity arrives digital quantity, and N position transformation result is stored in register, the final digital code of exporting institute's converts analog amount that Here it is.
The design of 3 high-speed comparators:
High-speed comparator should reduce its transmission delay as much as possible, so the basic principle of design is to adopt variation that preamplifier makes input enough greatly and strengthened on latch.This has combined the best feature of circuit: a kind of is the preamplifier with negative exponent response, and another kind is the latch circuit with positive exponent response.A high-speed comparator of following mentioned above principle design is as Fig. 3.The first order is one and increases progressively beneficial high bandwidth preamplifier, and it drives latch.The output of latch is used for driving a self biased differential amplifier.The output of self biased differential amplifier drives an output driver.
The structure of 4 syllogic digital to analog converters and operation principle:
Syllogic digital to analog converter is made up of electric capacity and electric resistance array and control switch, and wherein a point die pressing type for digital to analog converter is: capacitor array is to high-order dividing potential drop, and electric resistance array is to low level dividing potential drop; And high-order dividing potential drop capacitor array is made up of two capacitor arrays, centre is separated by a high accuracy convergent-divergent electric capacity.As Fig. 4 be the design syllogic digital to analog converter (DAC), its MSB(highest significant position) sub-DAC adopts electric charge bi-directional scaling, and LSB(least significant bit) sub-DAC adopts voltage scaling.Wherein MSB DAC adopts one 4 the sub-DAC of electric charge bi-directional scaling and a sub-DAC composition of 5 electric charge bi-directional scalings, by adding that between two sub-DAC a convergent-divergent capacitor C s realizes.Capacitor array adopts the capacitor C of formed objects
0composition.C
smust equal C with the tandem compound value of LSB charge of the electron convergent-divergent capacitor array
c0, C
svalue can be drawn by formula 1:
Therefore convergent-divergent capacitor C s should be
, C
c0for capacitor C
0capacitance, C
csfor capacitor C
scapacitance.
The output voltage of LSB DAC, can use LSB4 position control code L
4l
3l
2l
1represent, as formula 2:
L
4, L
3, L
2, L
1value is respectively 0 or 1, as resistance switch K
1, K
3, K
5, K
7, K
9, K
11, K
13, K
15closure is L
1get 0, otherwise get 1; As resistance switch K
1, K
2, K
5, K
6, K
9, K
10, K
13, K
14l when closed
2get 0, otherwise get 1; As resistance switch K
1, K
2, K
3, K
4, K
9, K
10, K
11, K
12l when closed
3get 0, otherwise get 1; As resistance switch K
1, K
2, K
3, K
4, K
5, K
6, K
7, K
8l when closed
4get 0, otherwise get 1.V
rEF2and V
rEF1for analog-to-digital conversion device reference voltage.
The output voltage that can calculate DAC is expressed formula, as formula 3:
S in formula 3
1～S
9represent the annexation of bidirectional switch, S
1～S
9value is 0 or 1, as capacitance switch S
1～S
9connect reference voltage V
rEF2that value is 1, when connecting reference voltage V
rEF1that value is 0.
Advantage of the present invention is:
1 is conducive to realize infrared focal plane read-out circuit sheet mountain integrated digital function, can reduce infrared system power consumption and area, reduces the noise in infrared system, improves the stability of infrared system.Be conducive to the realization of the infrared imaging system of high integration simultaneously.
2 the present invention is directed to the feature of infrared focal plane read-out circuit, in design, cancel sampling hold circuit, reduce the error that sampling hold circuit is introduced, adopted the new D/A C-structure of syllogic simultaneously, make the area of analog-to-digital conversion device less, power consumption is lower, is applicable to infrared focus plane row shared structure.
Brief description of the drawings
Fig. 1 is the structured flowchart of infrared focal plane read-out circuit, it the is integrated gradual approaching A/D converter of row shared structure.
Fig. 2 is the structured flowchart of gradual approaching A/D converter.
Fig. 3 is high-speed comparator, is made up of, respectively: increase progressively beneficial high bandwidth preamplifier, latch and self biased differential amplifier three parts.The output of self biased differential amplifier drives an output driver.
Fig. 4 is syllogic analog to digital converter, S
1～S
9for bidirectional switch, K
1～K
16for analog switch, V
ref1, V
ref2for reference voltage, C
0for specific capacitance, C
sfor convergent-divergent electric capacity, R is cell resistance.
Embodiment
Design of A/D Converter precision 12bit, adopts 0.35umCMOS technique, and layout design width requirement 60um, can be applicable in the capable shared structure of infrared focal plane read-out circuit of 30um centre-to-centre spacing.Analog-to-digital conversion device operating frequency is 153.8KHz, meets the requirement of infrared focus plane circuit 512*512 array 100 frame frequencies.
1 digital control circuit is by writing Verilog code, comprehensive via DC after, produce domain by Astro instrument.
First 2 comparator design need to make its common-mode input range coupling infrared focal plane read-out circuit preposition detector input stage voltage range (1V～3V in this example).Because the design's precision of A/D converter requires to reach 12bit, therefore the minimum of comparator is differentiated voltage and is less than 0.3mV.Require the maximum delay that can calculate comparator in conjunction with the feature of analog-to-digital conversion device in the design to be less than 250ns by infrared focal plane array scale and reading speed, the high-speed comparator of final choice is as Fig. 3.
3 syllogic digital to analog converters (DAC) are as Fig. 4, its MSB(highest significant position) sub-DAC adopts electric charge bi-directional scaling, and LSB(least significant bit) sub-DAC adopts voltage scaling.Wherein MSB DAC adopts one 4 the sub-DAC of electric charge bi-directional scaling and a sub-DAC composition of 5 electric charge bi-directional scalings, by adding that between two sub-DAC a convergent-divergent capacitor C s realizes.Capacitor array adopts the capacitor C of formed objects
0composition.Capacitor C
0size is 1pf, and capacitor C s size can be calculated as 0.5333pf by formula 1.LSB DAC is voltage scaling form, is made up of similar resistance resistance, and resistance draws for considering power consumption calculation, and the design's value is 2K Ω.
Claims (1)
1. the gradual approaching A/D converter for infrared focal plane read-out circuit, it comprises a digital control circuit of being realized by hardware description language Code Design, three stage structure digital to analog converter and a preamplifier by cascade, latch, the high-precision high-speed comparator of self biased differential amplifier and output driver composition, it is characterized in that: described syllogic digital to analog converter is that distributed digital to analog converter and electric resistance partial pressure digital to analog converter combine again by traditional two-part electric charge, two-part electric charge again one end of the Terminal Capacitance of distribution number weighted-voltage D/A converter is directly connected with the output of electric resistance partial pressure digital to analog converter.
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| CN201410121000.7A CN103916128A (en) | 2014-03-28 | 2014-03-28 | Successive-approximation analog-to-digital converter for infrared focal plane readout circuit |
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|---|---|---|---|
| CN201410121000.7A CN103916128A (en) | 2014-03-28 | 2014-03-28 | Successive-approximation analog-to-digital converter for infrared focal plane readout circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105471432A (en) * | 2015-11-19 | 2016-04-06 | 成都华微电子科技有限公司 | Low power consumption charge redistribution capacitance array circuit |
| CN107870593A (en) * | 2017-11-24 | 2018-04-03 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high speed large dynamic range infrared simulation signal acquisition circuit |
| CN110319856A (en) * | 2019-07-10 | 2019-10-11 | 中国电子科技集团公司第十一研究所 | A kind of infrared detector reading circuit and read-out device |
-
2014
- 2014-03-28 CN CN201410121000.7A patent/CN103916128A/en active Pending
Non-Patent Citations (3)
| Title |
|---|
| LEI GAO ETC.: "On-chip ADC for infrared focal plane arrays", 《PROC SPIE8907 ：INTERNATIONAL SYMPOSIUM ON PHOTOELECTRONIC DETECTION AND IMAGING 2013: INFRARED IMAGING AND 》 * |
| 朱慧等: "一种红外焦平面的数字化输出设计方案", 《激光与红外》 * |
| 窦建华等: "一种用于逐次逼近ADC的低电压", 《宇航计测技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105471432A (en) * | 2015-11-19 | 2016-04-06 | 成都华微电子科技有限公司 | Low power consumption charge redistribution capacitance array circuit |
| CN107870593A (en) * | 2017-11-24 | 2018-04-03 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high speed large dynamic range infrared simulation signal acquisition circuit |
| CN110319856A (en) * | 2019-07-10 | 2019-10-11 | 中国电子科技集团公司第十一研究所 | A kind of infrared detector reading circuit and read-out device |
| CN110319856B (en) * | 2019-07-10 | 2022-04-19 | 中国电子科技集团公司第十一研究所 | Infrared detector reading circuit and reading device |
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Application publication date: 20140709 |