CN103913691B - Jump delay failure vector generation method and device - Google Patents
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Abstract
The present invention provides a kind of jump delay failure vector generation method and device, and wherein, the method comprises determining that the first enable trigger, and described first enables trigger for controlling the source trigger in time exception path；Filter out from the test vector randomly generated jump delay failure vector, described jump delay failure vector make described first enable trigger sweep end-of-shift time level value be disarmed state.Therefore when this jump delay failure vector is used in test process, will not make an exception in the triggered time path, the phenomenon of failure during success when avoiding measurement result in prior art, thus improve test accuracy and the stability of jump delay failure vector, and need not during generating jump delay failure vector, time exception path is analyzed as prior art, reduce the complexity of the atpg tool generating jump delay failure vector.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a method and a device for generating a jump delay fault vector.
Background
The chips are inevitably defective due to factors such as manufacturing processes, manufacturing materials, etc. during the manufacturing process, and thus, the chips need to be tested to remove the chips having defects. At present, a jump delay fault model can be used for testing a chip, namely, an Automatic Test Pattern Generation (ATPG) tool is used for generating a Test vector according to the jump delay fault model, and then the Test vector is used for testing each path of the chip, namely, the Test vector enables a source end of the path to start jump once on one clock edge, and when the influence of the jump on a terminal of the path is captured on the next clock edge, the chip is tested normally, otherwise, the chip is tested to be in fault. Since the test vector is for one clock cycle, and the time exception path (e.g. dummy path, multi-cycle path) is a path that cannot be completed in a single cycle, it is necessary to distinguish which paths are time exception paths.
In the prior art, before a test vector is generated, each time exception path is statically analyzed, then an ATPG tool dynamically analyzes each time exception path when generating the test vector, that is, a value of a source end trigger of the time exception path is detected in an analog manner, if the value of the source end trigger jumps, the jumped value is stored, and meanwhile, the value of the source end trigger is injected into an "X" value, wherein the X is a value which is not 0 or 1, and the "X" value is transmitted forward along a logic cone of the time exception path. If the terminal trigger does not detect the value X, the value of the source end trigger is restored to the value after the jump, then the value of the terminal trigger is calculated according to the value of the source end trigger after the jump, and the value of the terminal trigger is stored in the test vector. If the terminal trigger detects an "X" value, the time exception path is considered to be triggered and the value of the terminal trigger is the "X" value and is stored in the test vector. Therefore, when the test vector tests each path, the test result of the time exception path is determined to be successful according to the condition that the value of the terminal trigger corresponding to the time exception path is the value X.
However, in the prior art, if multiple time exception paths share the same terminal trigger, although the terminal trigger does not detect an "X" value in the process of generating a test vector, that is, the test vector does not cause the terminal trigger to jump, in the actual test process, because the time delays of the time exception paths are different, the terminal trigger may jump, which may cause the test result to succeed or fail sometimes, thereby reducing the stability of the test vector.
Disclosure of Invention
The invention provides a method and a device for generating a jump delay fault vector, which are used for improving the stability of the jump delay fault vector.
In a first aspect, the present invention provides a method for generating a jump delay fault vector, including:
determining a first enabling trigger, wherein the first enabling trigger is used for controlling a source end trigger of a time exception path;
and screening a jump delay fault vector from the randomly generated test vectors, wherein the jump delay fault vector enables the level value of the first enabling trigger at the end of scanning shift to be in an invalid state.
In a second aspect, the present invention provides a device for generating a jump delay fault vector, including:
the device comprises a determining unit, a judging unit and a processing unit, wherein the determining unit is used for determining a first enabling trigger, and the first enabling trigger is used for controlling a source end trigger of a time exception path;
and the generating unit is used for screening a jump delay fault vector from the randomly generated test vectors, and the jump delay fault vector enables the level value of the first enabling trigger determined by the determining unit at the end of scanning shift to be in an invalid state.
According to the jump delay fault vector generation method and device provided by the invention, the first enabling trigger of the source end trigger of the control time exception path is determined, and then the jump delay fault vector is generated, wherein the jump delay fault vector enables the level value of the first enabling trigger at the end of scanning shift to be in an invalid state. Therefore, when the jump delay fault vector is used in the test process, the time exception path can not be triggered, and the phenomenon that the measurement result is successful and failed in the prior art is avoided, so that the test accuracy and the stability of the jump delay fault vector are improved, the time exception path does not need to be analyzed in the process of generating the jump delay fault vector, and the complexity of an ATPG tool for generating the jump delay fault vector is reduced.
Drawings
Fig. 1 is a flowchart of a first embodiment of a method for generating a jump delay fault vector according to the present invention;
FIG. 2 is a diagram illustrating a first time exception path according to an embodiment of the present invention;
fig. 3 is a first schematic diagram of a level value variation relationship of each flip-flop in fig. 2 according to an embodiment of the present invention;
fig. 4 is a second schematic diagram of a level value variation relationship of each flip-flop in fig. 2 according to an embodiment of the present invention;
fig. 5 is a flowchart of a second embodiment of a method for generating a jump delay fault vector according to the present invention;
FIG. 6 is a diagram illustrating a second time exception path according to an embodiment of the present invention;
fig. 7 is a first schematic diagram of a level value variation relationship of each flip-flop in fig. 6 according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a third time exception path according to an embodiment of the present invention;
fig. 9 is a flowchart of a third embodiment of a hopping delay fault vector generation method according to the present invention;
fig. 10 is a flowchart of a fourth embodiment of a method for generating a jump delay fault vector according to the present invention;
fig. 11 is a schematic structural diagram of a first embodiment of a hopping delay fault vector generation apparatus according to the present invention;
fig. 12 is a schematic structural diagram of a second embodiment of the jump delay fault vector generation apparatus according to the present invention.
Detailed Description
Fig. 1 is a flowchart of a first embodiment of a method for generating a jump delay fault vector according to the present invention, and as shown in fig. 1, an execution subject of the embodiment is a jump delay fault vector generation device, for example: the ATPG tool, the method of this embodiment may include:
s101, determining a first enabling trigger, wherein the first enabling trigger is used for controlling a source end trigger of a time exception path.
S102, a jump delay fault vector is screened from randomly generated test vectors, and the jump delay fault vector enables a level value of the first enabling trigger to be in an invalid state when scanning and shifting are finished.
In this embodiment, after configuration of source end triggers of a large number of time exception paths is completed, values of the source end triggers are kept unchanged all the time, and such source end triggers are generally controlled by an enable trigger, and when an enable signal output by the enable trigger is valid, the value of the source end trigger is updated, that is, a jump occurs, and when the enable signal of the enable trigger is invalid, the value of the source end trigger is kept unchanged, that is, no jump occurs. Therefore, to prevent the source end trigger from jumping, the enable trigger for controlling the source end trigger needs to be determined first.
The test vectors are randomly generated, and the non-compliant test vectors are deleted according to the condition required to be met, so as to finally form a group of vectors for testing the jump delay fault, namely the jump delay fault vector, wherein one jump delay fault vector comprises a scan shift enable signal, an excitation and a response, wherein the value in the excitation enables the level value of the first enable trigger at the end of the scan shift to be in an invalid state, the level value of the scan shift enable signal comprises an enable valid state and an enable invalid state, the duration of the enable valid state is related to the length of the scan chain (namely the number of the triggers contained in the scan chain), when the level value of the scan enable signal is in the enable valid state, the enable trigger is shifted, for example, the level value of the enable trigger is changed to be in the valid state or in the invalid state, and when the level value of the scan shift enable signal is changed to be in the invalid state, the level value of the enable trigger is enabled to be kept The level value after the shift is finished is held.
In the time when the level value of the scan shift enable signal is in the invalid state, there are two clocks, one is a launch (launch) clock, and the other is a capture (capture) clock, the level value of the first enable flip-flop after the scan shift is finished is in the invalid state by the jump delay fault vector of this embodiment, and the level value of the first enable flip-flop is still in the invalid state in the period from the end of the scan shift to the arrival of the launch clock by the first enable flip-flop, so the source end flip-flop does not jump on the rising edge of the launch clock, and the jump delay fault vector does not trigger the time exception path. For example: when the time reaches the rising edge of the launch clock, the level value of the first enabling trigger is not triggered to jump, namely the first enabling trigger can keep an invalid state in the launch clock, at the time, the level value of the first enabling trigger acquired by the source end trigger is the level value when the time reaches the rising edge of the launch clock, namely the invalid state, and therefore the source end trigger keeps the level value unchanged, namely the first enabling trigger does not jump according to the fact that the level value of the first enabling trigger is the invalid state.
Or, when the time reaches the rising edge of the launch clock, the level value of the first enabling trigger can be triggered to change from the invalid state to the valid state, although the level value that triggers the first enable flip-flop changes at the present moment of the launch clock rising edge, but a certain time delay is needed for the level value of the first enabling flip-flop to change from the invalid state to the valid state, so that the level value of the first enabling flip-flop is still in the invalid state at this current moment, the level value of the first enable flip-flop obtained by the source flip-flop at this current time is the level value at this current time when the rising edge of the launch clock is reached, namely, the source end flip-flop is in an invalid state, and therefore, the level value of the source end flip-flop is kept unchanged according to the level value of the enabling flip-flop in the invalid state, which indicates that the first enabling flip-flop does not trigger the source end flip-flop to generate a jump, and therefore the source end flip-flop does not jump on the rising edge of the launch clock.
In the method for generating a jump delay fault vector provided by the embodiment of the invention, the first enabling trigger of the source end trigger for controlling the time exception path is determined, and then the jump delay fault vector is generated, wherein the jump delay fault vector enables the level value of the first enabling trigger at the end of scanning shift to be in an invalid state, so that the time exception path is not triggered when the jump delay fault vector is used in a test process, and the phenomena that a measurement result is successful and failed in time and time in the prior art are avoided, so that the test accuracy and the stability of the jump delay fault vector are improved, and the time exception path does not need to be analyzed in the process of generating the jump delay fault vector as in the prior art, so that the complexity of an ATPG tool for generating the jump delay fault vector is reduced.
It should be noted that a level value of "0" may be represented as an invalid state, a level value of "1" may also be represented as an invalid state, and in the following embodiments of the present invention, a level value of "0" is used to represent an invalid state, but the present invention is not limited thereto.
In a feasible implementation manner of the embodiment of the present invention, fig. 2 is a schematic diagram of a first time exception path provided by the embodiment of the present invention, as shown in fig. 2, the time exception path is a path from a source end flip-flop to a terminal flip-flop, and the source end flip-flop is controlled by an enable flip-flop, when an enable signal sent by the enable flip-flop is in an invalid state, for example, "0", a level value of the source end flip-flop is kept unchanged, that is, the source end flip-flop does not hop; when the enable signal sent by the enable flip-flop is in an active state, for example, "1", the level value of the source flip-flop jumps, and the source flip-flop jumps on the rising edge of the launch clock and the terminal flip-flop jumps on the rising edge of the capture clock. Fig. 3 is a first schematic diagram of a level value change relationship of each flip-flop in fig. 2 according to an embodiment of the present invention, where fig. 3 shows a relationship of level value changes of a source end flip-flop and an enable flip-flop in a test process of a test vector (that is, a transition delay fault vector), and a clock signal shown in fig. 3 is a clock signal of a first enable flip-flop, a source end flip-flop, and a terminal flip-flop in a test process corresponding to a transition delay fault vector. A jump delay fault vector may include a scan shift enable signal, a change of a level value of the scan shift enable signal in a test process is shown in fig. 3, when a level value of the scan shift enable signal is 1, a level value of an enable flip-flop may be scan shifted, a clock signal shown in fig. 3 has three pulses (low-speed pulses) within a time when the level value of the scan shift enable signal is 1, which indicates that the jump delay fault vector enables a first enable flip-flop to be scan shifted three times, the level value after the first scan shift is 0 or 1, the scan level value after the second scan shift is 0 or 1, and this embodiment is not limited; note that the level value of the first enable flip-flop after the third scan shift is 0. Since the level value of the first enable flip-flop is triggered to jump, i.e., jump to 0, when the level value of the first enable flip-flop is the third clock rising edge of the clock signal, the level value of the first enable flip-flop at the end of the scan shift (i.e., when the level value of the scan shift enable signal becomes 0) is 0.
After the level value of the first enabling trigger is shifted, two clocks are included in the time when the level value of the scanning shift enabling signal is 0, the first clock is a launch clock, the second clock is a capture clock, and the level value of the first enabling trigger is 0 before the launch clock is reached. When the rising edge of the launch clock is reached, the level value of the first enable flip-flop may have two changing behaviors as follows.
The first variation behavior is: as shown in fig. 3, at the rising edge of the launch clock, the level value of the first enabling trigger is triggered to change; it should be noted that, in this embodiment, a certain time delay is required for the level value of the first enable flip-flop to change from 0 to 1, that is, the level value of the first enable flip-flop is still 0 on the rising edge of the launch clock, and the level value of the first enable flip-flop is updated to 1 in a time period between the lagging of the rising edge of the launch clock and the leading of the rising edge of the capture clock. Therefore, the level value of the first enabling trigger acquired by the source end trigger on the rising edge of the launch clock is 0, the source end trigger keeps unchanged on the rising edge of the launch clock and cannot jump, and then the terminal trigger keeps unchanged on the rising edge of the launch clock and cannot jump. The method includes that a source end trigger is triggered to capture a current level value 1 of a first enabling trigger on a rising edge of a capture clock, the level value of the source end trigger is changed from 0 to 1, and it is worth explaining that updating of the level value of the source end trigger needs a certain time delay, namely the level value of the source end trigger is still 0 on the rising edge of the capture clock, the level value of the source end trigger is updated to 1 in a period of time lagging behind the rising edge of the capture clock, so that the rising edge of the source end trigger on the capture clock is kept unchanged and cannot jump, and then a terminal trigger is kept unchanged on the rising edge of the capture clock and cannot jump. The transition delay fault vector does not trigger a time, e.g., a path, during this test.
The second variation behavior is: as shown in fig. 4, at the rising edge of the launch clock, the level value 0 of the first enable flip-flop is kept unchanged; it should be noted that, the source end flip-flop is further triggered at the rising edge of the launch clock to obtain the current level value of the first enabling flip-flop, so that the level value of the first enabling flip-flop, which is obtained at the rising edge of the launch clock by the source end flip-flop, is 0, the source end flip-flop is also kept unchanged at the rising edge of the launch clock, and no jump occurs, and then the terminal flip-flop is also kept unchanged at the rising edge of the launch clock, and no jump occurs. The level value of the first enabling trigger is still kept unchanged at the rising edge of the capture clock, and it should be noted that the source end trigger is also triggered at the rising edge of the capture clock to acquire the current level value of the first enabling trigger, so the level value of the first enabling trigger acquired at the rising edge of the capture clock by the source end trigger is 0, the source end trigger is also kept unchanged at the rising edge of the capture clock and cannot jump, and then the terminal trigger is also kept unchanged at the rising edge of the capture clock and cannot jump. So the transition delay fault vector does not trigger the clock exception path during this test.
Therefore, in the application scenario shown in fig. 2, the jump delay fault vector makes the level value of the first enable flip-flop invalid at the end of the scan shift, then at the launch clock edge, the source flip-flop will not jump, i.e., the clock exception path is not triggered, so that the time exception path does not need to be analyzed in the process of generating the jump delay fault vector, therefore, when the jump delay fault vector is used in the test process, the time exception path can not be triggered, the phenomena that the measurement result is successful or failed in the prior art are avoided, therefore, the test accuracy and the stability of the jump delay fault vector are improved, and the time exception path does not need to be analyzed in the process of generating the jump delay fault vector as in the prior art, so that the complexity of an ATPG tool for generating the jump delay fault vector is reduced.
Fig. 5 is a flowchart of a second embodiment of the method for generating a jump delay fault vector according to the present invention, and as shown in fig. 5, an execution subject of the embodiment is a jump delay fault vector generation device, for example: the ATPG tool, the method of this embodiment may include:
s201, determining a first enabling trigger, wherein the first enabling trigger is used for controlling a source end trigger of a time exception path.
S202, screening the jump delay fault vector from the randomly generated test vectors, wherein the jump delay fault vector enables the level values of the first enabling trigger at the end of scanning shift and at the time of starting a clock falling edge to be in an invalid state.
In this embodiment, when the source end flip-flop is triggered by a clock falling edge (that is, the transition of the source end flip-flop occurs on the clock falling edge) or the terminal flip-flop is triggered by the clock falling edge (that is, the transition of the terminal flip-flop occurs on the clock falling edge), in order to avoid the source end flip-flop from jumping on a launch clock falling edge or the terminal flip-flop from jumping on a capture clock falling edge, it is further required to ensure that the generated jump delay fault vector controls a level value of the first enable flip-flop of the source end flip-flop when the first enable flip-flop is in a launch clock falling edge to be in an invalid state.
If the source end flip-flop is a flip-flop whose transition occurs at the falling edge of the clock, in this embodiment, the level value of the first enable flip-flop at the end of the scan shift and at the falling edge of the launch clock is in an invalid state, which indicates that the first enable flip-flop is not triggered to generate the transition at the rising edge of the launch clock, and the level value of the first enable flip-flop is kept in the invalid state. When the time reaches the launch clock falling edge, the source end trigger acquires the level value of the first enabling trigger, namely the level value of the first enabling trigger at the launch clock falling edge, and the level value of the first enabling trigger acquired by the source end trigger is in an invalid state.
In this embodiment, the level value of the first enable flip-flop at the end of the scan shift and the level value of the launch clock at the falling edge are in an invalid state, which means that the first enable flip-flop is not triggered to jump at the launch clock rising edge, and the level value of the first enable flip-flop is kept in an invalid state. When the time reaches the rising edge of the launch clock, the source end trigger acquires the level value of the first enabling trigger, namely the level value of the first enabling trigger at the rising edge of the launch clock, so that the source end trigger is in an invalid state according to the level value of the first enabling trigger at the rising edge of the launch clock and does not jump, and then the terminal trigger is kept unchanged at the falling edge of the launch clock and does not jump. The level value of the first enabling trigger in the launch clock is in an invalid state, so that the level value of the first enabling trigger at the rising edge of the capture clock is in an invalid state, when the time reaches the rising edge of the capture clock, the source end trigger acquires the level value of the first enabling trigger, namely the level value of the first enabling trigger at the rising edge of the capture clock is acquired (in an invalid state), the source end trigger keeps unchanged at the rising edge of the capture clock and cannot jump, and then the terminal trigger keeps unchanged at the falling edge of the capture clock, cannot jump and cannot trigger a time exception path.
In the method for generating a jump delay fault vector provided by the embodiment of the present invention, a first enable trigger of a source end trigger controlling a time exception path is determined, and then a jump delay fault vector is screened from randomly generated test vectors, where the jump delay fault vector makes a level value of the first enable trigger at the end of scanning shift and at the falling edge of a start clock be an invalid state. Therefore, when the jump delay fault vector is used in the test process, the time exception path can not be triggered, and the phenomenon that the measurement result is successful and failed in the prior art is avoided, so that the test accuracy and the stability of the jump delay fault vector are improved, the time exception path does not need to be analyzed in the process of generating the jump delay fault vector as in the prior art, and the complexity of an ATPG tool for generating the jump delay fault vector is reduced.
In a possible implementation manner of the embodiment of the present invention, fig. 6 is a schematic diagram of a second time exception path provided by the embodiment of the present invention, as shown in fig. 6, the time exception path is a path from a source end flip-flop to a terminal end flip-flop, the source end flip-flop is controlled by a first enable flip-flop, and the source end flip-flop is a flip-flop with a falling edge transition of a clock. Fig. 7 is a first schematic diagram of a level value change relationship of each flip-flop in fig. 6 according to an embodiment of the present invention, how to make a level value after the level value scanning and shifting of the first enable flip-flop is in an invalid state may refer to related descriptions in fig. 3, which is not described herein again.
As shown in fig. 7, after the scan shift of the first enable flip-flop is finished, the level value of the first enable flip-flop may have two variation modes in the launch clock, but in this embodiment, the level value of the first enable flip-flop at the falling edge of the launch clock is in an invalid state, that is, the first enable flip-flop keeps the level value "0" in the launch clock; when the launch clock falls, the level value of the first enable flip-flop acquired by the source end flip-flop is 0, so that the source end flip-flop does not jump on the launch falling edge, and the level value is kept unchanged, for example, the level value is kept to be 0. The source end trigger does not jump at the descending edge of the launch clock, so that the terminal trigger does not jump at the ascending edge of the capture clock, the level value is kept unchanged, and the time exception path cannot be triggered by the jump delay fault vector in the test process.
In another possible implementation manner of the embodiment of the present invention, fig. 8 is a schematic diagram of a third time exception path provided by the embodiment of the present invention, and as shown in fig. 8, the time exception path is a path from a source end flip-flop to a terminal end flip-flop, the source end flip-flop is controlled by a first enable flip-flop, the terminal end flip-flop is a flip-flop with a falling clock edge transition, and the source end flip-flop is a flip-flop with a rising clock edge transition. Fig. 7 shows a relationship between the level value changes of the flip-flops in fig. 8, and how to make the level value after the level value scanning shift of the first enabling flip-flop in an invalid state may refer to related descriptions in fig. 3, which are not described herein again.
As shown in fig. 7, after the level value scanning shift of the first enable flip-flop is finished, the level value of the first enable flip-flop may have two changes in the launch clock, but in this embodiment, the level value of the first enable flip-flop at the falling edge of the launch clock is in an invalid state, that is, the level value of the first enable flip-flop in the launch clock is kept to be "0". When the launch clock rises, the source end trigger acquires the current level value (0) of the first enabling trigger, and the source end trigger keeps unchanged and does not jump on the launch clock rising edge; and then the terminal trigger is kept unchanged at the launch falling edge and does not jump. Since the first enable flip-flop keeps the level value at "0" in the launch clock, the level value of the first enable flip-flop at the rising edge of the capture clock is also "0". The current level value of the first enabling trigger acquired by the source end trigger at the rising edge of the capture clock is 0, the rising edge of the source end trigger at the capture clock is kept unchanged and does not jump, and then the falling edge of the capture trigger at the terminal trigger is also kept unchanged and does not jump, so that the time exception path cannot be triggered by the jump delay fault vector in the test process.
Fig. 9 is a flowchart of a third embodiment of a method for generating a jump delay fault vector according to the present invention, and as shown in fig. 9, an execution subject of the present embodiment is a jump delay fault vector generation device, for example: the ATPG tool, the method of this embodiment may include:
s301, acquiring indication information input by a user, wherein the indication information is used for indicating a first enabling trigger of a source end trigger of a control time exception path.
S302, determining the first enabling trigger according to the indication information.
S303, a jump delay fault vector is screened from the randomly generated test vectors, and the jump delay fault vector enables the level value of the first enabling trigger to be in an invalid state when the scanning and shifting are finished.
In this embodiment, if the designed RTL code is visible, the user may analyze, for each time exception path, in combination with the RTL code, whether a source end trigger of the time exception path has a first enable trigger controlling the source end trigger, and if so, the user may input indication information indicating the first enable trigger controlling the source end trigger into a jump delay fault vector generation apparatus (for example, an ATPG tool). Assuming that a source end trigger with three time exception paths obtained by user analysis is controlled by a first enabling trigger, indication information input to a hopping delay fault vector generation device by a user can indicate the first enabling triggers respectively controlling the source end triggers of the three time exception paths, after the hopping delay fault vector generation device receives the indication information, the hopping delay fault vector generation device can determine that each enabling trigger indicated in the indication information can control the source end trigger of the time exception path, and then, level values of each first enabling trigger indicated by the indication information at the end of scanning shift are in an invalid state, and a hopping delay fault vector is screened out.
Assuming that a user analyzes and obtains that source end triggers of two time exception paths are not controlled by a first enabling trigger, the processing processes of the two time exception paths are the same as the prior art, namely the two time exception paths are read into an ATPG tool, the source end trigger and the terminal trigger of the time exception paths are determined, a logic gate of the time exception paths is subjected to static splitting, a logic cone influenced by each split part is found, then when a jump delay fault vector is generated, the value of the source end trigger is checked firstly, if the source end trigger jumps, the logic value is stored, and meanwhile, an X value is injected into the source end trigger. This "X" value will pass along the logic cone on the time exception path. And if the terminal trigger does not detect the 'X' value, the stored source end logic value is recovered, the terminal trigger value is calculated according to the recovered value, and the calculated value is used as the test end of the terminal trigger without fault and is stored in the jump delay fault vector. And if the terminal trigger observes the value X, the time exception path is considered to be triggered, and the value X of the terminal trigger is used as the test end of the terminal trigger without fault and is stored in the jump delay fault vector.
In a possible implementation manner, if the indication information is used to indicate a first enable trigger of a source trigger of the control time exception path; or, the indication information is used to indicate a first enable trigger of a source trigger of the control time exception path, and the indication information is further used to indicate: and the source end trigger and the terminal trigger of the time instance path are both triggers with jumping clock rising edges, and the jumping delay fault vector generation device screens jumping delay fault vectors from randomly generated test vectors, wherein the jumping delay fault vectors enable the level value of the first enabling trigger at the end of scanning shift to be in an invalid state.
In another possible implementation manner, if the indication information is used to indicate a first enable flip-flop of a source end flip-flop controlling the time exception path, and the indication information is also used to indicate that the source end flip-flop and/or a terminal flip-flop controlling the time exception path are flip-flops which transition at a falling edge of a clock, the transition delay fault vector is screened from randomly generated test vectors, and the transition delay fault vector makes level values of the first enable flip-flop at the end of scan shift and at the time of starting the falling edge of the clock be in an invalid state.
Fig. 10 is a flowchart of a fourth embodiment of the method for generating a jump delay fault vector according to the present invention, and as shown in fig. 10, an execution subject of the embodiment is a jump delay fault vector generation device, for example: the ATPG tool, the method of this embodiment may include:
s401, acquiring a time exception path.
S402, determining a control trigger of a source trigger for controlling the time exception path.
And S403, determining that the control trigger is a first enabling trigger.
In this embodiment, a user may read a timing constraint file including a time exception path into a hopping delay fault vector generation device, and then the hopping delay fault vector generation device may extract the included time exception path from the timing constraint file, and map a source end of the time exception path to a corresponding trigger, where the trigger may be a source end trigger of the time exception path; and mapping the terminal of the time exception path to a corresponding trigger, wherein the trigger can be the terminal trigger of the time exception path. Then tracing back the source end flip-flop can determine the control flip-flop that controls the source end flip-flop, but the control flip-flop that controls the source end flip-flop is not necessarily the first enable flip-flop, and therefore, after determining the control flip-flop that controls the source end flip-flop, it is also determined whether the control flip-flop is the first enable flip-flop of the source end flip-flop.
Specifically, the level value of the control flip-flop of the source end flip-flop may be set to "0", and if it is determined that the level value of the source end flip-flop is not hopped, it may be determined that the control flip-flop is the first enable flip-flop that controls the source end flip-flop, and when the level value of the first enable flip-flop is "0", the level value is in an invalid state. The level value of the control trigger of the source end trigger may also be set to "1", and if it is determined that the level value of the source end trigger does not jump, it may be determined that the control trigger is the first enable trigger controlling the source end trigger, and when the level value of the first enable trigger is "1", the level value is in an invalid state.
If the level value of the control trigger of the source trigger is set to "0" or "1", and the source triggers all jump, it may be determined that the control trigger is not the first enable trigger for controlling the source trigger. And for the time exception path corresponding to the source trigger, the jump delay fault vector generation device analyzes and processes the time exception path according to the mode of the prior art when generating the jump delay fault vector.
And S404, deleting the time exception path.
In this embodiment, if it is determined that the control trigger of the source end trigger that controls the time exception path is the first enable trigger of the source end trigger, the time exception path may be deleted from the jump delay fault vector generation device, so that the jump delay fault vector generation device does not perform the dynamic analysis on the time exception path as described in the prior art when generating the jump delay fault vector.
S405, a jump delay fault vector is screened from the randomly generated test vectors, and the jump delay fault vector enables the level value of the first enabling trigger to be in an invalid state when the scanning and shifting are finished.
When the control trigger of the control source end trigger is determined to be the first enabling trigger, a jump delay fault vector can be screened from randomly generated test vectors.
In a feasible implementation manner, if the source end flip-flop and the terminal flip-flop of the time exception path are both flip-flops in which a clock rising edge jumps, the screened jump delay fault vector makes a level value of the first enable flip-flop at the end of the scan shift be an invalid state.
In another possible implementation manner, if the source end flip-flop and/or the terminal end flip-flop of the time exception path are flip-flops in which a clock falling edge jumps, the screened jump delay fault vector makes the level value of the first enable flip-flop at the end of the scan shift and at the time of starting the clock falling edge be an invalid state.
In the following, a detailed description is given of an embodiment of the present invention, and the jump delay fault vector generation device may be an ATPG tool.
Step 1: the timing constraint file containing the time exception path is read into the ATPG tool.
Step 2: the temporal exception path is extracted from the constraint.
And step 3: and mapping the source end of the time exception path to a corresponding trigger, and determining the source end trigger of each time exception path. The terminal of the time exception path can be mapped to the corresponding trigger, and the terminal trigger of each time exception path is determined.
And 4, step 4: and tracking the source end triggers of all the time exceptional paths backwards, finding out the control trigger for controlling each source end trigger, and further determining the source end triggers controlled by each control trigger. These control flip-flops are then sorted according to the number of source flip-flops they control. The flip-flop controlling the largest number of source side flip-flops is ranked first. Setting a threshold value, and selecting the control triggers when the number of the source triggers controlled by the control triggers is higher than the threshold value, and placing the control triggers in a set A. It can be considered here that when the number of source end triggers controlled by the control trigger is less than the threshold value, the control trigger is not the first enabling trigger.
And 5: and (4) sequentially analyzing the control triggers in the set A picked out in the step (4).
First, a control trigger A [ i ] is selected, the level value of the control trigger A [ i ] is set to '0', and whether the level value of the source end trigger of the time exception path controlled by the control trigger can keep the original value or not is judged. If the level value of the source end trigger can keep the original value, namely no jump occurs, the control trigger A [ i ] is the enabling trigger of the source end trigger, the enabling value is '1', and when the level value of the control trigger is '0', the control trigger is in an invalid state.
If the level value of the source end trigger can not keep the original value, namely jump occurs, then the level value of the control trigger A [ i ] is set to be 1, and the level value of the source end trigger is judged. If the level value of the source end trigger can keep the original value, namely jump does not occur, the control trigger A [ i ] is a first enabling trigger of the source end trigger, the enabling value is '0', and the control trigger is in an invalid state when the level value of the control trigger is '1'; all source end triggers controlled by the first enabling trigger are recorded in a two-dimensional array B [ A [ i ] with A [ i ] as an index. If the level value of the source end trigger can not keep the original value, namely jump occurs, controlling the trigger A [ i ] not to be a first enabling trigger; control triggers A [ i ] are removed from set A and then other control triggers are analyzed.
After determining that the control trigger is the first enable trigger, step 6 is performed.
Step 6: for the two-dimensional array B, a source end trigger B [ A [ i ] ] [ j ] controlled by a control trigger A [ i ] and an end trigger of a time exception path with the source end trigger B [ A [ i ] ] [ j ] as a starting point are analyzed.
And if all source end triggers controlled by the control trigger are triggered by the clock rising edge, namely the level value of the source end trigger jumps at the clock rising edge, and all end triggers are triggered by the clock rising edge, the level value of the control trigger A [ i ] at the end of scanning shift is in an invalid state. If there is an end point flip-flop which is triggered by the falling edge of the clock, the level value of the control flip-flop A [ i ] at the end of the scanning shift and the level value of the launch clock falling edge are both in an invalid state. And if one source end trigger in all the source end triggers controlled by the control trigger is triggered by the clock falling edge, controlling the level value of the control trigger A [ i ] at the end of scanning shift and the level value of the launch clock falling edge to be in an invalid state. Therefore, the time exception paths with the source end trigger B [ A [ i ] ] [ j ] as the starting point can not be triggered, then the time exception paths can be removed from the constraint, and the dynamic analysis in the prior art is not needed in the generation process of the jump delay fault vector, so that the complexity of the ATPG tool is reduced.
Although a part of the time exception paths are removed in step 6, a part of the time exception paths may also exist in the constraint, and for these remaining time exception paths, the process of generating the transition delay fault vector is still processed according to the prior art, such as statically splitting logic gates of these remaining time exception paths, finding out a logic cone affected by each split part, and then performing dynamic analysis.
Fig. 11 is a schematic structural diagram of a first embodiment of a jump delay fault vector generation apparatus according to the present invention, and as shown in fig. 11, the apparatus of this embodiment may include: the device comprises a determining unit 11 and a generating unit 12, wherein the determining unit 11 is used for determining a first enabling trigger, and the first enabling trigger is used for controlling a source trigger of a time exception path; the generating unit 12 is configured to screen a jump delay fault vector from randomly generated test vectors, where the jump delay fault vector makes a level value of the first enable trigger determined by the determining unit 11 at the end of the scan shift be an invalid state.
Optionally, the generating unit 12 is specifically configured to screen a jump delay fault vector from randomly generated test vectors, where the jump delay fault vector makes level values of the first enable flip-flop at the end of the scan shift and at the time of starting a falling edge of the clock be in an invalid state.
The apparatus of this embodiment may be configured to implement the technical solution of the method embodiment of the present invention, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 12 is a schematic structural diagram of a second embodiment of the apparatus for generating a jump delay fault vector according to the present invention, and as shown in fig. 12, the apparatus of this embodiment may further include, on the basis of the apparatus structure shown in fig. 11: an acquisition unit 13.
In a first possible implementation manner, the obtaining unit 13 is configured to obtain indication information input by a user before the determining unit 11 determines the first enabling trigger, where the indication information is used to indicate the first enabling trigger of an origin trigger controlling the time exception path; the determining unit 11 is specifically configured to determine the first enabling trigger according to the indication information acquired by the acquiring unit 13.
In a second possible implementation manner, the obtaining unit 13 is configured to obtain the time exception path before the determining unit 11 determines the first enabling trigger; determining a control trigger for controlling a source trigger of the time exception path; the determining unit 11 is specifically configured to: setting the level value of the control trigger to be 0, and if the level value of a source end trigger controlled by the control trigger is determined not to jump, determining the control trigger to be the first enabling trigger; or setting the level value of the control trigger to be "1", and if it is determined that the level value of the source end trigger controlled by the control trigger does not jump, determining that the control trigger is the first enabling trigger.
Optionally, the apparatus of this embodiment may further include: a deleting unit 14, where the deleting unit 14 is configured to delete the time exception path after the determining unit 11 determines that the control trigger is the first enabling trigger.
The apparatus of this embodiment may be configured to implement the technical solution of the method embodiment of the present invention, and the implementation principle and the technical effect are similar, which are not described herein again.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for generating a jump delay fault vector is characterized by comprising the following steps:
determining a first enabling trigger, wherein the first enabling trigger is used for controlling a source end trigger of a time exception path;
and screening a jump delay fault vector from the randomly generated test vectors, wherein the jump delay fault vector enables the level value of the first enabling trigger at the end of scanning shift to be in an invalid state.
2. The method of claim 1, wherein the screening out a transition delay fault vector from randomly generated test vectors, wherein the transition delay fault vector renders a level value of the first enable flip-flop at the end of the scan shift invalid, comprises:
and screening a jump delay fault vector from the randomly generated test vectors, wherein the jump delay fault vector enables the level values of the first enabling trigger at the end of scanning shift and the falling edge of the starting clock to be in an invalid state.
3. The method of claim 1 or 2, wherein prior to determining the first enabling trigger, further comprising:
acquiring indication information input by a user, wherein the indication information is used for indicating the first enabling trigger of a source end trigger for controlling the time exception path;
the determining a first enabling trigger includes:
and determining the first enabling trigger according to the indication information.
4. The method of claim 1 or 2, wherein prior to determining the first enabling trigger, further comprising:
acquiring the time exception path;
determining a control trigger of a source trigger for controlling the time exception path;
the determining a first enabling trigger includes:
setting the level value of the control trigger to be 0, and if the level value of a source end trigger controlled by the control trigger is determined not to jump, determining the control trigger to be the first enabling trigger; or,
and setting the level value of the control trigger to be 1, and if the level value of the source end trigger controlled by the control trigger is determined not to jump, determining the control trigger to be the first enabling trigger.
5. The method of claim 4, wherein after determining that the control trigger is the first enable trigger, further comprising:
deleting the time exception path.
6. A apparatus for generating a transition delay fault vector, comprising:
the device comprises a determining unit, a judging unit and a processing unit, wherein the determining unit is used for determining a first enabling trigger, and the first enabling trigger is used for controlling a source end trigger of a time exception path;
and the generating unit is used for screening a jump delay fault vector from the randomly generated test vectors, and the jump delay fault vector enables the level value of the first enabling trigger determined by the determining unit at the end of scanning shift to be in an invalid state.
7. The apparatus according to claim 6, wherein the generating unit is specifically configured to screen out a transition delay fault vector from randomly generated test vectors, wherein the transition delay fault vector is configured to disable the level values of the first enable flip-flop at the end of the scan shift and at the start of the falling edge of the clock.
8. The apparatus of claim 6 or 7, further comprising:
an obtaining unit, configured to obtain indication information input by a user before the determining unit determines the first enabling trigger, where the indication information is used to indicate the first enabling trigger of a source trigger that controls the time exception path;
the determining unit is specifically configured to determine the first enabling trigger according to the indication information acquired by the acquiring unit.
9. The apparatus of claim 6 or 7, further comprising:
an obtaining unit, configured to obtain the time exception path before the determining unit determines the first enabling trigger; determining a control trigger for controlling a source trigger of the time exception path;
the determining unit is specifically configured to: setting the level value of the control trigger to be 0, and if the level value of a source end trigger controlled by the control trigger is determined not to jump, determining the control trigger to be the first enabling trigger; or setting the level value of the control trigger to be "1", and if it is determined that the level value of the source end trigger controlled by the control trigger does not jump, determining that the control trigger is the first enabling trigger.
10. The apparatus of claim 9, further comprising:
and the deleting unit is used for deleting the time exception path after the determining unit determines that the control trigger is the first enabling trigger.
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| CN101852839A (en) * | 2010-05-19 | 2010-10-06 | 中国科学院计算技术研究所 | Ageing predetermination and overspeed delay testing bifunctional system and method thereof |
| CN103675641A (en) * | 2013-12-23 | 2014-03-26 | 龙芯中科技术有限公司 | Chip fault positioning method, device and system |
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| CN101764125A (en) * | 2010-01-07 | 2010-06-30 | 中国科学院计算技术研究所 | Overspeed delay test system and method |
| CN101852839A (en) * | 2010-05-19 | 2010-10-06 | 中国科学院计算技术研究所 | Ageing predetermination and overspeed delay testing bifunctional system and method thereof |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |