CN109444714B

CN109444714B - Real-time scanning test method and control circuit

Info

Publication number: CN109444714B
Application number: CN201811406396.4A
Authority: CN
Inventors: 张心标; 曾辉; 姜雪风
Original assignee: Zhongke Sugon Information Industry Chengdu Co ltd; Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Zhongke Sugon Information Industry Chengdu Co ltd; Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2018-11-23
Filing date: 2018-11-23
Publication date: 2022-03-01
Anticipated expiration: 2038-11-23
Also published as: CN109444714A

Abstract

The invention provides a real-time scanning test method and a control circuit. The method is used for real-time scanning test of a clock area, the clock area comprises a plurality of scanning chains, and each scanning chain flexibly controls scanning enabling through a pipeline scanning enabling signal, and the method comprises the following steps: sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock; additionally shifting data into the scanning registers on each scanning chain by adopting a fast clock; loading the excitation to the input end of each scan chain, and capturing the test output value of each scan chain by adopting a quick clock; the pipeline scanning enabling signal is effective when being shifted into data, effective when being additionally shifted into the data and ineffective when being captured. The test method has high coverage rate of the jump fault test and good controllability.

Description

Real-time scanning test method and control circuit

Technical Field

The invention relates to the technical field of chip testing, in particular to a real-time scanning testing method and a control circuit.

Background

With the continuous development of semiconductor digital integrated circuits, the scale of the digital integrated circuits is continuously increased, and how to perform sufficient and effective tests on large-scale digital integrated circuits has become the most difficult and important task at present. Thus, design for testability (DFT) of digital integrated circuits is increasingly valued and applied by engineers. As the operating frequency of digital integrated circuits is increasing, real-time scan test (at-speed scan test) becomes more important for the design of testability of chips.

The real-time scan test (at-speed scan test) can cover some faults which cannot be related to the static test, such as transition fault (transition fault), delay fault (delay fault), and the like. It uses a high-speed clock (at-speed clock) in the capture stage (capture), if the circuit works normally, the jump will propagate to the end of the path in time, and can capture the correct value. Otherwise, if there is a delay causing slow propagation, the transition from trigger to capture will be problematic and the error value will be captured, and the defect is detected.

The existing real-time scanning test methods mainly include two types, one is Capture-on-Capture (LOC for short, and some places are also called Functional approval/broadcast Load), and the other is Shift-loading (LOS for short, and some places are also called skip Load).

For LOC, as shown in FIG. 1, the basic steps are that in the shift phase, the scan enable signal SE is high, and a slow speed clock (slow speed shift clock) is used to shift data into the scan chain. The SE is then pulled low into the capture phase to generate two operating frequency pulses (at-speed capture clock), the first pulse to generate a transition to initiate a propagation from a scan cell, i.e. launch, and the second pulse to capture (capture) the scan cell value.

For LOS, as shown in FIG. 2, the basic steps are that in the shift stage, the scan enable signal SE is high, and for the scan chain to shift in data, it is assumed that the scan chain includes N scan registers, the first N-1 beat occurs in the low speed clock, the Nth beat adopts the high speed clock at-speed clock, and at the same time, a jump is generated in the Nth beat, and launch is executed. Then, the scan enable signal SE is pulled down immediately, and enters a capture stage, and a high-speed clock is adopted to capture the value of the scan unit.

In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:

LOC is triggered by a transition in an operating mode (high-speed clock), and therefore may propagate along an actual operating path, so that many transition faults cannot be detected, and thus the test coverage rate of the LOC transition faults is relatively low. In LOS, because the clock is the high-speed clock at-speed clock when the scan chain is last shifted (launch is performed at the same time), and then the scan enable signal needs to be pulled down immediately, the LOS has poor controllability.

Disclosure of Invention

In order to solve the problems, the invention provides a real-time scanning test method, which has high coverage rate of jump fault test and good controllability.

In a first aspect, the present invention provides a real-time scan testing method, for performing real-time scan testing on a clock region, where the clock region includes a plurality of scan chains, and each scan chain flexibly controls scan enabling through a pipeline scan enabling signal, the method including:

sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock;

additionally shifting data into the scanning registers on each scanning chain by adopting a fast clock;

loading the excitation to the input end of each scan chain, and capturing the test output value of each scan chain by adopting a quick clock;

the pipeline scanning enabling signal is effective when being shifted into data, effective when being additionally shifted into the data and ineffective when being captured.

In a second aspect, the present invention provides a real-time scan testing method, for performing real-time scan testing on a clock region, where the clock region includes a plurality of scan chains, and each scan chain flexibly controls scan enabling through a pipeline scan enabling signal, the method including:

setting a test mode of a clock area, wherein the test mode comprises a first mode and a second mode;

if the first mode is adopted to carry out real-time scanning test on the clock area, the test is carried out according to the following steps:

if the real-time scanning test is carried out on the clock area by adopting the second mode, the test is carried out according to the following steps:

triggering the propagation of each scan chain by adopting a quick clock;

the pipeline scanning enabling signal is effective when data is shifted in the first mode, effective when data is additionally shifted in and ineffective when data is captured, and is effective when data is shifted in the second mode, ineffective when data is triggered and ineffective when data is captured.

In a third aspect, the present invention provides a real-time scan test control circuit, including:

the device comprises a pipeline scanning enabling unit, a clock area and a control unit, wherein the pipeline scanning enabling unit is used for outputting a pipeline scanning enabling signal under a first mode or a second mode according to a test mode of the clock area, the pipeline scanning enabling signal is effective when data is shifted in the first mode, effective when data is additionally shifted in and ineffective when data is captured, and the pipeline scanning enabling signal is effective when data is shifted in the second mode, ineffective when triggered and ineffective when captured, and is input into each scan chain in the clock area;

the clock test enabling unit is used for outputting a clock test enabling signal according to a test mode of a clock area, wherein the clock test enabling signal is effective when data is shifted in a first mode, is effective when the data is additionally shifted in, and is ineffective when the data is captured, and is effective when the data is shifted in a second mode, is ineffective when triggered, and is ineffective when captured;

and the clock gate control unit is used for outputting a scanning clock signal according to the clock test enabling signal and the function enabling signal, and the scanning clock signal is input into each scanning chain in the clock area.

Optionally, the clock test enabling unit includes: a first scan register, a second scan register, a first general register, a first OR gate, a second OR gate, a third OR gate, and a first AND gate,

the scanning input ends of the first scanning register and the second scanning register shift in scanning data;

a D end of the first scan register is connected with a Q end of the first scan register, the Q end of the first scan register is connected with one input end of the first OR gate, the other input end of the first OR gate inputs a scan enable signal, an output end of the first OR gate is connected with the D end of the first general register, and the Q end of the first general register is connected with one input end of the first AND gate;

a D end of the second scan register is connected with a Q end of the second scan register, the Q end of the second scan register is connected with one input end of the second or gate, the other input end of the second or gate inputs a scan enable signal, and an output end of the second or gate is connected with the other input end of the first and gate;

the output end of the first and gate is connected with one input end of the third or gate, the other input end of the third or gate is connected with the output end of the first or gate, and the output end of the third or gate is used for outputting a clock test enabling signal.

Optionally, the pipeline scan enabling unit includes: a third scan register, a fourth scan register, a multiplexer, a second general register, a second AND gate, and a fourth OR gate,

the D end of the third scanning register is connected with the Q end of the third scanning register, the D end of the fourth scanning register is connected with the Q end of the fourth scanning register, scanning data are shifted into the scanning input ends of the third scanning register and the fourth scanning register, and the Q end is connected with the selection end of the multi-path selection register;

the output end of the multiplexer is connected with one input end of the second AND gate;

a D end of the second general register inputs a scanning enabling signal, and a Q end of the second general register is connected with the other input end of the second AND gate;

one input end of the fourth or gate inputs a scan enable signal, the other input end of the fourth or gate is connected with the output end of the second and gate, and the output end of the fourth or gate is used for outputting a pipeline scan enable signal.

Optionally, the third scan register and the fourth scan register are used to set a test mode, and if the third scan register is shifted to "1" and the fourth scan register is shifted to "0", the test mode is set to the first mode; the third scan register is shifted to "0" and the fourth scan register is shifted to "1", and the test mode is set to the second mode.

Optionally, the output of the multiplexer is "1" in the first mode and "0" in the second mode.

According to the real-time scanning test method and the control circuit provided by the invention, because the pipeline scanning enable signal PSE is effective in an extra shift stage (namely a launch stage), and the scan chain is still in a shift state, a shift path is taken instead of a normal working path when the launch is triggered by a condition, so that the jump fault test coverage rate is higher. Meanwhile, slow clocks are adopted in the process (shift) of shifting data into the scan chain, so that the controllability is high.

Drawings

FIG. 1 is a timing diagram illustrating a conventional LOC testing method;

FIG. 2 is a timing diagram of a prior art LOS test method;

FIG. 3 is a flow chart of one embodiment of a real-time scan test method of the present invention;

FIG. 4 is a timing diagram illustrating an embodiment of a real-time scan test method according to the present invention;

FIG. 5 is a timing diagram illustrating a real-time scan test method configured as a second mode according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a real-time scan test control circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a structure of the PTE _ STRUC of FIG. 6;

FIG. 8 is a schematic diagram of a structure of the pipeline scan enable unit PSE _ STRUC in FIG. 6;

FIG. 9 is a schematic diagram of an embodiment of a real-time scan test control circuit for testing an entire test area.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a real-time scan testing method, configured to perform real-time scan testing on a clock region, where the clock region includes a plurality of scan chains, and each scan chain flexibly controls scan enabling through a pipeline scan enabling signal, as shown in fig. 3, where the method includes:

s11, sequentially shifting data into the scanning registers on the scanning chains by adopting a slow clock, wherein the pipeline scanning enabling signal is effective when the data are shifted;

s12, shifting data into the scan registers of each scan chain by adopting a fast clock, wherein the pipeline scan enable signal is effective when the data is additionally shifted;

and S13, loading excitation to the input end of each scan chain, capturing the test output value of each scan chain by adopting a fast clock, and invalidating a pipeline scan enable signal during capturing.

Unless otherwise specified, in the embodiments of the present invention, the signal active means a high level, and the signal inactive means a low level. Before starting the test, it is necessary to initialize each scan chain in the clock region so that the scan register on each scan chain is at a predetermined value. After capturing the test output value of each scan chain, the pipeline scan enable signal input by each scan chain in the control clock area needs to be validated again, and the test output value of each scan chain is output.

The real-time scan testing method provided by the embodiment of the invention is an Enhanced real-time scan testing method (Enhanced Launch extra-Shift, ELS for short), all flip-flops are supposed to be triggered sensitively by clock rising edges, and the method is based on a scan chain consisting of four scan registers.

With reference to fig. 4, the basic flow of the scan test using the ELS test method based on the scan chain composed of four scan registers is as follows:

1) shifting (shift) the scan chain four times by adopting a slow clock, wherein the PSE is effective;

2) additionally shifting (extra shift) data into the scan chain once by adopting a fast clock (extra shift is performed in the 5 th step in the figure), wherein the PSE is still effective, and the scan _ clk is switched to an at-speed clock;

3) and pulling down the PSE, enabling the scan chain to be in a working state, entering a capture stage, loading excitation to an input end of the scan chain, and capturing a test output value of the scan chain, wherein scan _ clk is also an at-speed clock.

In the real-time scanning test method provided by the embodiment of the invention, because the pipeline scanning enable signal PSE is effective in the extra shift stage (namely the launch stage), and the scan chain is still in the shift state, the shift path is taken instead of the normal working path when the launch is triggered by the condition, so that the jump fault test coverage rate is higher. Meanwhile, slow clocks are adopted in the process (shift) of shifting data into the scan chain, so that the controllability is high. It can be seen that the present invention can improve existing LOC and LOS testing methods.

Further, the real-time scanning test method in the above embodiment mainly performs a test for one clock region, and when an actual chip is tested, the whole test region must have more than one clock region, and if each clock region adopts an ELS test method, power consumption is unacceptable. Considering the power consumption problem, all clock regions cannot use the ELS test method at the same time, and two selectable test modes are set for each clock region.

The embodiment of the invention also provides a real-time scanning test method, which is used for carrying out real-time scanning test on a clock area, wherein the clock area comprises a plurality of scanning chains, and each scanning chain flexibly controls scanning enabling through a pipeline scanning enabling signal, and the method comprises the following steps:

s21, setting a test mode of a clock area, wherein the test mode comprises a first mode and a second mode;

s22, performing real-time scan test on the clock area according to the set test mode, including:

when the real-time scanning test is carried out on the clock area by adopting the first mode, the test is carried out according to the following steps:

sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock, wherein a pipeline scanning enabling signal is effective;

data is additionally shifted into the scanning registers on each scanning chain by adopting a fast clock, and the pipeline scanning enabling signal is effective at the moment;

and loading the excitation to the input end of each scan chain, and capturing the test output value of each scan chain by adopting a quick clock, wherein the pipeline scan enable signal is invalid.

When the real-time scanning test is carried out on the clock area by adopting the second mode, the test is carried out according to the following steps:

triggering the propagation of each scan chain by adopting a quick clock, wherein the pipeline scan enabling signal is invalid;

Obviously, the first mode herein adopts the ELS testing method of the foregoing embodiment, and the timing diagram can refer to fig. 4, and the second mode adopts the existing LOC testing method, and the timing diagram is shown in fig. 5. It should be noted that, regardless of the first mode or the second mode, the method further includes the following steps:

before starting the test, each scan chain in the clock region needs to be initialized, so that the scan register on each scan chain is in a preset value. After capturing the test output value of each scan chain, the pipeline scan enable signal input by each scan chain in the control clock area needs to be validated again, and the test output value of each scan chain is output.

According to the real-time scanning test method provided by the embodiment of the invention, each clock area has two test modes which can be selected, the first mode adopts an ELS test method, the second mode adopts the existing LOC test method, and the test mode of the clock area is set according to the requirement, so that the real-time scanning test of the clock area is more flexible, and higher jump fault test coverage rate can be obtained under the condition of lower power consumption.

Based on the real-time scanning test method, when the real-time scanning test is carried out on the whole test area, the whole test area is divided into a plurality of clock areas, each clock area has different clocks, and the test is carried out according to the following method:

1) appointing a clock area as a current target clock area, carrying out real-time scanning test on the current target clock area by adopting an ELS test method in a first mode, and carrying out real-time scanning test on other clock areas except the current target clock area by adopting an LOC test method in a second mode;

2) and sequentially appointing each clock area as a current target clock area, and repeatedly executing the step 1) to finish the test of the whole test area.

For example, the whole test area is divided into several Clock areas, Clock Domain1, Clock Domain2, … … Clock Domain n. The Clock Domain1 is tested by the ELS method, and the other Clock domains (Clock Domain2-Clock Domain) are tested by the LOC method. The Clock Domain2 is tested by an ELS method, and the other Clock domains (Clock Domain1, Clock Domain3-Clock Domain) are tested by a LOC method. And repeating the steps in the same way to finish the test of the whole test area. By the method, the whole test area is subjected to real-time scanning test, different clock areas are divided, and an ELS and LOC test method is combined in the scanning process, so that higher jump fault test coverage rate can be obtained under lower power consumption.

Further, to implement the real-time scan testing method of the embodiment of the present invention, a set of control circuit is required to ensure that the levels of the scan clock and the pipeline scan enable signal at each stage meet the requirements.

Therefore, an embodiment of the present invention further provides a real-time scan test control circuit, as shown in fig. 6, including:

the PSE-STRUC comprises a pipeline scanning enabling unit PSE-STRUC, and is characterized in that according to a test mode and a time sequence of a corresponding clock region, the test mode comprises a first mode and a second mode, a pipeline scanning enabling signal PSE in the first mode or the second mode is output, the pipeline scanning enabling signal PSE is effective when data is input in the first mode, effective when data is additionally input in the first mode and ineffective when capturing, and the pipeline scanning enabling signal PSE is effective when data is input in the second mode, ineffective when triggering and ineffective when capturing, and the PSE inputs each scan chain in the clock region;

the clock test enabling unit PTE _ STRUC outputs a clock test enabling signal TE according to a test mode and a time sequence of a corresponding clock area, wherein the clock test enabling signal TE is effective when data is shifted in a first mode, is effective when the data is additionally shifted in, and is ineffective when being captured, and is effective when the data is shifted in a second mode, is ineffective when being triggered, and is ineffective when being captured;

and the clock gate control unit ICG is used for outputting a scanning clock signal scan _ clk according to the clock test enabling signal TE and the function enabling signal EN, and the scanning clock signal scan _ clk is input into each scanning chain in the clock region.

Referring to fig. 4, analyzing the ELS process, it can be seen that the first beat of the two-beat fast clock is used for extra shift (i.e., launch), and the second beat is used for capture. For the clock, the clock test enable signal TE needs to be active at the time of extra shift (to "1") and disabled at the time of capture (to "0"), and thus the corresponding logic value of the clock test enable signal TE at the two-beat fast clock stage should be "10" or "11". In order to obtain higher coverage, the logic structure of the function enable terminal EN of the clock gate control unit ICG needs to be tested, and thus the logic value of the clock test enable signal TE should be "10" in the two-beat fast clock phase. In addition, the ELS method is used together with the LOC method, so the logic value of the clock test enable signal TE in the two-beat fast clock phase should also be "00".

Alternatively, a structural form of the clock test enable unit PTE _ STRUC is shown in fig. 7, and the clock test enable unit PTE _ STRUC includes: two scan registers scan _ ff1, scan _ ff2, a general register DFF1, three OR gates OR1, OR2, OR3, an AND gate AND1, scan inputs of the scan registers scan _ ff1 AND scan registers scan _ ff2 shift in scan data, a D terminal AND a Q terminal of the scan register scan _ ff1 are connected, a Q terminal of the scan register scan _ ff1 is connected to one input terminal of the OR gate OR1, the other input terminal of the OR gate OR1 inputs a scan enable signal SE, an output terminal of the OR gate OR1 is connected to a D terminal of the general register DFF1, AND a Q terminal of the general register DFF1 is connected to one input terminal of the AND gate 1. The D terminal AND the Q terminal of the scan register scan _ ff2 are connected, the Q terminal of the scan register scan _ ff2 is connected to one input terminal of an OR gate OR2, the other input terminal of the OR gate OR2 inputs a scan enable signal SE, AND the output terminal of the OR gate OR2 is connected to the other input terminal of an AND gate AND 1. The output terminal of the AND gate AND1 is connected to one input terminal of the OR gate OR 3. An output of the OR gate OR1 is connected to another input of the OR gate OR 3. The output terminal of the OR gate OR3 is used to output the clock test enable signal TE.

When the scan test of the first mode (ELS mode) is performed on the clock area, the clock test enable unit PTE _ STRUC operates as follows.

When the shift stage is last shifted (i.e. beat 4 in fig. 4), the scan enable signal SE is "1", and passes through two stages of OR gates OR1 and OR3, the value of TE is "1", and the shift stage scan _ clk must be clocked. At this time, data "0" into which scan _ ff1 is shifted and data "1" into which scan _ ff2 is shifted.

When extra shift (i.e., beat 5 in fig. 4), scan enable SE is "0", scan _ ff1 captures data "0" that was last shifted in, so OR gate OR1 comes out as "0", and register DFF1 comes out as "1"; scan _ ff2 captures the last shifted-in data "1", so OR gate OR2 comes out as "1"; the TE signal is also "1" at this time, ensuring that the extra shift stage scan _ clk must be clocked.

When capture (i.e., the second beat of the fast clock in fig. 4), scan enable SE is "0", scan _ ff1 holds data "0", register DFF1 captures data "0" of OR gate OR1 at the fifth beat, and scan _ ff2 holds data "1". The TE signal is "0" at this time, and the corresponding function path of the enable terminal (EN) of the ICG can be tested at this time.

When the second mode (LOC mode) scan test is performed on the clock region, the clock test enable unit PTE _ STRUC operates as follows.

When the shift phase is the last shift (i.e., beat 4 in fig. 5), scan enable SE is "1", and TE is "1" through two stages of OR gates OR1 and OR3, and scan _ clk must be clocked. At this time, data "0" into which scan _ ff1 is shifted and data "0" into which scan _ ff2 is shifted.

When launch (i.e., beat 5 in fig. 5), scan enable SE is "0", scan _ ff1 captures the data "0" that was last shifted in, so OR gate OR1 comes out as "0", and register DFF1 comes out as "1"; scan _ ff2 captures the last shifted-in data "0", so OR gate OR2 comes out as "0", at which time the TE signal is "0", at which time the scan clock is controlled by the enable signal in the active state.

When capture (i.e., the second beat of the fast clock in fig. 5), scan enable SE is "0", scan _ ff1 holds data "0", register DFF1 captures data "0" of OR gate OR1 at the fifth beat, and scan _ ff2 holds data "0". At this time, the TE signal is "0", and at this time, the function path corresponding to the function enable terminal (EN) of the ICG may be tested.

Referring to fig. 4, analyzing ELS process, it can be seen that the pipeline scan enable signal PSE entering the scan test clock region needs to be switched from "1" to "0" in two beats of the fast clock.

Alternatively, a structural form of the pipeline scan enabling unit PSE _ STRUC is shown in fig. 8, and the pipeline scan enabling unit PSE _ STRUC includes: two scan registers scan _ ff3 AND scan _ ff4, a one-out-of-four multiplexer MUX, a general register DFF2, an AND gate AND2, AND an OR gate OR 4. Two scan registers scan _ ff3 and scan _ ff4 are used to set the test mode, the D terminal of scan _ ff3 is connected to the Q terminal, the D terminal of scan _ ff4 is connected to the Q terminal, the scan input terminals of scan _ ff3 and scan _ ff4 are shifted in scan data, and the Q terminal is used to output the test mode signal. The test mode signal is input to the select terminal S of the multiplexer MUX, the scan register scan _ ff3 is used to provide the ELS test mode enable signal (ELS), and the scan register scan _ ff4 is used to provide the LOC test mode enable signal (LOC). The select terminal of the multiplexer MUX is controlled by an ELS test mode enable signal (ELS) and a LOC test mode enable signal (LOC). The output of the multiplexer MUX is connected to one input of an AND gate AND 2. The scan enable signal SE is input to the D terminal of the general register DFF2, AND the Q terminal of the general register DFF2 is connected to the other input terminal of the AND gate AND 2. An output terminal of the AND gate AND2 AND one input terminal of the OR gate OR4 are connected, AND the scan enable signal SE is input to the other input terminal of the OR gate OR 4. The output of OR gate OR4 is used to output the pipeline scan enable signal PSE.

The above embodiment sets the test mode by two scan registers scan _ ff3 and scan _ ff4, scan _ ff3 shifts into "1" and scan _ ff4 shifts into "0" as the first mode, scan _ ff3 shifts into "0" and scan _ ff4 shifts into "1" as the second mode, the output of the MUX is "1" in the first mode and "0" in the second mode.

When the first mode (ELS mode) scan test is performed on the clock area, the operation of the pipeline scan enable unit PSE _ STRUC is as follows.

When performing the ELS mode test, ELS is "1" and LOC is "0" during the shift phase, after which the multiplexer MUX output remains "1".

When the shift stage is shifted for the last time (i.e. beat 4 in fig. 4), the scan enable signal SE is "1", and the pipeline scan enable signal PSE entering the region to be scanned is "1" through the OR gate OR4, so that the shift operation can be performed on the clock region.

When extra shift (i.e. beat 5 in fig. 4), scan enable signal SE jumps to "0", the output of general register DFF2 still holds data "1" of the previous beat when the rising edge comes, AND after passing through AND gate (AND2) OR gate (OR4), scan enable signal PSE entering the clock region still remains "1" when the rising edge of the clock occurs, so that the clock region can be shifted with fast clock.

When capture (i.e., the second beat of the fast clock in fig. 4), scan enable SE is "0", the output of general register DFF2 has settled to "0", AND after passing through AND gate (AND2) OR gate (OR4), scan enable signal PSE entering the clock region becomes "0", so that the capture operation can be performed on the clock region with the fast clock.

When the scan test of the second mode (LOC mode) is performed on the clock area, the operation of the pipeline scan enable unit PSE _ STRUC is as follows.

When the LOC mode test is performed, ELS is "0" and LOC is "1" during the shift phase, after which the multiplexer MUX output remains "0".

The output of the multiplexer is "0" AND thus the output of AND gate AND2 is "0", at which time the output PSE of OR gate OR4 coincides with the SE signal.

When the shift phase is the last shift (i.e., beat 4 in fig. 5), PSE is 1, a shift operation may be performed.

When launch (i.e., beat 5 in FIG. 5), PSE is 0, a propagation may be initiated from the register.

When capture (i.e., the second beat of the fast clock in FIG. 5), PSE is 0, the register can capture the data at the D terminal.

Further, the real-time scan test control circuit in the above embodiment is for one Clock Domain, and for the whole test Domain, the whole test is divided into several Clock domains, Clock Domain1, Clock Domain2, … … Clock Domain. The real-time scanning test control circuit in the whole test area is subjected to corresponding structural expansion, as shown in fig. 9.

The scanning clock and the pipeline scanning enabling signal of each stage of the real-time scanning test method can be realized through the control circuit.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A real-time scan test method for real-time scan testing of a clock region, wherein the clock region includes a plurality of scan chains, and each scan chain flexibly controls scan enable via a pipeline scan enable signal, the method comprising:

sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock, so that the slow clock is adopted in the process of shifting the data into the scanning chains;

adopting a fast clock to additionally shift in the scan registers on each scan chain with data once after the process of shifting in the data is finished;

triggering the propagation of each scan chain by adopting a quick clock;

2. A real-time scan test method for real-time scan testing of an entire test area, wherein the entire test area includes a plurality of clock areas, each clock area having a different clock, each clock area including a plurality of scan chains, each scan chain flexibly controlling scan enable via a pipeline scan enable signal, the method comprising:

2-1) appointing a clock area as a current target clock area, adopting a first mode to carry out real-time scanning test on the current target clock area, and adopting a second mode to carry out real-time scanning test on other clock areas except the current target clock area;

2-2) sequentially appointing each clock area as a current target clock area, and repeatedly executing the step 2-1);

wherein, the real-time scanning test of the current target clock area by adopting the first mode comprises the following steps:

the performing real-time scanning test on other clock regions except the current target clock region by adopting the second mode comprises the following steps:

triggering the propagation of each scan chain by adopting a quick clock;

3. A real-time scan test control circuit, comprising:

a pipeline scan enable unit for outputting a pipeline scan enable signal in the first mode or the second mode according to a test mode of the clock region, the test mode including a first mode and a second mode, wherein the test step of the first mode includes: sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock, so that the slow clock is adopted in the process of shifting the data into the scanning chains; adopting a fast clock to additionally shift in the scan registers on each scan chain with data once after the process of shifting in the data is finished; loading the excitation to the input end of each scan chain, and capturing the test output value of each scan chain by adopting a quick clock; the testing step of the second mode comprises: sequentially shifting data into the scanning registers on each scanning chain by adopting a slow clock; triggering the propagation of each scan chain by adopting a quick clock; loading the excitation to the input end of each scan chain, and capturing the test output value of each scan chain by adopting a quick clock; the pipeline scanning enabling signal output by the pipeline scanning enabling unit is effective when data is shifted in a first mode, is effective when data is additionally shifted in, and is ineffective when the data is captured, and is effective when the data is shifted in a second mode, is ineffective when the data is triggered and is ineffective when the data is captured, and the pipeline scanning enabling signal is input into each scanning chain in a clock area;

4. The circuit of claim 3, wherein the clock test enable unit comprises: a first scan register, a second scan register, a first general register, a first OR gate, a second OR gate, a third OR gate, and a first AND gate,

5. The circuit of claim 3, wherein the pipeline scan enable unit comprises: a third scan register, a fourth scan register, a multiplexer, a second general register, a second AND gate, and a fourth OR gate,

a D end of the third scanning register is connected with a Q end of the third scanning register, a D end of the fourth scanning register is connected with a Q end of the fourth scanning register, scanning data are shifted into scanning input ends of the third scanning register and the fourth scanning register, and the Q end is connected with a selection end of the multiplexer;

6. The circuit of claim 5, wherein the third scan register and the fourth scan register are used to set a test mode, the third scan register is shifted in to "1" and the fourth scan register is shifted in to "0", and the test mode is set to a first mode; the third scan register is shifted to "0" and the fourth scan register is shifted to "1", and the test mode is set to the second mode.

7. The circuit of claim 5, wherein the output of the multiplexer is a "1" in the first mode and a "0" in the second mode.