CN103904110A - Depletion type insulated gate AlGaN / GaN component structure with gate field plate and manufacturing method of depletion type insulated gate AlGaN / GaN component structure - Google Patents

Depletion type insulated gate AlGaN / GaN component structure with gate field plate and manufacturing method of depletion type insulated gate AlGaN / GaN component structure Download PDF

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CN103904110A
CN103904110A CN201410025002.6A CN201410025002A CN103904110A CN 103904110 A CN103904110 A CN 103904110A CN 201410025002 A CN201410025002 A CN 201410025002A CN 103904110 A CN103904110 A CN 103904110A
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algan
gan
layer
field plate
grid
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CN103904110B (en
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冯倩
杜锴
代波
张春福
梁日泉
郝跃
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Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/404Multiple field plate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention discloses a depletion type insulated gate AlGaN / GaN component structure with a gate field plate and a manufacturing method of the depletion type insulated gate AlGaN / GaN component structure. The structure comprises a substrate, an intrinsic GaN layer, an AlN isolation layer, an intrinsic AlGaN layer, an AlGaN doping layer, a gate electrode, a source electrode, a drain electrode, the gate field plate, an insulation layer, a passivation layer and silicide used for adjusting an electric field of a channel. The AlGaN doping layer is located on the upper portion of the intrinsic AlGaN layer, the electrodes and the insulation layer are located on the upper portion of the AlGaN layer, and the silicide is located on the upper portion of the insulation layer. A depletion type AlGaN / GaN heterojunction material is arranged on the substrate in an epitaxial growth mode, the source electrode and the drain electrode are formed on the structure, then the insulation layer is deposited, the gate electrode is formed on the insulation layer, the silicide such as NiSi and TiSi2 is formed on the insulation layer between the gate drain area and the gate source area, the silicide on the thick insulation layer is electrically connected with the gate electrode to form a gate field plate structure, the passivation layer is deposited at last, and passivation of the component is achieved. The structure and the manufacturing method have the advantages of being high in component frequency, process repeatability and controllability.

Description

Add grid field plate depletion type insulated gate AlGaN/GaN device architecture and preparation method thereof
Technical field
The invention belongs to microelectronics technology, relating to semiconductor device makes, one adds grid field plate depletion-mode AlGaN/GaN HEMT device architecture and manufacture method, the depletion high electron mobility transistors that can be used for making low on-resistance, high-frequency, high-breakdown-voltage specifically.
Background technology
The 3rd bandwidth bandgap semiconductor take SiC and GaN as representative is large with its energy gap in recent years, breakdown electric field is high, thermal conductivity is high, saturated electrons speed is large and the characteristic such as heterojunction boundary two-dimensional electron gas height, makes it be subject to extensive concern.In theory, utilize the devices such as high electron mobility transistor (HEMT) that these materials make, LED, laser diode LD to there is obvious advantageous characteristic than existing device, therefore researcher has carried out extensive and deep research to it both at home and abroad in the last few years, and has obtained the achievement in research attracting people's attention.
AlGaN/GaN heterojunction high electron mobility transistor (HEMT) is demonstrating advantageous advantage aspect high-temperature device and HIGH-POWERED MICROWAVES device, and pursuit device high-frequency, high pressure, high power have attracted numerous research.In recent years, make higher frequency high pressure AlGaN/GaN HEMT and become the another study hotspot of concern.Due to after AlGaN/GaN heterojunction grown, just there are a large amount of two-dimensional electron gas 2DEG in heterojunction boundary, and in the time of the resistivity decreased of interface, we can obtain higher device frequency characteristic.AlGaN/GaN heterojunction electron mobility transistor can obtain very high frequency, but often will be to sacrifice high pressure resistant property as cost.The method of the AlGaN/GaN heterojunction transistor frequency improving is at present as follows:
1. in conjunction with reducing resistivity without passivated dielectric medium (dielectric-free passivation) and the long ohmic contact of living again.Referring to Yuanzheng Yue, Zongyang Hu, the InAlN/AlN/GaN HEMTs With Regrown Ohmic Contacts andf_{T}of370GH such as Jia Guo.EDL.Vol33.NO.7,P1118-P1120。The method has adopted 30 nanometer grid long, and in conjunction with reducing source ohmic leakage rate without passivated dielectric medium (dielectric-free passivation) and the long ohmic contact of living again.Frequency can reach 370GHz.Can also continue to improve frequency to 500GHz by reducing channel length.
2. the long heavy-doped source of living again drains to the Two-dimensional electron gas channel of nearly grid.Referring to Shinohara, K.Regan, D.Corrion, the self-aligned-gate GaN-HEMTs with heavily-doped n+-GaN ohmic contacts to2DEG such as A.Brown; IEDM, IEEE; 2012.The long n+GaN ohmic contact of living again in the past achieves noticeable achievement to reducing raceway groove contact resistance, but heavy-doped source drain contact directly can obtain better frequency characteristic and current characteristics to the Two-dimensional electron gas channel approaching under grid.The method of reporting in literary composition makes frequency reach f t/ fmax=342/518GHz.Puncture voltage 14V simultaneously.
Summary of the invention
The object of the invention is to the deficiency for above high-frequency device, a kind of method that based on silicide, raceway groove is produced stress is provided, to improve the transistorized frequency characteristic voltage endurance of depletion-mode AlGaN/GaN high mobility simultaneously, the controllability and the repeatability that strengthen technique, meet GaN base electron device to high-frequency, high-tension application requirements.
The present invention is achieved in that
Technical thought of the present invention is: use the method for epitaxial growth the etching insulating barrier of growing on AlGaN, generate a step-like thick thin dielectric layer by etching, multiple bulk silicon compounds of growing on thin dielectric layer again, silicide agglomeration spacing is less than piece width, the Formation of silicide field plate be connected in grid of also growing in thick dielectric layer.Because the thermal coefficient of expansion of silicide is greater than the thermal coefficient of expansion of insulating barrier and AlGaN.In the time that epitaxial growth is cooling, silicide can be introduced compression to insulating barrier and AlGaN layer, and meanwhile, the AlGaN layer between silicide will be subject to tensile stress.In the time that AlGaN layer is subject to compression, the 2DEG concentration that is positioned at AlGaN/GaN interface reduces to some extent, and in the time that AlGaN layer is subject to tensile stress, the 2DEG concentration that is positioned at AlGaN/GaN interface increases to some extent.The size of AlGaN layer institute compression chord (tensile stress) is relevant with the length of silicide (silicide spacing), this relation is not a kind of linear relationship, but in the time that operating distance reduces the suffered stress of AlGaN layer on the impact of polarization charge increase sharply (being illustrated in fig. 2 shown below), so we can make the width of silicide, spacing difference between silicide realizes the adjusting of two-dimensional electron gas, the increase of 2DEG concentration still reduces the magnitude relationship that depends on the two on the whole, in this invention, we select to make two-dimensional electron gas increase reduce channel resistance.So tensile stress is greater than compression, so silicide width is less than silicide spacing.As shown in the figure, if the width of silicide is 1 μ m, silicide spacing is 0.25 μ m,. (0.25 μ m) the tension force effect that stands in region makes polarization charge finally than large two orders of magnitude of the polarization charge of silicide regions (1um) to silicide spacing so, so effect on the whole shows as AlGaN layer, to be subject to tensile stress be that polarization charge concentration increases to some extent, thereby the concentration of 2DEG also presents the result that entirety increases because of the increase of polarization charge between grid source and between grid leak.Therefore the resistance in this region reduces to some extent.Referring to IEICE TRANS.ELECTON, VOL.E93-C, NO.8AUGUST2010.Analysis of Passivation-Film-Induced Stress Effects on Electrical Properties in AlGaN/GaN HEMTs. makes spacing between silicide be less than the length of silicide by selection, the growth that makes 2DEG concentration reduces much larger than 2DEG concentration, thereby the resistance between grid leak and grid source is reduced to some extent, in the situation that not changing grid leak spacing, improve the transistorized frequency characteristic of high mobility.Field plate in thick dielectric layer, because medium is thicker, can be ignored the impact of 2DEG, but is connected in the effect that can play field plate after grid, can improve voltage endurance of the present invention.
According to above-mentioned technical thought, device of the present invention comprises substrate, intrinsic GaN layer, AlN separator, AlGaN barrier layer (intrinsic AlGaN layer), AlGaN doped layer, gate electrode, source electrode, drain electrode, grid field plate, insulating barrier, passivation layer and for regulating the silicide of raceway groove electric field.AlGaN doped layer is positioned on barrier layer, and electrode and insulating barrier are positioned on AlGaN layer, and silicide is positioned on insulating barrier.Epitaxial growth depletion-mode AlGaN/GaN heterojunction material on substrate, and in this structure, form source electrode and drain electrode, then deposit one layer insulating, on insulating barrier, form grid, finally on insulating barrier (between grid leak region and grid source region), form silicide (NiSi, TiSi2 etc.), the silicide in thick dielectric layer is electrically connected with grid and forms grid field plate structure.Last deposit passivation layer is realized the passivation of device.Thereby electron gas concentration and electric field in raceway groove are played to regulating action, and the voltage endurance capability of device also strengthens.Thereby improve transistorized frequency characteristic and voltage endurance.
According to above-mentioned technical thought, utilize metal silicide to improve the structure of AlGaN/GaN HEMT device performance, comprise the steps:
(1) epitaxially grown AlGaN/GaN material is carried out to organic washing, by mobile washed with de-ionized water and put into HCl: H 2o=1: corrode 30-60s in 1 solution, finally dry up by mobile washed with de-ionized water and with high pure nitrogen
(2) the AlGaN/GaN material cleaning up is carried out to photoetching and dry etching, be formed with source region table top;
(3) the AlGaN/GaN material for preparing table top is carried out to photoetching, form source-drain area, put into electron beam evaporation platform deposit metal ohmic contact Ti/Al/Ni/Au=(20/120/45/50nm) and peel off, the last rapid thermal annealing that carries out 850 ℃ of 35s in nitrogen environment, forms ohmic contact
(4) device is put into magnetron sputtering reative cell and prepared Al 2o 3film, process conditions are: the DC offset voltage of Al target is 100V, Ar throughput is 30sccm, O 2flow is 10sccm, and the pressure of reative cell is 0.5Pa, the Al that deposit 300nm is thick 2o 3film;
(5) device that completes deposit is carried out to photoetching development, form Al 2o 3the wet etching district of film, puts into 1 by material: 10=HF: H 2in the solution of O, corrosion 3min~5min, by Al 2o 3corrode to 5-10nm;
(6) then device is put into simultaneously sputter Ni and the Si of reative cell of magnetron sputtering, process conditions are: the DC offset voltage of Ni target is 100V, the rf bias voltage of Si target is 450V, and the flow of carrier gas Ar is 30sccm, the hybrid metal film that codeposition 100nm~150nm is thick
(7) device of the good film of deposit is carried out to photoetching, form the etching window district of mixed film, and put into ICP dry etching reative cell, process conditions are: upper electrode power is 200W, and lower electrode power is 20W, and chamber pressure is 1.5Pa, CF 4flow be 20sccm, the flow of Ar gas is 10sccm, etch period is 5min;
(8) device is put into quick anneal oven, carry out 450 ℃ under nitrogen environment, the rapid thermal annealing of 30s, forms NiSi alloy
(9) device that completes alloy is carried out to photoetching, form gate electrode and grid field plate region, then put into electron beam evaporation platform deposit Ni/Au=20/200nm and peel off, complete the preparation of gate electrode and grid field plate
(10) put into PECVD equipment deposit SiN film by completing device prepared by gate electrode, concrete technology condition is: SiH 4flow be 40sccm, NH 3flow be 10sccm, chamber pressure is 1~2Pa, radio-frequency power is 40W, the SiN passivating film that deposit 200nm~300nm is thick
(11) device is cleaned again, photoetching development, form the etched area of SiN film, and put into ICP dry etching reative cell, process conditions are: upper electrode power is 200W, lower electrode power is 20W, chamber pressure is 1.5Pa, CF 4flow be 20sccm, the flow of Ar gas is 10sccm, etch period is 10min, the SiN that source electrode, drain and gate are covered above and Al 2o 3film etches away;
(12) device is cleaned, photoetching development, and put into the thick electrode that adds of electron beam evaporation platform deposit Ti/Au=20/200nm, complete the preparation of integral device.
Tool of the present invention has the following advantages:
(1) device of the present invention adopts the method for deposition insulating layer and silicide, and AlGaN is produced to effect of stress, regulates electron gas concentration and electric field strength in raceway groove.Improve device frequency characteristic.
(2) in the present invention, prepared silicide, between grid leak and grid source, does not need to reduce grid leak distance when improving frequency characteristic, thereby without sacrificing high pressure resistant property.
(3) in the present invention owing to can regulate as required size and the spacing of silicide between grid leak and grid source, thereby regulate effect of stress size.Electron gas concentration and frequency characteristic can regulate as required between grid source and between grid leak.
(4) in the present invention grid field plate add the puncture voltage that has improved device.
(5) in the present invention, adopt insulated gate structure, greatly reduced grid leakage current.
Accompanying drawing explanation
By describing in more detail exemplary embodiment of the present invention with reference to accompanying drawing, above and other aspect of the present invention and advantage will become more and be readily clear of, in the accompanying drawings:
Fig. 1 is the cross-sectional view of device of the present invention;
Fig. 2 is physical principle key diagram (polarization charge is with the variation of silicide width);
Fig. 3 is the fabrication processing schematic diagram of device of the present invention.
Embodiment
Hereinafter, now with reference to accompanying drawing, the present invention is described more fully, various embodiment shown in the drawings.But the present invention can implement in many different forms, and should not be interpreted as being confined to embodiment set forth herein.On the contrary, it will be thorough with completely providing these embodiment to make the disclosure, and scope of the present invention is conveyed to those skilled in the art fully.
Hereinafter, exemplary embodiment of the present invention is described with reference to the accompanying drawings in more detail.
With reference to Fig. 1, device of the present invention comprises substrate, intrinsic GaN layer, AlN separator, AlGaN barrier layer (intrinsic AlGaN layer), AlGaN doped layer, gate electrode, source electrode, drain electrode, grid field plate, insulating barrier, passivation layer and for regulating the silicide of raceway groove electric field.AlGaN doped layer is positioned on barrier layer, and electrode and insulating barrier are positioned on AlGaN layer, and silicide is positioned on insulating barrier.Epitaxial growth depletion-mode AlGaN/GaN heterojunction material on substrate, and in this structure, form source electrode and drain electrode, then deposit one layer insulating, on insulating barrier, form grid, finally on insulating barrier (between grid leak region and grid source region), form silicide (NiSi, TiSi 2etc.), the silicide in thick dielectric layer is electrically connected with grid and forms grid field plate structure.Last deposit passivation layer is realized the passivation of device.
The foregoing is only embodiments of the invention, be not limited to the present invention.The present invention can have various suitable changes and variation.All any modifications of doing within the spirit and principles in the present invention, be equal to replacement, improvement etc., within protection scope of the present invention all should be included in.

Claims (10)

1. add a grid field plate depletion type insulated gate AlGaN/GaN device architecture, it is characterized in that: described structure comprises substrate, intrinsic GaN layer, AlN separator, intrinsic AlGaN layer, AlGaN doped layer, gate electrode, source electrode, drain electrode, grid field plate, insulating barrier, passivation layer and for regulating the silicide of raceway groove electric field; Described AlGaN doped layer is positioned on intrinsic AlGaN layer, and electrode and insulating barrier are positioned on AlGaN layer, and silicide is positioned on insulating barrier; Epitaxial growth depletion-mode AlGaN/GaN heterojunction material on substrate, and on this heterojunction material, form source electrode and drain electrode, then deposit one layer insulating, on insulating barrier, form grid, between last grid leak region and grid source region on insulating barrier, form silicide, the silicide in thick dielectric layer is electrically connected with grid and forms grid field plate structure, last deposit passivation layer is realized the passivation of device.
2. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: backing material is wherein sapphire, carborundum, GaN or MgO.
3. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: in AlGaN wherein, the component of Al and Ga can regulate, Al xga 1-xx=0~1 in N.
4. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: silicide comprises NiSi, TiSi 2, or Co 2si.
5. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: the thickness of thin dielectric layer is 5~10nm, and thick dielectric layer thickness is 200~700nm.
6. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: its GaN raceway groove replaces with Al yga 1-yn raceway groove, and Al yga 1-yin N, the component of y is less than the Al component x in addition two-layer, i.e. x>y.
7. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized by: the silicide being positioned in thick dielectric layer is electrically connected formation grid field plate structure with grid, improve the puncture voltage of device.
8. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized by: grid adopts insulated gate structure, has reduced grid leakage current.
9. the grid field plate depletion type insulated gate AlGaN/GaN device architecture that adds according to claim 1, is characterized in that: its insulating barrier and passivation layer comprise SiN, Al 2o 3, HfO 2, the insulating material such as HfSiO.
10. the manufacture method based on adding grid field plate depletion type insulated gate AlGaN/GaN device architecture, comprises the steps:
Utilize metal silicide to improve the structure of AlGaN/GaN MISHEMT device performance, comprise following process:
(1) epitaxially grown AlGaN/GaN material is carried out to organic washing, by mobile washed with de-ionized water and put into HCl: H 2o=1: corrode 30-60s in 1 solution, finally dry up by mobile washed with de-ionized water and with high pure nitrogen;
(2) the AlGaN/GaN material cleaning up is carried out to photoetching and dry etching, be formed with source region table top;
(3) the AlGaN/GaN material for preparing table top is carried out to photoetching, form source-drain area, put into electron beam evaporation platform deposit metal ohmic contact Ti/Al/Ni/Au=(20/120/45/50nm) and peel off, the last rapid thermal annealing that carries out 850 ℃ of 35s in nitrogen environment, forms ohmic contact;
(4) device is put into magnetron sputtering reative cell and prepared Al 2o 3film, process conditions are: the DC offset voltage of Al target is 100V, Ar throughput is 30sccm, O 2flow is 10sccm, and the pressure of reative cell is 0.5Pa, the Al that deposit 300nm is thick 2o 3film;
(5) device that completes deposit is carried out to photoetching development, form Al 2o 3the wet etching district of film, puts into 1 by material: 10=HF: H 2in the solution of O, corrosion 3min~5min, by Al 2o 3corrode to 5-10nm;
(6) then device is put into simultaneously sputter Ni and the Si of reative cell of magnetron sputtering, process conditions are: the DC offset voltage of Ni target is 100V, the rf bias voltage of Si target is 450V, and the flow of carrier gas Ar is 30sccm, the hybrid metal film that codeposition 100nm~150nm is thick;
(7) device of the good film of deposit is carried out to photoetching, form the etching window district of mixed film, and put into ICP dry etching reative cell, process conditions are: upper electrode power is 200W, and lower electrode power is 20W, and chamber pressure is 1.5Pa, CF 4flow be 20sccm, the flow of Ar gas is 10sccm, etch period is 5min;
(8) device is put into quick anneal oven, carry out 450 ℃ under nitrogen environment, the rapid thermal annealing of 30s, forms NiSi alloy;
(9) device that completes alloy is carried out to photoetching, form grid and grid field plate region, then put into electron beam evaporation platform deposit Ni/Au=20/200nm and peel off, complete the preparation of gate electrode and grid field plate;
(10) put into PECVD equipment deposit SiN film by completing device prepared by gate electrode, concrete technology condition is: SiH 4flow be 40sccm, NH 3flow be 10sccm, chamber pressure is 1~2Pa, radio-frequency power is 40W, the SiN passivating film that deposit 200nm~300nm is thick;
(11) device is cleaned again, photoetching development, form the etched area of SiN film, and put into ICP dry etching reative cell, process conditions are: upper electrode power is 200W, lower electrode power is 20W, chamber pressure is 1.5Pa, CF 4flow be 20sccm, the flow of Ar gas is 10sccm, etch period is 10min, the SiN that source electrode, drain and gate are covered above and Al 2o 3film etches away;
(12) device is cleaned, photoetching development, and put into the thick electrode that adds of electron beam evaporation platform deposit Ti/Au=20/200nm, complete the preparation of integral device.
CN201410025002.6A 2014-01-20 2014-01-20 Add grid field plate depletion type insulated gate AlGaN/GaN device architecture and preparation method thereof Expired - Fee Related CN103904110B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106549039A (en) * 2016-11-03 2017-03-29 浙江大学 A kind of Low Power High Performance germanium raceway groove quantum well field effect transistor
WO2018149029A1 (en) * 2017-02-17 2018-08-23 昆山华太电子技术有限公司 Method for manufacturing hemt with high reliability

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US20070235775A1 (en) * 2006-03-29 2007-10-11 Cree, Inc. High efficiency and/or high power density wide bandgap transistors
CN101414633A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Groove insulated gate type composite gate field plate device with high electron mobility
CN101414626A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Insulated gate type gate-leakage composite field plate power device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235775A1 (en) * 2006-03-29 2007-10-11 Cree, Inc. High efficiency and/or high power density wide bandgap transistors
CN101414633A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Groove insulated gate type composite gate field plate device with high electron mobility
CN101414626A (en) * 2008-12-01 2009-04-22 西安电子科技大学 Insulated gate type gate-leakage composite field plate power device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106549039A (en) * 2016-11-03 2017-03-29 浙江大学 A kind of Low Power High Performance germanium raceway groove quantum well field effect transistor
WO2018149029A1 (en) * 2017-02-17 2018-08-23 昆山华太电子技术有限公司 Method for manufacturing hemt with high reliability

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