CN103745993B - Based on the AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof of superjunction - Google Patents
Based on the AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof of superjunction Download PDFInfo
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- CN103745993B CN103745993B CN201410030986.7A CN201410030986A CN103745993B CN 103745993 B CN103745993 B CN 103745993B CN 201410030986 A CN201410030986 A CN 201410030986A CN 103745993 B CN103745993 B CN 103745993B
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- 229910002704 AlGaN Inorganic materials 0.000 title claims abstract description 120
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000005036 potential barrier Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 55
- 238000001259 photo etching Methods 0.000 claims description 27
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- 229910052733 gallium Inorganic materials 0.000 claims description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005566 electron beam evaporation Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses a kind of AlGaN/GaNMISHEMT high tension apparatus based on superjunction and preparation method thereof, the structure of high tension apparatus comprises substrate, GaN resilient coating, intrinsic GaN(or AlGaN from bottom to up successively) channel layer, AlN separator and AlGaN potential barrier, AlGaN potential barrier has source electrode, grid, drain electrode, linear AlGaN layer, Gate source field plate, P type GaN(or InGaN) layer, base stage, be also provided with insulating medium layer between grid and AlGaN potential barrier.Usefulness of the present invention is: during break-over of device, first area, second area and four-range 2DEG concentration increase, and resistance reduces, and reaches the object reducing device on-resistance; During device cut-off, the 2DEG of first area reduces, and second area is identical with during break-over of device with the 2DEG in the 3rd region, adds the width of device depletion region, reaches the object improving device electric breakdown strength; Grid source field plate ensure that peak electric field there will not be at the boundary of grid near source, improves puncture voltage; Insulated gate structure avoids gate leakage current, improves device performance.
Description
Technical field
The present invention relates to a kind of high tension apparatus and preparation method thereof, be specifically related to a kind of based on the AlGaN/GaNMISHEMT high pressure of superjunction, the high tension apparatus of low on-resistance and preparation method thereof, can be used for the AlGaN/GaN High Electron Mobility Transistor making high pressure low on-resistance, belong to microelectronics technology.
Background technology
, the characteristic such as breakdown electric field high, thermal conductivity high, saturated electrons speed large and heterojunction boundary two-dimensional electron gas high large with its energy gap with SiC and the GaN third generation broad stopband gap semiconductor that is representative, is subject to extensive concern in recent years.In theory, the device such as high electron mobility transistor (HEMT), LED, laser diode LD utilizing these materials to make has obvious advantageous characteristic than existing device, therefore researcher has carried out extensive and deep research to it both at home and abroad in the last few years, and achieves the achievement in research attracted people's attention.
AlGaN/GaN heterojunction high electron mobility transistor (HEMT) has shown advantageous advantage in high-temperature device and HIGH-POWERED MICROWAVES device, and pursuit device high-frequency, high pressure, high power have attracted numerous research.In recent years, the another study hotspot that higher frequency high pressure AlGaN/GaNHEMT becomes concern is made.After AlGaN/GaN heterojunction grown, just there is a large amount of two-dimensional electron gas 2DEG in heterojunction boundary, and its mobility is very high, and therefore we can obtain higher device frequency characteristic.In raising AlGaN/GaN heterojunction electron mobility transistor puncture voltage, people have carried out large quantifier elimination, find that puncturing of AlGaN/GaNHEMT device mainly occurs in grid by drain terminal, therefore the puncture voltage of device will be improved, the electric field redistribution in grid leak region must be made, especially reduce the electric field of grid by drain terminal, for this reason, there has been proposed the method adopting field plate structure:
1. adopt field plate structure.See YujiAndo, AkioWakejima, the NovelAlGaN/GaNdual-field-plateFETwithhighgain of YasuhiroOkamoto etc., increasedlinearityandstability, IEDM2005, pp.576-579,2005(mono-kind has two field plate field-effect transistors of high-gain, high linearity and stability).In AlGaN/GaNHEMT device, adopt grid field plate and source field plate structure simultaneously, the puncture voltage of device is adopted the 250V after two field plate from adopting separately the 125V of grid field plate to bring up to, and reduces gate leakage capacitance, improve the linearity and the stability of device.
2. employing super-junction structures.See AkiraNakajima, the GaNbasedsuperheterojunctionfieldeffecttransistorsusingth epolarizationjunctionconcept(mono-kind of YasunobuSumida, MaheshH utilizes the superjunction field-effect transistor based on GaN of polarization knot).Have 2DEG and 2DEH in this device architecture simultaneously, when grid forward bias, there is not any change in the concentration of 2DEG, therefore the conducting resistance of device can not increase, when gate backbias, 2DEG in raceway groove can exhaust due to electric discharge, thus improves the puncture voltage (being increased to 560V from 110V) of device, and conducting resistance is 6.1m Ω cm
2.
But all there is the larger weak point of conducting resistance in the high tension apparatus with above-mentioned two kinds of structures.
Summary of the invention
For solving the deficiencies in the prior art, the object of the present invention is to provide and a kind ofly meet the AlGaN/GaNMISHEMT high-voltage device structure based on superjunction that the application of high pressure, low on-resistance is required, and there is this method based on the AlGaN/GaNMISHEMT high tension apparatus of superjunction of making of good controllability and repeatability.
In order to realize above-mentioned target, the present invention adopts following technical scheme:
A kind of AlGaN/GaNMISHEMT high tension apparatus based on superjunction, it is characterized in that, comprise successively from bottom to up: substrate, GaN resilient coating, intrinsic AlGaN or GaN channel layer, AlN separator and AlGaN potential barrier, AlGaN potential barrier has in the horizontal direction successively: source electrode, grid and drain electrode, Zone Full above AlGaN potential barrier between source electrode and grid, the linear AlGaN layer of subregion extension above AlGaN potential barrier between grid and drain electrode, aforementioned grid also extends to form the Gate source field plate contacted with linear AlGaN layer upper surface to source electrode direction, also insulating medium layer is provided with between grid and AlGaN potential barrier, linear AlGaN layer between grid and drain electrode and leave gap between drain electrode and in linear AlGaN layer, extension has P type GaN or InGaN epitaxial loayer, P type GaN or InGaN epitaxial loayer there is the base stage be electrically connected with grid, linear AlGaN layer between grid and drain electrode, the width of P type GaN or InGaN epitaxial loayer reduces successively, aforementioned AlGaN potential barrier is made up of the i type AlGaN layer of lower floor and the N-shaped AlGaN layer on upper strata, the upper surface of aforementioned source electrode, grid, drain electrode and base stage is also formed and adds thick electrode, and the both sides adding thick electrode are all formed with passivation layer.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, aforesaid substrate is sapphire, carborundum, GaN or MgO.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, in aforementioned AlGaN potential barrier, the ratio of component of Al and Ga can regulate, and the component of Al, Ga, N is respectively x, 1-x, 1,1>x>0.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, it is characterized in that, in aforementioned linear AlGaN layer, the component of Al is linearly increased to y by x, and the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively y, 1-y, 1,1>y>x>0.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, it is characterized in that, in aforementioned intrinsic AlGaN channel layer, the component of Al is less than x, and the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively z, 1-z, 1,1>x>z>0.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, aforementioned dielectric dielectric layer is SiN, Al
2o
3or HfO
2.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, aforementioned passivation layer is SiN, Al
2o
3or HfO
2.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, in aforementioned InGaN epitaxial loayer, In component is constant or increase gradually.
The aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, is characterized in that, the linear AlGaN layer between aforementioned grid and drain electrode and gap >=0.5 μm between drain electrode.
Make the method for the aforesaid AlGaN/GaNMISHEMT high tension apparatus based on superjunction, it is characterized in that, comprise the following steps:
(1) organic washing is carried out to the linear AlGaN/AlGaN/GaN material of epitaxially grown p-GaN/, with flowing washed with de-ionized water and put into HCl:H
2carry out corrosion 30-60s in the solution of O=1:1, finally with flowing washed with de-ionized water and dry up with high pure nitrogen;
(2) photoetching and dry etching are carried out to the AlGaN/GaN heterojunction material cleaned up, be formed with region meas;
(3) photoetching is carried out to the AlGaN/GaN heterojunction material preparing table top, form the etched area of P type GaN or InGaN, linear AlGaN layer, put into ICP dry etching reative cell to etch, subregion between grid and drain electrode and P type GaN above grid, source electrode and drain electrode or InGaN epitaxial loayer, linear AlGaN layer are all etched away, forms the 3rd region between grid leak;
(4) photoetching is carried out to device, then put into electron beam evaporation platform deposit metal ohmic contact Ti/Al/Ni/Au=20/120/45/50nm and peel off, in nitrogen environment, finally carrying out the rapid thermal annealing of 850 DEG C of 35s, form ohmic contact;
(5) device preparing ohmic contact is carried out photoetching, form the etched area of P type GaN or InGaN epitaxial loayer, put into ICP dry etching reative cell to etch, by subregion between grid and drain electrode, the P type GaN of Zone Full or InGaN epitaxial loayer etch away between grid source, form first area and second area between grid leak, and the 4th region between grid source;
(6) device preparing ohmic contact is put into atomic layer deposition apparatus, the Al that deposit 5-10nm is thick
2o
3medium, forms insulating medium layer;
(7) photoetching is carried out to the device completing deposit, form the corrosion region of insulating medium layer, then put into HF:H
230s in the solution of O=1:10, erodes the insulating medium layer beyond area of grid;
(8) device prepared is carried out photoetching, form base region, then put into electron beam evaporation platform deposit Ni/Au=20/20nm and peel off, in atmospheric environment, finally carrying out the annealing of 550 DEG C of 10min, form base ohmic contact;
(9) carrying out photoetching to completing device prepared by base stage, forming grid and field plate region, grid source, then put into electron beam evaporation platform deposit Ni/Au=20/200nm and peel off, completing the preparation of grid and grid source field plate;
(10) put into PECVD reative cell deposit SiN passivating film by completing device prepared by grid, the deposition thickness of passivating film is 200nm-300nm;
(11) device is carried out again clean, photoetching development, form the etched area of SiN film, and put into ICP dry etching reative cell and etch, SiN film source electrode, drain and gate covered above etches away;
(12) device is carried out clean, photoetching development, and put into electron beam evaporation platform deposit Ti/Au=20/200nm add thick electrode, complete the preparation of integral device.
Usefulness of the present invention is:
1, between grid leak, between first area, second area and the 3rd region and grid source, four-range is formed and makes: during break-over of device, first area, second area and four-range 2DEG concentration increase, resistance is reduced, and reaches the object reducing device on-resistance; During device cut-off, the 2DEG of first area is reduced, and second area is identical with during break-over of device with the 2DEG in the 3rd region, adds the width of device depletion region, changes Electric Field Distribution, reaches the object improving device electric breakdown strength;
2, the present invention adopts grid source field plate, ensure that peak electric field there will not be at the boundary of grid near source, reaches the object improving puncture voltage;
3, the present invention adopts insulated gate structure (insulating medium layer of grid and below), avoids gate leakage current, improves device performance;
4, method of the present invention, has good controllability and repeatability.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a specific embodiment of high tension apparatus of the present invention;
Fig. 2 is the fabrication processing figure of high tension apparatus of the present invention.
The implication of Reference numeral in figure: 1-substrate, 2-GaN resilient coating, 3-intrinsic GaN channel layer, 4-AlN separator, 5-AlGaN barrier layer, 501-i type AlGaN layer, 502-n type AlGaN layer, 6-source electrode, 7-grid, 8-drains, 9-insulating medium layer, the linear AlGaN layer of 10-, 11-P type GaN epitaxial layer, 12-base stage, 13-Gate source field plate, 14-adds thick electrode, 15-passivation layer, and D1 represents first area, D2 represents second area, D3 represents the 3rd region, D4 represents the 4th region.
Embodiment
Below in conjunction with the drawings and specific embodiments, concrete introduction is done to the present invention.
First, the structure of the AlGaN/GaNMISHEMT high tension apparatus based on superjunction of the present invention is introduced.
With reference to Fig. 1, AlGaN/GaNMISHEMT high tension apparatus based on superjunction of the present invention, its structure comprises from bottom to up successively: substrate 1, GaN resilient coating 2, intrinsic GaN channel layer 3(intrinsic GaN channel layer 3 can also replace with AlGaN channel layer), AlN separator 4 and AlGaN potential barrier 5, AlGaN potential barrier 5 is made up of the i type AlGaN layer 501 of lower floor and the N-shaped AlGaN layer 502 on upper strata, wherein, AlGaN potential barrier 5 has in the horizontal direction successively: source electrode 6, grid 7 and drain electrode 8, the linear AlGaN layer 10 of Zone Full extension above AlGaN potential barrier 5 between source electrode 6 and grid 7, the subregion also linear AlGaN layer 10 of extension above AlGaN potential barrier 5 between grid 7 and drain electrode 8, grid 7 and drain electrode 8 between linear AlGaN layer 10 and drain electrode 8 between leave gap (width >=0.5 μm in gap), and extension has P type GaN epitaxial layer 11 in linear AlGaN layer 10, P type GaN epitaxial layer 11 can also be replaced with InGaN epitaxial loayer, InGaN epitaxial loayer is used if having selected, In component both can constantly also can increase gradually, the base stage 12 that P type GaN epitaxial layer 11 is electrically connected with grid 7 in addition, linear AlGaN layer 10 between grid 7 and drain electrode 8, the width of P type GaN epitaxial layer 11 reduces successively.Grid 7 also extends to form width≤1 μm of field plate 13, Gate source, the Gate source field plate 13 contacted with linear AlGaN layer 10 upper surface to source electrode 6 direction.Also be provided with insulating medium layer 9 between grid 7 and AlGaN potential barrier 5, insulating medium layer 9 is SiN, Al
2o
3or HfO
2.In addition, source electrode 6, grid 7, drain electrode 8 and the upper surface of base stage 12 are also formed and add thick electrode 14, and the both sides adding thick electrode 14 are all formed with passivation layer 15, and passivation layer 15 is SiN, Al preferably
2o
3or HfO
2.
As the preferred scheme of one, substrate 1 is sapphire, carborundum, GaN or MgO.
As the preferred scheme of one, in AlGaN potential barrier 5, the ratio of component of Al and Ga can regulate, and the component of Al, Ga, N is respectively x, 1-x, 1,0<x<1, i.e. Al
xga
1-xn.
More preferably, in linear AlGaN layer 10, the component of Al is linearly increased to y by x, and the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively y, 1-y, 1,1>y>x>0, i.e. Al
yga
1-yn.
Suppose, the thickness of linear AlGaN layer 10 is L, then the distance apart from the lower surface of linear AlGaN layer 10 is L
1the weight content of place Al is: (y-x) × L1/L.
More preferably, in intrinsic AlGaN channel layer, the component of Al is less than x, and the ratio of component of Al and Ga can regulate, and the component of Al, Ga, N is respectively z, 1-z, 1,1>x>z>0, i.e. Al
zga
1-zn.
Next, the method making the above-mentioned AlGaN/GaNMISHEMT high tension apparatus based on superjunction is introduced.
With reference to Fig. 2, this manufacture method comprises the following steps:
1, organic washing is carried out to the linear AlGaN/AlGaN/GaN material of epitaxially grown p-GaN/, with flowing washed with de-ionized water and put into HCl:H
2carry out corrosion 30-60s in the solution of O=1:1, finally with flowing washed with de-ionized water and dry up with high pure nitrogen.
2, photoetching and dry etching are carried out to the AlGaN/GaN heterojunction material cleaned up, be formed with region meas.
3, photoetching is carried out to the AlGaN/GaN heterojunction material preparing table top, form P type GaN(or InGaN) and the etched area of linear AlGaN layer, put into ICP dry etching reative cell to etch, process conditions are: upper electrode power is 200W, lower electrode power is 20W, chamber pressure is 1.5Pa, Cl
2flow be 10sccm, N
2flow be 10sccm, etch period is 5min-8min, by the subregion between grid and drain electrode and P type GaN(above grid, source electrode and drain electrode or InGaN) epitaxial loayer, linear AlGaN layer all etch away, and forms the 3rd region D3 between grid leak.
4, photoetching is carried out to device, then put into electron beam evaporation platform deposit metal ohmic contact Ti/Al/Ni/Au=20/120/45/50nm and peel off, in nitrogen environment, finally carrying out the rapid thermal annealing of 850 DEG C of 35s, form ohmic contact.
5, the device preparing ohmic contact is carried out photoetching, forms P type GaN(or InGaN) etched area of epitaxial loayer, put into ICP dry etching reative cell and etch, process conditions are: upper electrode power is 200W, lower electrode power is 20W, and chamber pressure is 1.5Pa, Cl
2flow be 10sccm, N
2flow be 10sccm, etch period is 3min-5min, by subregion between grid and drain electrode, the P type GaN(of Zone Full or InGaN between grid source) epitaxial loayer etches away, and to form between grid leak the 4th region D4 between first area D1 and second area D2 and grid source.
6, the device preparing ohmic contact is put into atomic layer deposition apparatus, the Al that deposit 5-10nm is thick
2o
3medium, form insulating medium layer, process conditions are: growth temperature is 300 DEG C, and pressure is 2000Pa, H
2the flow of O and TMAl is 150sccm.
7, photoetching is carried out to the device completing deposit, form the corrosion region of insulating medium layer, then put into HF:H
230s in the solution of O=1:10, erodes the insulating medium layer beyond area of grid.
8, the device prepared is carried out photoetching, form base region, then put into electron beam evaporation platform deposit Ni/Au=20/20nm and peel off, in atmospheric environment, finally carrying out the annealing of 550 DEG C of 10min, form base ohmic contact.
9, carrying out photoetching to completing device prepared by base stage, forming grid and field plate region, grid source, then put into electron beam evaporation platform deposit Ni/Au=20/200nm and peel off, completing the preparation of grid and grid source field plate.
10, put into PECVD reative cell deposit SiN passivating film by completing device prepared by grid, the deposition thickness of passivating film is 200nm-300nm, and process conditions are: the flow of SiH4 is 40sccm, NH
3flow be 10sccm, chamber pressure is 1-2Pa, and radio-frequency power is 40W.
11, device is carried out again clean, photoetching development, form the etched area of SiN film, and put into ICP dry etching reative cell and etch, process conditions are: upper electrode power is 200W, and lower electrode power is 20W, and chamber pressure is 1.5Pa, CF
4flow be the flow of 20sccm, Ar gas be 10sccm, etch period is 10min, and SiN film source electrode, drain and gate covered above etches away.
12, device is carried out clean, photoetching development, and put into electron beam evaporation platform deposit Ti/Au=20/200nm add thick electrode, complete the preparation of integral device.
As can be seen here, method of the present invention has good controllability and repeatability.
Due to high tension apparatus of the present invention, it is formed: the 4th region D4 between first area D1, second area D2 and the 3rd region D3 and grid source between grid leak, thus makes:
(1) during break-over of device, almost identical with the increase of the AlGaN/GaN interface 2DEG concentration immediately below the 4th region D4 immediately below the D1 of first area, immediately below second area D2, all be greater than the 2DEG concentration of the 3rd region D3, therefore the resistance of first area D1, second area D2 and the 4th region D4 reduces all to some extent, reaches the object reducing device on-resistance;
(2) during device cut-off (during grid voltage≤threshold voltage), 2DEG in raceway groove immediately below grid 7 is depleted, meanwhile because the base stage 12 of first area D1 is electrically connected with grid 7, the 2DEG concentration therefore immediately below the D1 of first area reduces (being even reduced to 50%) to some extent; In addition, 2DEG concentration immediately below second area D2 is identical with during break-over of device, be conducive to the redistribution of electric field, 3rd region D3 guarantees that peak electric field there will not be at drain electrode 8 place, because this increasing the width of device depletion region, change Electric Field Distribution, reach the object improving device electric breakdown strength.
Because high tension apparatus of the present invention have employed grid source field plate, ensure that peak electric field there will not be at the boundary of grid near source, reach the object improving puncture voltage.
In addition, because the present invention adopts insulated gate structure (insulating medium layer of grid and below), avoid gate leakage current, improve device performance.
It should be noted that, above-described embodiment does not limit the present invention in any form, the technical scheme that the mode that all employings are equal to replacement or equivalent transformation obtains, and all drops in protection scope of the present invention.
Claims (10)
1. based on the AlGaN/GaNMISHEMT high tension apparatus of superjunction, it is characterized in that, comprise successively from bottom to up: substrate, GaN resilient coating, intrinsic AlGaN or GaN channel layer, AlN separator and AlGaN potential barrier, AlGaN potential barrier has in the horizontal direction successively: source electrode, grid and drain electrode, Zone Full above AlGaN potential barrier between source electrode and grid, the linear AlGaN layer of subregion extension above AlGaN potential barrier between grid and drain electrode, described grid also extends to form the Gate source field plate contacted with linear AlGaN layer upper surface to source electrode direction, also insulating medium layer is provided with between grid and AlGaN potential barrier, linear AlGaN layer between grid and drain electrode and leave gap between drain electrode and in linear AlGaN layer, extension has P type GaN or InGaN epitaxial loayer, P type GaN or InGaN epitaxial loayer there is the base stage be electrically connected with grid, linear AlGaN layer between grid and drain electrode, the width of P type GaN or InGaN epitaxial loayer reduces successively, described AlGaN potential barrier is made up of the i type AlGaN layer of lower floor and the N-shaped AlGaN layer on upper strata, the upper surface of described source electrode, grid, drain electrode and base stage is also formed and adds thick electrode, and the both sides adding thick electrode are all formed with passivation layer.
2. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, is characterized in that, described substrate is sapphire, carborundum, GaN or MgO.
3. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, it is characterized in that, in described AlGaN potential barrier, the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively x, 1-x, 1,1>x>0.
4. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 3, it is characterized in that, in described linear AlGaN layer, the component of Al is linearly increased to y by x, and the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively y, 1-y, 1,1>y>x>0.
5. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 3, it is characterized in that, in described intrinsic AlGaN channel layer, the component of Al is less than x, and the ratio of component of Al and Ga can regulate, the component of Al, Ga, N is respectively z, 1-z, 1,1>x>z>0.
6. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, is characterized in that, described insulating medium layer is SiN, Al
2o
3or HfO
2.
7. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, is characterized in that, described passivation layer is SiN, Al
2o
3or HfO
2.
8. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, is characterized in that, in described InGaN epitaxial loayer, In component is constant or increase gradually.
9. the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, is characterized in that, the linear AlGaN layer between described grid and drain electrode and gap >=0.5 μm between drain electrode.
10. make the method for the AlGaN/GaNMISHEMT high tension apparatus based on superjunction according to claim 1, it is characterized in that, comprise the following steps:
(1) organic washing is carried out to the linear AlGaN/AlGaN/GaN material of epitaxially grown p-GaN/, with flowing washed with de-ionized water and put into HCl:H
2carry out corrosion 30-60s in the solution of O=1:1, finally with flowing washed with de-ionized water and dry up with high pure nitrogen;
(2) photoetching and dry etching are carried out to the AlGaN/GaN heterojunction material cleaned up, be formed with region meas;
(3) photoetching is carried out to the AlGaN/GaN heterojunction material preparing table top, form the etched area of P type GaN epitaxial layer, linear AlGaN layer, put into ICP dry etching reative cell to etch, subregion between grid and drain electrode and the P type GaN epitaxial layer above grid, source electrode and drain electrode, linearly AlGaN layer are all etched away, forms the 3rd region between grid leak;
(4) photoetching is carried out to device, then put into electron beam evaporation platform deposit metal ohmic contact Ti/Al/Ni/Au=20/120/45/50nm and peel off, in nitrogen environment, finally carrying out the rapid thermal annealing of 850 DEG C of 35s, form ohmic contact;
(5) device preparing ohmic contact is carried out photoetching, form the etched area of P type GaN epitaxial layer, put into ICP dry etching reative cell to etch, by subregion between grid and drain electrode, the P type GaN epitaxial layer of Zone Full etches away between grid source, form first area and second area between grid leak, and the 4th region between grid source;
(6) device preparing ohmic contact is put into atomic layer deposition apparatus, the Al that deposit 5-10nm is thick
2o
3medium, forms insulating medium layer;
(7) photoetching is carried out to the device completing deposit, form the corrosion region of insulating medium layer, then put into HF:H
230s in the solution of O=1:10, erodes the insulating medium layer beyond area of grid;
(8) device prepared is carried out photoetching, form base region, then put into electron beam evaporation platform deposit Ni/Au=20/20nm and peel off, in atmospheric environment, finally carrying out the annealing of 550 DEG C of 10min, form base ohmic contact;
(9) carrying out photoetching to completing device prepared by base stage, forming grid and field plate region, grid source, then put into electron beam evaporation platform deposit Ni/Au=20/200nm and peel off, completing the preparation of grid and grid source field plate;
(10) put into PECVD reative cell deposit SiN passivating film by completing device prepared by grid, the deposition thickness of passivating film is 200nm-300nm;
(11) device is carried out again clean, photoetching development, form the etched area of SiN film, and put into ICP dry etching reative cell and etch, SiN film source electrode, drain and gate covered above etches away;
(12) device is carried out clean, photoetching development, and put into electron beam evaporation platform deposit Ti/Au=20/200nm add thick electrode, complete the preparation of integral device.
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| CN101312207A (en) * | 2007-05-21 | 2008-11-26 | 张乃千 | Enhancement type gallium nitride HEMT device structure |
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| EP1973163A2 (en) * | 2007-03-23 | 2008-09-24 | Cree, Inc. | High temperature performance capable gallium nitride transistor |
| CN101312207A (en) * | 2007-05-21 | 2008-11-26 | 张乃千 | Enhancement type gallium nitride HEMT device structure |
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