CN103888129B - High speed cml latch - Google Patents
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- CN103888129B CN103888129B CN201410088168.2A CN201410088168A CN103888129B CN 103888129 B CN103888129 B CN 103888129B CN 201410088168 A CN201410088168 A CN 201410088168A CN 103888129 B CN103888129 B CN 103888129B
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Abstract
The invention discloses a high speed CML latch. According to the CML latch, an NMOS transistor is further arranged on the basis of a traditional CML latch. The transistor is used for improving bias currents of a latch branch so as to enable the latch branch to reach higher amplifying gain and play a role in increasing the speed of a circuit. Compared with the traditional CML latch, the high speed CML latch is increased little in power consumption, reaches 15.2Hz in working frequency, and realizes the purpose of increasing working speed under the premise of controlling power consumption.
Description
Technical field
The present invention relates to Latch Technology field, it is more particularly to a kind of high speed cml latch.
Background technology
With the continuous development of semiconductor technology, circuit work frequency is constantly lifted.Especially in high speed data transfer situation
Under, when speed reaches more than 5ghz, based on cmos(complementary metal oxide semiconductor) logic
Element circuit will face the restriction in operating rate.High speed data transfer is generally patrolled with cml circuitry instead tradition cmos
Volume.
As the basic module of sequential type digital circuit, latch is applied widely in integrated circuits.Based on cml's
The usual structure of latch follows branch road 100 and a latch branch road 102, respectively by positive and negative two-phase as shown in figure 1, it includes one
Clock vclk+ and vclk- control.Tail current source 116 is responsible for circuit and provides bias current, and this electric current is in load resistance 118
With 120 on produce pressure drop, thus producing output signal vout+ and vout-.Specifically, when vclk+ for high when, transistor 112
Conducting, follows branch road 100 and opens, and vclk- is low simultaneously, and transistor 114 turns off, and latches branch road 102 and turns off, bias current only flows
Cross and follow branch road 100.Input is controlled by differential input signal vin+ and vin- respectively to pipe 104 and 106, if vin+ is height,
Electric current flows through transistor 104 and load resistance 118, thus vout- is pulled down to a relatively low level；And transistor 106 He
The branch road that load resistance 120 is located then does not have electric current to flow through, so that output node vout+ remains high level.In the same manner, if
Vin- is height, then bias current flows through transistor 106 and load resistance 120, and transistor 104 and load resistance 118 then do not have
Electric current flows through so that output node vout- and vout+ shows as high level and relatively low level respectively.Thus, vclk+
For high when achieve the function that level is followed, and when vclk- for high when, transistor 114 turns on, latch branch road 102 open；Simultaneously
Vclk+ is low, and transistor 112 turns off, and follows branch road 100 and turns off.Output node vout+ and vout- is in cross-coupled pair pipe 108
In the presence of 110, keep and amplify the level of a upper following state, realize latch function.Because this circuit is by tail current
Source 116 provides constant bias current, and amplifier tube always works at saturation region, without constantly online as cmos circuit
Property between area and saturation region change, therefore circuit speed be better than cmos circuit.But, when frequency is extra high (>
10ghz), this circuit is affected by latching branch gain, and gain is little to be likely to occur disabler.Latch the gain master of branch road
To be affected by branch road tail current source size, gain amplifier can be improved by increasing branch road tail current source size, thus right
Follow under high frequency that the non-ideal signal that branch road captures is amplified and level recovers.For the traditional cml latch in Fig. 1,
Due to following branch road and latching the shared tail current source of branch road, lead to latch limited by branch gain under high frequency, thus have impact on circuit
Speed.And directly increase tail current source size and can lead to being obviously improved of power consumption, therefore this traditional cml latch is subject to speed
Mutual restriction with power consumption.
Content of the invention
(1) technical problem to be solved
The technical problem to be solved in the present invention is how on the premise of not dramatically increasing circuit power consumption, improves cml and latches
The operating frequency of device.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of high speed cml latch, described cml latch includes
Follow branch road 200, latch branch road 202, power pin v, ground pin g, the first load resistance 218, the second load resistance 220,
Reversely output node vout-, positive output node vout+, reverse clock vclk-, positive clock vclk+, positive input signal
Vin+, reverse input signal vin-, tail current source 216, the 7th nmos transistor 222；Wherein said branch road 200 of following includes
One nmos transistor 204, the 2nd nmos transistor 206, the 3rd nmos transistor 212；Described latch branch road 202 includes the 4th
Nmos transistor 214, the 5th nmos transistor 208, the 6th nmos transistor 210；
Described first load resistance 218 one end connects described power pin v, and the other end connects reverse output node vout-；
Described second load resistance 220 one end connects described power pin v, and the other end connects positive output node vout+；Described first
Nmos transistor 204, its grid connects positive input signal vin+, and drain electrode is connected to described reverse output node vout-；Described
2nd nmos transistor 206, its grid connects reverse input signal vin-, and drain electrode is connected to described forward direction output node vout+,
Source electrode is connected with the source electrode of a described nmos transistor 204；3rd nmos transistor 212, its grid connects positive clock
Vclk+, drain electrode is connected to the source electrode of a described nmos transistor 204 and the source electrode of described 2nd nmos transistor 206；
4th nmos transistor 214, its grid connects reverse clock vclk-, and source electrode connects described 3rd nmos transistor
212 source electrode；5th nmos transistor 208, its grid connects described forward direction output node vout+, and drain electrode connects described reverse
Output node vout-, source electrode connects the drain electrode of described 4th nmos transistor 214；6th nmos transistor 210, its grid is even
Meet described reverse output node vout-, drain electrode connects described forward direction output node vout+, and it is brilliant that source electrode connects described 4th nmos
The drain electrode of body pipe 214；
Described 7th nmos transistor 222, its grid connects described reverse clock vclk-, and drain electrode connects the described 3rd
The source electrode of nmos transistor 212, source electrode connects described ground pin g；
Described tail current source 216, its positive pole connects source electrode and the 4th nmos crystal of described 3rd nmos transistor 212
The source electrode of pipe 214, negative pole is connected to described ground pin g.
Preferably, when described reverse clock vclk- is high level, described forward direction clock vclk+ is low level, follows branch road
200 disconnections, latch branch road 202 and turn on, described 7th nmos transistor 222 turns on, and the current value flowing through latch branch road 202 is more than
The current value of tail current source 216；When described forward direction clock vclk+ is high level, described reverse clock vclk- is low level, with
With branch road (200) conducting, latch branch road (202) and disconnect, described 7th nmos transistor (222) is not turned on, and follows branch road (200)
Current value be equal to tail current source (216) current value.
Preferably, the maximum operating frequency of described high speed cml latch is 15.2ghz.
(3) beneficial effect
The invention provides a kind of high speed cml latch, it adopts one to be increased by the nmos transistor of clock control
Latching the tail current source size of branch road, thus improve the gain amplifier latching branch road, and then improve the work frequency of latch
Rate；Compared to traditional cml latch, the high speed cml latch that the present invention adopts increase only 1.3% power consumption, can be operated in height
Reach under the frequency of 15.2ghz.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the structural representation of traditional cml latch；
Fig. 2 is the structural representation of the high speed cml latch of a preferred embodiment of the present invention；
Fig. 3 a, Fig. 3 b are simulation result under 1.25ghz frequency for the two kinds of cml latch shown in Fig. 1, Fig. 2 respectively；
Fig. 4 a is by the structural representation of cml latch structure d trigger；
Fig. 4 b is the structural representation being constructed 4 frequency dividing circuits by d trigger；
Fig. 5 a, Fig. 5 b are 4 frequency dividing circuits being built based on two kinds of cml latch shown in Fig. 1, Fig. 2 in 8ghz frequency respectively
Under simulation result；
Fig. 6 a, Fig. 6 b be 4 frequency dividing circuits that built based on two kinds of cml latch shown in Fig. 1, Fig. 2 respectively respective
Simulation result under senior engineer's working frequency.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is described in further detail.Following examples are used for this is described
Bright, but can not be used for limiting the scope of the present invention.
Fig. 2 is the structural representation of the high speed cml latch of a preferred embodiment of the present invention, as shown in the figure: first
Load resistance 218, its one end is connected to described power pin v, and the other end is connected to reverse output node vout-；Second load
Resistance 220, its one end is connected to described power pin v, and the other end is connected to positive output node vout+；First nmos crystal
Pipe 204, its grid connects positive input signal vin+, and drain electrode is connected to described reverse output node vout-；2nd nmos crystal
Pipe 206, its grid connects reverse input signal vin-, and drain electrode is connected to described forward direction output node vout+, source electrode and described the
The source electrode of one nmos transistor 204 is connected；3rd nmos transistor 212, its grid connects positive clock vclk+, and drain electrode connects
Source electrode in described first and second nmos transistor 204 and 206.
4th nmos transistor 214, its grid connects reverse clock vclk-, source electrode and described 3rd nmos transistor 212
Source electrode be connected；5th nmos transistor 208, its grid is connected to described forward direction output node vout+, and drain electrode is connected to described
Reversely output node vout-, source electrode is connected to the drain electrode of described 4th nmos transistor 214；6th nmos transistor 210, its
Grid is connected to described reverse output node vout-, and drain electrode is connected to described forward direction output node vout+, and source electrode is connected to institute
State the drain electrode of the 4th nmos transistor 214, i.e. the source electrode of described 5th nmos transistor 208；7th nmos transistor 222, its
Grid is connected to described reverse clock vclk-, and drain electrode is connected to described 3rd nmos transistor 212 and the 4th nmos transistor
214 source electrode, source electrode is connected to described ground pin g.
Current source 216, its positive pole is connected to the source electrode of described 3rd nmos transistor 212 and the 4th nmos transistor 214,
Negative pole is connected to described ground pin g.
Latch is constituted by a nmos transistor 204, the 2nd nmos transistor 206 and the 3rd nmos transistor 212
Follow branch road 200, constituted by the 4th nmos transistor 214, the 5th nmos transistor 208 and the 6th nmos transistor 210
The latch branch road 202 of latch.
Described power pin v, for providing supply voltage for described cml latch；Described ground pin g, for for institute
Stating cml latch provides earth level；
The operation principle of the high speed cml latch of the present invention is: when vclk+ for high when, the 3rd nmos transistor 212 is led
Lead to and open so that following branch road 200, the electric current on tail current source 216 flows through follows branch road 200, and circuit is operated in following state.
Meanwhile, vclk- is low, and the 4th nmos transistor 214 and the 7th nmos transistor 222 turn off, and latches branch road and turns off, will not to
Produce impact with branch road.And when vclk- for high when, the 4th nmos transistor 214 turns on and opens so that latching branch road 202, intersect
Coupling is amplified to pipe 208 and the 210 pairs of signals and recovers, and circuit is operated in latch mode.Meanwhile, the 7th nmos transistor
222 also can open, and lead to flow through the size of current latching the electric current of branch road 202 more than tail current source 216, serve to separate and latch
Branch road and the effect following branch road.Electric current due to following branch road increases so that its gain becomes big, thus having preferably to signal
Amplify and recovery capability, higher operating frequency can be applied to.Meanwhile, the 7th nmos transistor 222 is protected under following state
Holding shutoff, thus not increasing the circuit power consumption under following state, can effectively save compared to the direct tail current source size that increases
Save circuit power consumption.
Using circuit simulation tools cadence respectively to the height according to the present invention in the existing latch and Fig. 2 in Fig. 1
Fast cml latch is emulated, and its simulation result is compared.This emulation is based on chrt130nm technique, supply voltage
For 1.2v.
First Transient is carried out at a lower frequency to two latch, to verify the operation principle of two latch.
Fig. 3 a and Fig. 3 b respectively illustrates in Fig. 1 and Fig. 2 oscillogram under 1.25ghz frequency for two kinds of cml latch.Wherein, Fig. 3 a
And three waveforms from top to bottom are all followed successively by Fig. 3 b: positive input signal vin+, positive clock signal vclk+ and complementation
Output signal vout；Due to cml latch circuit intrinsic support Complementary input structure, output, so with vout represent vout+ and
vout-.As seen from the figure, in fig. 3 a, when vclk+ is for high level, output signal vout+ follows the change of input signal vin+
Change, latch is operated in following state；And when vclk+ is for low level, output signal keeps constant, circuit is operated in latch shape
State.In fig 3b, output voltage assumes identical Changing Pattern, also corresponds to the operation principle of latch.Difference is,
Vclk+ is that output voltage swing during low level is more than the output voltage swing that vclk+ is during high level, and this is due to vclk+
During for low level, when that is, vclk- is high level, the 7th nmos transistor 222 turns on, so that flowing through the electric current latching branch road
More than the electric current of tail current source 216, and when vclk+ is for high level, the 7th nmos transistor 222 is not turned on, so that stream
Cross the electric current following the electric current of branch road equal to tail current source 216.Therefore, vclk+ is output voltage swing just meeting during low level
It is output voltage swing during high level more than vclk+.By the effect of the 7th nmos transistor, increase the biasing latching branch road
Electric current, thus improving its gain amplifier, and then improves the operating frequency of latch.
The power consumption of traditional cml latch and the high speed cml latch of the present invention is emulated.Frequency in 1.25ghz
Under rate, in Fig. 1 and Fig. 2, the power consumption of two kinds of latch is respectively 0.180mw and 0.182mw, the high speed cml latch phase of the present invention
In traditional cml latch, power consumption increased the value of very little to ratio.
The high speed cml latch of the checking present invention is compared to the speed advantage of traditional cml latch below.Divider circuit
Also have a very wide range of applications in integrated circuit fields, be therefore based respectively on two kinds of latch and built 4 frequency dividing circuits, and right
It has carried out simulation analysis.
Fig. 4 a is to build d trigger by cml latch, and Fig. 4 b is to build 4 frequency dividing circuits by described d trigger.Due to cml
Latch circuit is intrinsic to support Complementary input structure, output, so vout represents two nodes of vout+ and vout-；Vin represents vin+
And two nodes of vin-；Vclk represents two nodes of vclk+ and vclk-.
As shown in fig. 4 a, it is sequentially connected by two cml latch 302 and 304, you can constitute a d trigger 300.D touches
Send out device 300 and include four key nodes: input d, clock end clk, positive output end q and inverse output terminal qn.Wherein
The clock polarity of one cml latch 302 and clk input clock opposite polarity, the clock polarity of the 2nd cml latch 304 and clk
Input clock polarity is identical.Inverse output terminal qn is the complementary node of positive output end q it may be assumed that qn+=q-, qn-=q+；First cml
Output end vout of latch 302 connects the input signal end vin of the 2nd cml latch 304.
As shown in Figure 4 b, may make up 4 frequency dividing circuits by two d triggers 400 and 402.Two d triggers reverse
Output end qn is all connected with the input d of its own, to constitute frequency-halving circuit.The input end of clock of this 4 divider circuit
Vclkin is the clock end clk of a d trigger 400, and output terminal of clock vclkout is the forward direction of the 2nd d trigger 402
Output end q.Positive output end q of the first d trigger 400 is connected with the clock end clk of the 2nd d trigger 402, that is, two points
Intermediate node vmid after frequency.
First under the frequency of 8ghz, realize 4 points of high speed cml latch to the present invention and traditional cml latch
Frequency circuit is emulated, and respectively as shown in figure 5 a and 5b, each in figure waveform from top to bottom is respectively as follows: 8ghz's to oscillogram
Output signal vclkout after M signal vmid after input clock signal vclkin, two divided-frequency and four frequency dividing.It can be seen that,
Under the frequency of 8ghz, two circuit all enable the effect of four frequency dividings.Its circuit power consumption is respectively 0.841mw and 0.873mw.
Secondly, it is respectively directed to above-mentioned two divide by four circuit, emulate the highest frequency that it can reach.Emulation obtains, right
In the divide by four circuit realized based on traditional cml latch, its maximum operating frequency is 8.5ghz, for the height based on the present invention
The divide by four circuit that fast cml latch is realized, its maximum operating frequency is up to 15.2ghz.It can be seen that, the high speed cml lock of the present invention
Storage can effectively improve circuit work frequency.Fig. 6 a and Fig. 6 b respectively illustrates two kinds of divide by four circuits in its respective highest
Output waveform under operating frequency, three groups of waveforms from top to bottom are respectively as follows: the input clock signal under respective highest frequency
Output signal vclkout after M signal vmid after vclkin, respective two divided-frequency and four frequency dividing.
In sum, the high speed cml latch circuit of the present invention, the tail current that can separately follow branch road and latch branch road
Source, making latch branch road flow through more bias currents when working, thus lifting its circuit gain, effectively improving the work of latch
Frequency.Simultaneously compared to traditional cml latch, its power consumption merely add little percentage it is achieved that control power consumption before
Put the purpose improving operating rate.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although with reference to embodiment to this
Bright be described in detail, it will be understood by those within the art that, technical scheme is carried out various combinations,
Modification or equivalent, without departure from the spirit and scope of technical solution of the present invention, the right that all should cover in the present invention will
Ask in the middle of scope.
Claims (3)
1. a kind of high speed cml latch is it is characterised in that described cml latch includes following branch road (200), latches branch road
(202), power pin v, ground pin g, the first load resistance (218), the second load resistance (220), reverse output node
Vout-, positive output node vout+, reverse clock vclk-, positive clock vclk+, positive input signal vin+, reversely input
Signal vin-, tail current source (216), the 7th nmos transistor (222)；Wherein said branch road (200) of following includes a nmos
Transistor (204), the 2nd nmos transistor (206), the 3rd nmos transistor (212)；Described latch branch road (202) includes the 4th
Nmos transistor (214), the 5th nmos transistor (208), the 6th nmos transistor (210)；
Described first load resistance (218) one end connects described power pin v, and the other end connects reverse output node vout-；Institute
State the second load resistance (220) one end and connect described power pin v, the other end connects positive output node vout+；Described first
Nmos transistor (204), its grid connects positive input signal vin+, and drain electrode connects described reverse output node vout-；Described
2nd nmos transistor (206), its grid connects reverse input signal vin-, and drain electrode connects described forward direction output node vout+,
Source electrode is connected with the source electrode of a described nmos transistor (204)；3rd nmos transistor (212), when its grid connects positive
Clock vclk+, drain electrode connects the source electrode of a described nmos transistor (204) and the source of described 2nd nmos transistor (206)
Pole；
4th nmos transistor (214), its grid connects reverse clock vclk-, and source electrode connects described 3rd nmos transistor
(212) source electrode；5th nmos transistor (208), its grid connects described forward direction output node vout+, and drain electrode connects described
Reversely output node vout-, source electrode connects the drain electrode of described 4th nmos transistor (214)；6th nmos transistor (210),
Its grid connects described reverse output node vout-, and drain electrode connects described forward direction output node vout+, and source electrode connects described the
The drain electrode of four nmos transistors (214)；
Described 7th nmos transistor (222), its grid connects described reverse clock vclk-, and drain electrode connects described 3rd nmos
The source electrode of transistor (212), source electrode connects described ground pin g；
Described tail current source (216), its positive pole connects source electrode and the 4th nmos crystal of described 3rd nmos transistor (212)
The source electrode of pipe (214), negative pole connects described ground pin g.
2. high speed cml latch according to claim 1 is it is characterised in that described reverse clock vclk- is high level
When, described forward direction clock vclk+ is low level, and the 3rd nmos transistor (212) followed in branch road (200) disconnects, and latches and props up
The 4th nmos transistor (214) conducting in road (202), described 7th nmos transistor (222) conducting, latch branch road (202)
Current value be more than tail current source (216) current value；When described forward direction clock vclk+ is high level, described reverse clock
Vclk- is low level, follows the 3rd nmos transistor (212) conducting in branch road (200), latches the 4th in branch road (202)
Nmos transistor (214) disconnects, and described 7th nmos transistor (222) is not turned on, and the current value following branch road (200) is equal to tail
The current value of current source (216).
3. high speed cml latch according to claim 1 is it is characterised in that the highest of described high speed cml latch works
Frequency is 15.2ghz.
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|---|---|---|---|
| CN201410088168.2A CN103888129B (en) | 2014-03-11 | 2014-03-11 | High speed cml latch |
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|---|---|---|---|
| CN201410088168.2A CN103888129B (en) | 2014-03-11 | 2014-03-11 | High speed cml latch |
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| CN103888129B true CN103888129B (en) | 2017-01-18 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640531A (en) * | 2009-08-21 | 2010-02-03 | 天津大学 | Current mode logic latch |
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- 2014-03-11 CN CN201410088168.2A patent/CN103888129B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640531A (en) * | 2009-08-21 | 2010-02-03 | 天津大学 | Current mode logic latch |
Non-Patent Citations (1)
| Title |
|---|
| Prospects of CMOS technology for high-speed optical communication circuits;B. Razavi;《Gallium Arsenide Integrated Circuit (GaAs IC) Symposium,23rd Annual Technical Digest，2001》;20011231;第Ⅳ节、图9 * |
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