CN103887265A - 具有印刷电路层的集成电路封装及其制作方法 - Google Patents

具有印刷电路层的集成电路封装及其制作方法 Download PDF

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CN103887265A
CN103887265A CN201310712598.2A CN201310712598A CN103887265A CN 103887265 A CN103887265 A CN 103887265A CN 201310712598 A CN201310712598 A CN 201310712598A CN 103887265 A CN103887265 A CN 103887265A
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layer
nude film
circuit
signal route
encapsulation
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马修·戴维·罗米格
兰斯·科尔·赖特
莱斯利·爱德华·斯塔克
弗兰克·斯特普尼克
斯里尼瓦萨恩·K·科杜里
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Texas Instruments Inc
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Abstract

本申请案涉及具有印刷电路层的集成电路封装及其制作方法。一种集成电路IC封装包括IC裸片及电连接到所述IC裸片的导电油墨印刷电路层。

Description

具有印刷电路层的集成电路封装及其制作方法
技术领域
本发明涉及具有印刷电路层的集成电路封装。
背景技术
许多集成电路(“IC”)封装包括单个IC裸片，所述单个IC裸片安装于所述IC裸片所电连接到的引线框架或其它导电衬底上。裸片为含有执行预定功能的电路的小半导体块。引线框架或其它电衬底使得裸片中的电路能够连接到通常提供于在IC封装所电附接到的印刷电路板或其它电组合件上的外部电路。IC封装通常还包括保护裸片及电衬底的硬的非导电囊封材料层。
IC裸片含有作用于输入到裸片的信号的有源电路元件，例如晶体管。有时期望在信号被输入到裸片之前或在所述信号离开裸片之后使所述信号通过无源电路元件，例如电阻器及电容器。这样做的一种方式是在IC封装内提供一个或一个以上无源电路元件。无源电路元件可为(举例来说)附接到裸片的经蚀刻或经镀敷金属电路层或离散电路装置。
发明内容
本发明提供一种集成电路(IC)封装，其包含：IC裸片；及导电油墨印刷无源电路层，其电连接到所述IC裸片。
本发明进一步提供一种制作IC封装的方法，其包含：将电路印刷到所述IC封装的非导电层上，所述电路具有至少一个无源元件；及将IC裸片电连接到所述电路。
本发明还提供一种IC封装，其包含：IC裸片，其具有上面带有多个接触垫的上部表面，及底部表面；经图案化金属信号路由层，其定位于所述裸片的所述底部表面下面且具有顶部表面及底部表面，所述信号路由层的所述顶部表面线接合附接到所述裸片上的所述接触垫中的至少一者；聚酰亚胺带衬底，其定位于所述IC裸片及所述信号路由层下面，且具有顶部表面及底部表面且具有在其所述顶部与底部表面之间延伸的多个导通体；至少一个阻焊剂层，其提供于所述聚酰亚胺带衬底及所述信号路由层中的一者上；导电油墨印刷无源电路层，其印刷于所述聚酰亚胺带衬底及所述阻焊剂层中的一者上且电连接到所述信号路由层；囊封层，其囊封所述IC裸片、所述经蚀刻金属信号路由层、所述导电油墨印刷层及所述聚酰亚胺带衬底的至少一部分；及球栅阵列，其定位于所述聚酰亚胺带衬底下面且经由所述导通体而电附接到所述经蚀刻金属信号路由层。
附图说明
图1是常规IC封装的切除透视图。
图2是图1的IC封装的一部分的横截面图。
图3是制作常规IC封装(诸如展示于图1及2中)的工艺中的裸片附接步骤的示意性表示。
图4是制作常规IC封装的工艺中的线接合步骤的示意性表示。
图5是制作常规IC封装的工艺中的模制步骤的示意性表示。
图6是制作常规IC封装的工艺中的球附接步骤的示意性表示。
图7是制作常规IC封装的工艺中的单个化步骤的示意性表示。
图8是具有导电油墨无源电路层的IC封装的示意性横截面表示，所述导电油墨无源电路层印刷于阻焊剂层上且连接到经图案化金属层的外围部分。
图9是具有导电油墨无源电路层的IC封装的示意性横截面表示，所述导电油墨无源电路层印刷于封装衬底层上且通过延伸穿过导通孔的立柱连接到经图案化金属层。
图10是具有导电油墨无源电路层的IC封装的示意性横截面表示，所述导电油墨无源电路层印刷于封装衬底层上且通过延伸穿过导通孔的立柱连接到经图案化金属层，其中焊料球也经由所述导通孔连接到所述经图案化金属层。
图11是具有印刷于封装衬底层上的导电油墨无源电路层的IC封装的示意性横截面表示。
图12是IC封装的经图案化金属层的俯视平面图。
图13是印刷于非导电材料层上且连接到经图案化金属层的无源电路元件的细节平面图。
图14是印刷于非导电材料层上的另一无源电路元件的示意性平面图。
图15是提供于衬底上的无源电路元件的平面图。
图16是图15的无源电路元件的侧立面图。
具体实施方式
本发明一般来说描述集成电路(IC)封装11，其包括：IC裸片12；信号路由电路层22，其电连接到IC裸片12；及导电油墨印刷无源电路层122，其电连接到信号路由电路层22。还描述制作IC封装11的方法，其包括：用导电油墨将无源电路层122印刷到IC封装11的非导电层(例如，32、42)上；及经由信号路由电路层22将IC裸片12电连接到无源电路层122。已如此大体描述了IC封装及制作IC封装的方法，现在将详细描述其各种实施例。
图1是常规集成电路(IC)封装10的部分切除视图，且图2是图1的IC封装的一部分的横截面立面图。如由图2最佳图解说明，IC封装10包括具有顶部表面14及底部表面16的IC裸片12。多个接触垫18(图2中仅展示一个)提供于顶部表面14上。经蚀刻金属信号路由电路层22(在下文中称作“信号路由电路层22”)定位于IC裸片12下面且横向向外延伸超出IC裸片12。信号路由电路层22具有顶部表面24及底部表面26。绝缘层32(其可为阻焊剂层且其在本文中有时称作“阻焊剂层32”)直接定位于信号路由电路层22上面。绝缘层32具有顶部表面34及底部表面36。信号路由电路层22的顶部表面24与绝缘层32的底部表面36介接。具有顶部表面44及底部表面46的封装衬底层42定位于信号路由电路层22下面，其中衬底42的顶部表面44与信号路由电路层22的底部表面26介接。导通孔48在信号路由电路层22下面的区域中延伸穿过衬底42。焊料球60直接定位于导通孔48下面且具有延伸穿过导通孔48的焊料球立柱部分62。立柱部分62与信号路由电路层22电接触。IC裸片12通过多个线接合70电连接到信号路由电路层22。每一线接合70包括在一端处通过第一焊接74连接到IC裸片12上的接触垫18的薄引线72。线72在第二端处通过第二焊接76连接到信号路由电路层22的顶部表面部分。裸片12具有线接合连接到电路层22上的多个点的多个接触垫18(图1中仅展示两个)，如图1及4中所展示。
如图2中最佳展示，环氧树脂层50将IC裸片12附接到阻焊剂层32及封装衬底42的部分。
经凝固模制化合物82(在本文中有时称作囊封剂82)以密封方式覆盖IC裸片12、环氧树脂层50、阻焊剂层32、信号路由电路层22及线接合70。
用于制作IC封装10(例如图1及2中所图解说明)的主要工艺步骤示意性地展示于图3-7中。图3图解说明裸片附接工艺。衬底材料(例如聚酰亚胺带)的条带40具有通常通过此项技术中众所周知的多步骤光致抗蚀剂及蚀刻工艺图案化于其上的多个间隔开的电路层22。将阻焊剂层32(图3中未展示)施加于电路层22的一部分上方。接下来，通过自动化的注射在具有比将被施加到其的IC裸片12的占用面积稍微大的周边的区域中施加环氧树脂层50。环氧树脂50覆盖阻焊剂层32的大部分或全部。接下来，通常通过使用贴片机将IC裸片12施加到每一信号路由电路层22的环氧树脂50覆盖的区域。接着将衬底条带40移动到固化炉，环氧树脂50在所述固化炉处固化且因此牢固地将裸片12固持在适当位置。
如图4所展示的工艺中的下一步骤是线接合。在此工艺中，衬底条带40上的每一裸片12在其顶部表面上具有通过线接合70电附接到信号路由电路层22的预定部分的接触垫18。裸片到电路层的线接合附接在此项技术中是众所周知的。
如图5所图解说明，接下来将衬底条带40移动到模具台(例如，转移模具)，在所述模具台处施加模制化合物82(在本文中有时称作“囊封剂”)层，其覆盖裸片12、线接合70、电路层22及阻焊剂层32以及衬底条带40的环氧树脂50及顶部表面44。
接下来，如图6所图解说明，衬底条带40经历球附接工艺。在此工艺中，将衬底条带40翻转，从而暴露在裸片附接之前在条带40的底部表面中打的多个导通孔48。将焊料球60定位于导通孔48中的每一者上方且经由延伸穿过导通孔48的立柱部分62附接到信号路由电路层22(图1)。此种球栅附接在此项技术中广泛地实践。接下来，如图7中所图解说明，沿着大体对应于图6中的线41及43的锯割道将衬底条带40单个化。所述单个化产生个别IC封装10。
IC封装10的结构(如图1及2中所展示)及其制作方法(如图3到7中示意性地图解说明)在此项技术中是已知的。如较早所提及，借以产生信号路由电路层22的工艺是耗时的工艺，其涉及多个高精确度步骤(涉及光致抗蚀剂图案的施加、化学蚀刻等)或各种金属镀敷工艺步骤，其全部在此项技术中是已知的。类似地，借以在裸片12内形成电路的工艺为极高精确度的操作，其包括多个形成步骤。连接到此些电路层22的裸片12具有执行特定功能的经嵌入电路。有时期望除裸片12中所含有的电路外将其它电路添加到IC封装。存在添加电路组件的各种方式。一种方式是在裸片形成期间将此些组件添加到裸片电路。另一方式是提供类似于电路层22的通过蚀刻或镀敷形成但包括电连接到裸片电路的无源电路元件的另一电路层。这两种选项均非常昂贵。将新电路层提供到裸片12或在裸片的外部提供到封装10的一个优点在于，新电路层装配于IC封装10的现有占用面积内。所添加电路层多半不显著增加封装10的高度。以此方式添加电路的缺点在于，另一电路层的蚀刻等或金属镀敷(在裸片12的内部或外部)显著增加IC封装10的费用。
申请者已开发将额外电路层提供到IC封装的方法，其具有与添加经蚀刻或经镀敷金属电路层相同的优点，但成本低得多。所述方法涉及无源电路元件到非导电材料(例如，阻焊剂)层上的油墨印刷。所述方法使用可通过丝网印刷或通过喷墨印刷来印刷的导电油墨。可在IC封装内的不同位置处提供额外电路层，如下文将参照图9到12描述。可通过选择适当油墨图案来提供各种无源电路元件(例如，电容器、电阻器及电感器)，如下文参照图13到15所描述。
下文所描述的导电油墨印刷无源电路122可全部通过喷墨印刷或丝网印刷形成。使用喷墨印刷器在二维表面上印刷导电油墨在此项技术中是已知的，如在以下美国专利申请公开案中所描述：在2010年3月11日公开的谢尔盖·列米佐夫(Sergey Remizov)等人的“印刷电路板及制造方法(Printed Circuit Board and Manufacturing Method)”的第U.S.2010/0059251号美国专利申请公开案；在2010年6月17日公开的白润雅(Yoon-Ah Baik)等人的“表面处理方法、电路线形成方法、电路线形成设备及由此形成的印刷电路板(Surface Treatment Method，Circuit Lines Formation Method，Circuit Lines FormationApparatus and Printed Circuit Board Formed Thereby)”的U.S.2010/0149249；在2011年2月24日公开的李钟熙(Jong-Hee Lee)的“导电油墨、使用导电油墨制备金属布线的方法及使用方法制备的印刷电路板(Conductive Ink，Method of Preparing Medal WiringUsing Conductive Ink，and Printed Circuit Board Prepared Using Method)”的U.S.2011/0042125，其中的每一者针对其中所揭示的全部内容以引用方式并入本文中。电衬底上的导电油墨迹线的喷墨印刷也揭示于在2012年8月22日提出申请的马修·大卫·罗米格(Mathew David Romig)等人的“具有三维喷墨印刷迹线的电子组合件(ELECTRONICASSEMBLY WITH THREE DIMENSIONAL INKJET PRINTED TRACES)”的第13/591719号美国专利申请案中，所述申请案针对其所揭示的全部内容以引用方式并入本文中。
可用于喷墨印刷导电迹线的各种油墨配方在此项技术中是已知的，例如以引用方式并入的以上专利公开案中所揭示的那些。适合印刷导电迹线的另一此类油墨配方揭示于在2010年7月15日公开的美国专利申请案U.S.2010/0178420中，其针对其中所揭示的全部内容以引用方式并入本文中。可在市场上从各种制造商，例如杜邦(DuPont)、微电路材料(Microcircuit Materials)、14T.W.Alexander Dr.、三角研究园(Research TrianglePark)、MC27709购得其它合适喷墨油墨配方。一种此类杜邦喷墨油墨以产品名称5000银导体进行销售。
现在返回到图式，图8是其中提供有导电油墨印刷无源电路122的IC封装11的横截面示意图。在图8的实施例中，以相同参考编号标记IC封装11的与图2的IC封装10中所展示的那些组件相同的组件。在此实施例中，除导电油墨无源电路层122印刷于封装的非导电层(例如，32)的顶部上以外，图8-11中所展示的封装11的配置可与图2中所展示的封装10大体相同。印刷电路层122具有顶部表面124及底部表面126。顶部表面124与环氧树脂层50及模制化合物82层介接。端部分123横向向外延伸超出阻焊剂层32且向下延伸以与信号路由电路层22接触。关于用于施加此印刷电路层122的方法，在一个实施例中，在施加环氧树脂50之前将其印刷到阻焊剂层32上。在一些实施例中，通过将相关联衬底条带(其可类似于图3-7中的条带40)移动到热源(例如，干燥炉(未展示))而在单独加热步骤中使印刷电路层122固化，在所述热源处其在经选择用于所使用的特定导电油墨的固化的预定温度下被加热预定时段。在另一实施例中，将环氧树脂50施加于印刷电路层122上方。接着与环氧树脂50同时通过常规环氧树脂固化操作使印刷电路层122固化。IC封装11形成步骤的剩余部分可与上文针对IC封装10参照图3-7所描述大体相同。
施加导电油墨印刷无源电路层122的方法的另一实施例图解说明于图9中。如图9中所展示，将无源电路层122印刷于衬底层42的底部表面上，其中印刷电路层122的顶部表面124与衬底42的底部表面46介接。在一个实施例中，印刷电路层122具有沿着导通孔48的表面部分向上延伸的端立柱部分128。在导通孔48的顶部处，立柱部分128与信号路由电路层22的下部表面26的预定部分接触。在此实施例中，不存在与导通孔48相关联的焊料球60。在另一实施例中，如图10所展示，提供具有延伸到导通孔48中的立柱128的相同印刷电路层122。然而，在此实施例中，焊料球60具有也延伸穿过导通孔48的立柱部分62。此实施例本质上将额外层添加到封装的外部用于路由无源器件。
图11图解说明其中印刷电路层122邻近导通孔48印刷于衬底42的底部表面46上的实施例。在此实施例中，印刷电路层122充当第一电容板且板132充当第二电容器板。板132可为上面带有经镀敷或经蚀刻金属层的单独衬底或其可为印刷于衬底42的上部表面44上的导电油墨层。衬底42充当此电容器的介电层。电路层122及板132两者可通过常规连接构件(未展示)连接到信号路由电路层22或直接连接到裸片50。
现在将描述由印刷电路层122提供的某些无源电路元件的形成。图12图解说明具有多个信号迹线的典型经蚀刻信号路由电路层22。所述迹线可具有端接于此层的外边界处的端部分(例如，21、23)且可具有适于连接到提供于电路封装11(图8)的底部上的球栅阵列的球60的内部部分(例如，25、27)。在图8的实施例中，将非导电层(例如，阻焊剂层32)施加于信号路由电路层22的顶部表面上。接下来，通过导电油墨的喷墨印刷或丝网印刷将预定图案(例如，梳电容器图案140(图13))印刷到阻焊剂层32上。(在图13中以虚线展示信号路由电路层22，因为其被阻焊剂层32覆盖。)梳电容器140具有具有E形配置的第一部分142及具有大体U形配置的第二部分144。第一部分142具有与信号路由电路层22的迹线23接触的终止端143。第二部分144具有与信号路由电路层22的迹线21接触的终止端145。从图13将看到，印刷电路层122的终止端143及145可延伸超出阻焊剂层32的边缘。
图14示意性地图解说明具有提供电阻器150的盘旋图案的印刷层122。电阻器150具有连接到信号路由电路层22的终止端152及154。
图15是具有仿效电感器线圈的印刷图案160的衬底(例如，42)的俯视平面图。图16是其侧立面图。图案160具有连接到信号路由电路层22的终端162及164。图案160在图9的封装实施例中提供于非导电层(例如，衬底42)的顶部上。图案160包括通过金属蚀刻或金属镀敷或者通过导电油墨迹线的印刷形成于衬底42的表面上的线性电迹线170、172、174、176、178、180。所述图案进一步包括绝缘材料条带182、184、186、188、190，其可为通过常规方法或通过介电油墨的喷墨印刷或丝网印刷提供的阻焊剂或其它介电材料。绝缘材料条带182、184等在电迹线170、172等之间定位于衬底42上且可具有与电迹线实质上相同的高度。所述图案进一步包括在电迹线170、172、174等的端部分之间延伸且电连接所述端部分的印刷导电油墨迹线192、194、196、198、200。印刷迹线192、194等提供于绝缘条带182、184等的顶部上。将理解，如果图9的衬底42具备此图案160，那么图15及16的视图应反转。
所属领域的技术人员在阅读本发明之后将了解，已描述在IC封装中提供无源电路元件的新方法。此方法提供在已形成IC裸片之后“定制”集成电路封装的相对低成本方式。因此，可在裸片的有源电路已产生之后且以相对低成本将各种无源电路元件添加到裸片的有源电路。换句话说，相同裸片配置可与不同无源电路一起使用以在IC封装内提供全部具有本质上相同大小及形状的各种不同电路。由于可在无需设计及构造用于不同IC封装的裸片的情况下且在无需通过在封装的内部表面上蚀刻单独金属层的平常现有技术方法制作外部无源电路的情况下提供不同电路，因此可实现产生时间及成本的显著节约。印刷无源电路层不具有经蚀刻金属电路的高分辨率，但此分辨率对于封装级的无源电路并非必需的。因此，申请者的印刷无源电路层执行与经蚀刻无源电路层相同的功能，但花费时间及成本的一部分。
虽然本文中详细描述了具有导电油墨印刷电路层的IC封装的某些特定实施例，但所属领域的技术人员将了解，可以其它方式构造具有导电油墨印刷电路层的IC封装。举例来说，不是具有适于附接到球栅阵列的电路路由层，而是，IC封装可具有电连接到裸片及印刷电路层的引线框架。印刷电路层可印刷于安置于引线框架上面或下面的非导电层上，其中印刷电路层电连接到引线框架。权利要求书打算广泛地理解为涵盖所有此些替代实施例，而不受现有技术限制。

Claims (20)

1.一种集成电路IC封装，其包含：
IC裸片；及
导电油墨印刷无源电路层，其电连接到所述IC裸片。
2.根据权利要求1所述的IC封装，所述IC封装包含囊封所述IC裸片及所述无源电路层的囊封剂层。
3.根据权利要求1所述的IC封装，其进一步包含为经蚀刻金属信号路由层及经镀敷金属信号路由层中的一者的信号路由层，其中所述裸片及所述印刷电路层各自电连接到所述信号路由层。
4.根据权利要求3所述的IC封装，其中所述裸片线接合附接到所述信号路由层。
5.根据权利要求2所述的IC封装，所述无源电路元件包含电容器、电阻器及电感器中的至少一者。
6.根据权利要求3所述的IC封装，其中所述裸片定位于所述信号路由层上面，且所述导电油墨印刷电路层定位于所述裸片与所述信号路由层之间。
7.根据权利要求3所述的IC封装，其中所述裸片定位于所述信号路由层上面，且所述导电油墨印刷电路层定位于所述信号路由层下面。
8.根据权利要求7所述的IC封装，其进一步包含定位于所述信号路由层与所述导电油墨印刷电路层之间的衬底。
9.根据权利要求8所述的IC封装，所述衬底具有底部表面，其中所述导电油墨印刷电路层印刷于所述衬底底部表面上。
10.根据权利要求9所述的IC封装，其中所述导电油墨印刷电路层经由所述衬底中的孔而电连接到所述信号路由层。
11.根据权利要求9所述的IC封装，其进一步包含球栅阵列，所述球栅阵列具有定位于所述衬底下面且经由延伸穿过所述衬底中的多个导通孔的多个导通体而电附接到所述信号路由层的多个球，且其中所述导电油墨印刷电路层经由所述导通孔中的至少一者电连接到所述信号路由层。
12.一种制作集成电路“IC”封装的方法，其包含：
将电路印刷到所述IC封装的非导电层上，所述电路具有至少一个无源元件；及
将IC裸片电连接到所述电路。
13.根据权利要求12所述的方法，其中将所述IC裸片电连接到所述电路包含：
将所述裸片电连接到路由电路，及
将所述电路电连接到所述路由电路。
14.根据权利要求12所述的方法，其中所述印刷电路包含用导电油墨喷墨印刷所述电路。
15.根据权利要求12所述的方法，其中所述印刷电路包含用导电油墨丝网印刷所述电路。
16.根据权利要求12所述的方法，其中所述印刷电路包含印刷电阻器图案。
17.根据权利要求12所述的方法，其中所述印刷电路包含印刷电容器图案。
18.根据权利要求12所述的方法，其中印刷电路包含印刷电感器图案。
19.根据权利要求12所述的方法，其中所述印刷电路包含在阻焊剂层上印刷导电油墨层及在封装底部衬底层上印刷导电油墨层中的一者。
20.一种集成电路“IC”封装，其包含：
IC裸片，其具有上面带有多个接触垫的上部表面，及底部表面；
经图案化金属信号路由层，其定位于所述裸片的所述底部表面下面且具有顶部表面及底部表面，所述信号路由层的所述顶部表面线接合附接到所述裸片上的所述接触垫中的至少一者；
聚酰亚胺带衬底，其定位于所述IC裸片及所述信号路由层下面，且具有顶部表面及底部表面且具有在其所述顶部与底部表面之间延伸的多个导通体；
至少一个阻焊剂层，其提供于所述聚酰亚胺带衬底及所述信号路由层中的一者上；
导电油墨印刷无源电路层，其印刷于所述聚酰亚胺带衬底及所述阻焊剂层中的一者上且电连接到所述信号路由层；
囊封层，其囊封所述IC裸片、所述经蚀刻金属信号路由层、所述导电油墨印刷层及所述聚酰亚胺带衬底的至少一部分；及
球栅阵列，其定位于所述聚酰亚胺带衬底下面且经由所述导通体而电附接到所述经蚀刻金属信号路由层。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104093284A (zh) * 2014-07-25 2014-10-08 惠州市金百泽电路科技有限公司 一种通过pcb布线设计形成板上电容的方法
CN112888515A (zh) * 2018-10-01 2021-06-01 德州仪器公司 喷墨印刷的电子组件
CN115483033A (zh) * 2022-09-02 2022-12-16 深圳聚源新材科技有限公司 电容器、电路板及电路板埋容工艺
CN112888515B (zh) * 2018-10-01 2024-04-26 德州仪器公司 喷墨印刷的电子组件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8847349B2 (en) * 2012-12-21 2014-09-30 Texas Instruments Incorporated Integrated circuit package with printed circuit layer
US9559036B1 (en) 2014-08-01 2017-01-31 Altera Corporation Integrated circuit package with plated heat spreader
US9496171B2 (en) 2014-09-26 2016-11-15 Texas Instruments Incorporated Printed interconnects for semiconductor packages
US9524926B2 (en) 2014-09-26 2016-12-20 Texas Instruments Incorporated Packaged device with additive substrate surface modification
US10727085B2 (en) 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
US10916448B2 (en) * 2018-07-05 2021-02-09 Texas Instruments Incorporated Method for creating a wettable surface for improved reliability in QFN packages

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181008B1 (en) * 1998-11-12 2001-01-30 Sarnoff Corporation Integrated circuit power supply
US6459588B1 (en) * 1998-07-08 2002-10-01 Dai Nippon Printing Co., Ltd. Noncontact IC card and fabrication method thereof
US20040155322A1 (en) * 2003-02-07 2004-08-12 Sung-Dae Cho Semiconductor package with pattern leads and method for manufacturing the same
US20050194454A1 (en) * 2004-02-06 2005-09-08 T-Ink, Llc Personal card system featuring integrated circuit
US20060154434A1 (en) * 2005-01-10 2006-07-13 Endicott Interconnect Technologies, Inc. Method of making an internal capacitive substrate for use in a circuitized substrate and method of making said circuitized substrate
CN101523594A (zh) * 2006-10-05 2009-09-02 日本电气株式会社 半导体封装和用于制造半导体封装的方法
US20110039212A1 (en) * 2005-01-10 2011-02-17 Das Rabindra N Circuitized substrate with internal resistor, method of making said circuitized substrate, and electrical assembly utilizing said circuitized substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US7791424B2 (en) * 2002-10-15 2010-09-07 Marvell World Trade Ltd. Crystal oscillator emulator
KR100678419B1 (ko) 2005-04-01 2007-02-02 삼성전기주식회사 기판의 표면처리방법, 배선형성방법 및 배선기판
KR100999506B1 (ko) 2008-09-09 2010-12-09 삼성전기주식회사 인쇄회로기판 및 그 제조 방법
KR20100083391A (ko) 2009-01-13 2010-07-22 삼성에스디아이 주식회사 인쇄회로기판용 도전성 잉크 조성물의 제조 방법 및 인쇄회로기판의 제조방법
KR101082443B1 (ko) 2009-08-19 2011-11-11 삼성에스디아이 주식회사 도전성 잉크, 상기 도전성 잉크를 이용한 금속 배선의 형성 방법 및 상기 방법에 의하여 제조된 인쇄회로 기판
US8847349B2 (en) * 2012-12-21 2014-09-30 Texas Instruments Incorporated Integrated circuit package with printed circuit layer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459588B1 (en) * 1998-07-08 2002-10-01 Dai Nippon Printing Co., Ltd. Noncontact IC card and fabrication method thereof
US6181008B1 (en) * 1998-11-12 2001-01-30 Sarnoff Corporation Integrated circuit power supply
US20040155322A1 (en) * 2003-02-07 2004-08-12 Sung-Dae Cho Semiconductor package with pattern leads and method for manufacturing the same
US20050194454A1 (en) * 2004-02-06 2005-09-08 T-Ink, Llc Personal card system featuring integrated circuit
US20060154434A1 (en) * 2005-01-10 2006-07-13 Endicott Interconnect Technologies, Inc. Method of making an internal capacitive substrate for use in a circuitized substrate and method of making said circuitized substrate
US20110039212A1 (en) * 2005-01-10 2011-02-17 Das Rabindra N Circuitized substrate with internal resistor, method of making said circuitized substrate, and electrical assembly utilizing said circuitized substrate
CN101523594A (zh) * 2006-10-05 2009-09-02 日本电气株式会社 半导体封装和用于制造半导体封装的方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104093284A (zh) * 2014-07-25 2014-10-08 惠州市金百泽电路科技有限公司 一种通过pcb布线设计形成板上电容的方法
CN104093284B (zh) * 2014-07-25 2017-05-31 惠州市金百泽电路科技有限公司 一种通过pcb布线设计形成板上电容的方法
CN112888515A (zh) * 2018-10-01 2021-06-01 德州仪器公司 喷墨印刷的电子组件
CN112888515B (zh) * 2018-10-01 2024-04-26 德州仪器公司 喷墨印刷的电子组件
CN115483033A (zh) * 2022-09-02 2022-12-16 深圳聚源新材科技有限公司 电容器、电路板及电路板埋容工艺

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