CN103855121A - 具有拉伸应力的封装半导体器件及其制造方法 - Google Patents

具有拉伸应力的封装半导体器件及其制造方法 Download PDF

Info

Publication number
CN103855121A
CN103855121A CN201310756734.8A CN201310756734A CN103855121A CN 103855121 A CN103855121 A CN 103855121A CN 201310756734 A CN201310756734 A CN 201310756734A CN 103855121 A CN103855121 A CN 103855121A
Authority
CN
China
Prior art keywords
chip
thickness
carrier
articulamentum
tensile stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310756734.8A
Other languages
English (en)
Inventor
R·奥特伦巴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103855121A publication Critical patent/CN103855121A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053—Bonding environment
    • H01L2224/85095—Temperature settings
    • H01L2224/85099—Ambient temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

具有拉伸应力的封装半导体器件及其制造方法。公开了一种组装的半导体器件及制造组装的半导体器件的方法。在一个实施例中，该组装的器件包括具有第一厚度的载体、设置在该载体上的连接层以及设置在该连接层上的芯片，该芯片具有第二厚度，其中该第二厚度大于该第一厚度。

Description

具有拉伸应力的封装半导体器件及其制造方法
技术领域
本发明通常涉及封装的半导体元件，并且更加具体地，涉及封装的平面半导体芯片。
背景技术
对于具有增强的性能、更多不同的功能以及改善的可靠性的半导体器件的消费市场需求已经在所有涉及的技术领域推动了技术的创新。对于构成了单个或多个芯片制造的最后阶段的封装和组装领域来说也是如此。封装提供了芯片和芯片载体之间的必要的互连，并且提供了组装中的保护性的外壳以保护其免受化学或机械损伤。
在封装的元件中，热机械引起的应力缺陷的存在是影响电子器件的使用寿命的关键问题。对于这些器件，在器件界面处的分层或裂纹形成，或者焊点失效是典型的问题。
发明内容
根据本发明的一个实施例，一种组装的器件包括包含第一厚度的载体、设置在该载体上的连接层以及设置在该连接层上的芯片，该芯片包含第二厚度，其中该第二厚度大于该第一厚度。
根据本发明的一个实施例，一种组装的器件包括载体、设置在该载体上的连接层以及包含顶表面和底表面的平面芯片，该平面芯片以底表面设置在该连接层上，其中该平面芯片的顶表面包含拉伸应力。
根据本发明的一个实施例，一种组装的器件包括载体、设置在该载体上的连接层以及包含顶表面和底表面的芯片，该芯片以底表面设置在该连接层上，该芯片进一步包括在该顶表面处的第一源/漏接触以及在该顶表面处的第二源/漏接触，其中该芯片包括在该第一源/漏接触和该第二源漏接触之间的拉伸应力。
根据本发明的一个实施例，一种制造半导体器件的方法包括将半导体衬底的底主表面放置在引线框架上，从而在该半导体衬底的顶主表面处形成拉伸应力，该引线框架相较于该半导体衬底包括更大的厚度。
附图说明
为了更加完整地理解本发明及其优点，现在参考下面结合附图进行的描述，其中：
图1示出了芯片/载体组件的截面图，其中图1a描绘了在结合开始时芯片到载体的附着的组件，同时图1b示出了冷却之后的结合的组件；
图2示出了在半导体元件的顶表面处包含拉伸应力的封装的平面半导体元件的实施例的截面图；
图3示出了实验数据的图表，说明了在硅芯片的底表面处的对于硅/铜引线框架厚度的不同结合的不同应力水平。
图4示出了实验数据的图表，说明了在硅芯片的顶表面处的对于硅/铜引线框架厚度的不同结合的不同应力水平；以及
图5示出了制造封装的平面半导体元件的方法的实施例，该封装的平面半导体元件在其半导体衬底的顶部区域中包括拉伸应力。
具体实施方式
在下文中详细地讨论了当前的优选实施例的制造和使用。然而，应当意识到，本发明提供了多种可应用的发明构思，其能够体现在各种各样的特定上下文中。讨论的特定实施例仅仅示出了制造和使用本发明的特定的途径，并且不限制本发明的范围。
将关于在特定的上下文中的实施例，即关于封装的平面半导体器件描述本发明。然而，本发明还可以应用于其他封装的半导体器件或封装的元件。
半导体元件的封装通常包括将元件(例如，管芯或芯片)附着至元件载体，从而形成机械和/或电气元件载体接触。
在高温下，通常在200℃至400℃的范围内的温度下，执行将管芯结合至载体。图1以简化的方式示出了管芯至载体组装的初始和最终阶段。图1a示出了在半导体管芯110、连接层120和管芯载体130的第一物理接触时刻的组装的半导体器件100。在这个阶段，在结合工艺的开始，该组件100还未形成源自该管芯110/载体130接合的应力。相反，图1b示出了在结合工艺完成之后的组装的状态150。在中间，该组装的半导体器件100被加热至高温并且随后被冷却至室温。
在该冷却阶段过程中，该组件100/150的所有元件将经受基于所涉及的材料的热膨胀系数(CTE)的收缩力。因为所涉及的材料的CTE通常是不同的----如果进行CTE匹配尝试，其可能仅仅部分地降低了CTE失配----该冷却的组件150将包括得自于该管芯110/载体130接合的内部应力。这将导致在该组件150中的机械变形，引起该组件150的层的轻微的向上或向下弯曲。图1b以夸大的方式示出了向下弯曲。例如，当采用展示相对高的CTE的金属载体130时，可以观察到这种类型的变形。
该组装的封装元件150的每一个单独的部件可以影响在该封装的元件150中的其他部件。特别地，厚层相比于薄层可能对于应力诱发的变形具有更强的影响。例如，厚层的相互位置越近并且它们之间的CTE差越大，变形可能越高。
所观察到的应力性质上可以是拉伸的或压缩的。通过公认的命名法，拉伸应力通过正值表示并且压缩应力通过负值表示。在该封装的元件150的特定区域内观察到的应力可以是不均匀的并且依赖方位的。在该半导体芯片110的顶部区域内的应力与在该芯片110的底部区域内的应力相比，在量值和/或符号方面可以是不同的。类似地，该载体区域130、在该载体130的外围处的132相对于中间载体区域136可以展示出相当较低的表面翘曲和较低的应力值。
在电元件的体系结构中产生的应力可能成为可靠性问题。这是众所周知的。然而，使用应力来改善在封装结构中的半导体器件的电性能是未知的。
本发明的实施例基于元件载体界面而使用压缩和/或拉伸应力，从而改善元件的电性能。多种实施例提供了拉伸应力至平面器件的顶部主表面(有源器件定位于此)并且在该平面器件的底部主表面处提供了压缩应力。在一些实施例中，该拉伸应力包括超过100MPa的值。
在一些实施例中，通过在平行于电流方向的方向上存在拉伸应力来改善器件性能。此外，在一些实施例中，应当避免在平行于电流方向的方向上的压缩应力，因为其降低了器件性能。在多种实施例中，该拉伸应力引起了电子迁移率的增加，导致了在速度和功率消耗方面的器件性能优势。相信有效电子质量的降低和电子散射的降低是导致观察到的电子迁移率增加的机制。
图2示出了封装的半导体元件200的实施例的截面图。该封装的半导体元件200包括半导体芯片210，该半导体芯片210通过连接层250结合至芯片载体260的中间部分262。该半导体芯片210包括半导体衬底220。通过端子层230覆盖该衬底220的上部第一主表面222。背面金属化(BSM)层240设置于该半导体衬底220的第二主表面224之下，其中该第二主表面224面对该载体260。此外，该封装的元件200包括互连部件270、272、274，互连部件270、272、274从该端子层230的限定区域(或元件接触)延伸至该载体260的外围部分264、266、268。此外，通过密封剂280全部地或者部分地围住该半导体芯片210、所述互连270、272、274以及该芯片载体260。
在多种实施例中，该半导体衬底220可以包括例如硅或锗的单一元素半导体材料。可替换地，该半导体衬底220包括例如SiC、SiGe、InP、InAs、GaAs、GaN或GaP的复合半导体材料。该半导体衬底220可以仅包括单体半导体材料，或者可替换地，可以包括设置在体半导体之上的外延半导体层的组合。例如，外延或者体半导体层的厚度可以等于或者大于20μm、50μm或者100μm。该半导体衬底220的总厚度可以高达1000μm。在一些实施例中，该半导体衬底220可以包括绝缘体上硅(SOI)衬底。
上文所述的几个半导体材料具有在2.3ppm/K至7ppm/K的范围内的CTE值。Si和GaN的CTE可以分别低至2.3ppm/K和3.2ppm/K。例如，具有相对高的CTE的半导体材料是Ge(5.8至5.9ppm/K)或GaAs(5.7至6.9ppm/K)。
该半导体芯片210可以包括平面功率器件，例如，平面功率MOSFET(金属氧化物半导体场效应晶体管)，该平面功率MOSFET包括源极、漏极和栅极区域，所有这些区域沿着该第一主表面222对齐。可替换地，该半导体芯片210可以包括另一种类型的半导体器件，例如无源器件、MEMS或者光电器件。该半导体芯片210可以是独立器件或者集成电路。
在一个实施例中，该半导体芯片210包括背面金属化(BSM)层240，该BSM层240设置在该半导体衬底220的该第二主表面224之下。该BSM层240可以包括包含金属或者金属合金材料的单层或者多层。例如，该BSM层240可以是Al/Fi/NiV的三层堆叠、包含Al/Ti或者Al/TiW的双层堆叠，或者其可以是更加复杂的成分(例如A1/Ti/Cu/Sn/Ag或者A1/TiW/Cu/Sn/Ag)。BSM堆叠240的总厚度可以在0.5μm至5μm的范围内。可替换地，该BSM层240包括在0.1μm和10μm之间的厚度。配置该BSM层(堆叠)240以促进从该半导体芯片210至该载体260的有效热传递。
该载体260包括中间部分262和外围区域(例如264、266、268)，该芯片210安装在该中间部分262之上。该载体260可以是金属引线框架，该金属引线框架包括CTE≥15ppm/K的材料，例如铜(CTE16.6至17.6ppm/K)、黄铜(CTE～20ppm/K)或铝(CTE23至24ppm/K)。该引线框架260的厚度可以在50μm至1000μm的范围内，或者可替换地，在100μm和500μm之间。
在一些实施例中，具有显著高于所应用的半导体衬底220的CTE的CTE的刚性材料可以被应用作为载体260的材料。如下面所解释的，低CTE材料，例如CTE范围在4ppm/K至8ppm/K之间的大部分陶瓷或者CuMo，可能不太适合于本发明的一些实施例。另一方面，具有的CTE在10.5ppm/K左右的氧化锆陶瓷可以适合作为载体材料，虽然其CTE值比传统的金属引线框架材料的CTE低大致30％。
该连接层250促进了该芯片210至该载体260的结合。在一1实施例中，该连接层250可以包括能够结合至该金属引线框架260的焊接材料，例如AuSn、AgSn、CuSn或SnSb。在一些实施例中，该焊料层可以展示出高的刚性并且尽可能薄以最小化其作为应力缓冲层的有效性，该应力缓冲层减轻了源自该管芯/载体接合的应力。在一个实施例中，该焊接材料的厚度可以小于20μm。该焊料层250厚度可以低至1μm至3μm。如传统应用中经常使用的，在50μm和100μm之间的焊料厚度可能不适合于本发明的各种实施例。
在可替换的实施例中，该连接层240可以是导电的或不导电的、有机的或无机的粘接层。有机粘接层可以包括混合有交联成分的环氧树脂、环氧树脂/聚氨酯、聚酯或聚酰亚胺树脂。导电粘接层可以另外包括金属/合金的纳米颗粒(高达85体积％)，所述金属/合金例如为Ag、Cu、Au、涂覆Ag的Ni或者镀Au的Ni。导电粘接膜相对于非导电粘接膜可以提供更好的导热性，从而提供从该半导体器件至该载体260的更加有效的散热。施加的粘接层的厚度可以是低的，例如小于50μm。可替换地，该厚度可以在5μm至20μm的范围内。
设置在该半导体衬底220的第一主表面222之上的端子层230可以包括导电接触焊盘(未示出)，互连部件(例如270、272、274)附着至所述导电接触焊盘。接触焊盘可以包括一层或多层高导电率金属(例如Cu、Al、Ni)、金属合金、焊接材料、导电粘合剂或其组合。此外，该端子层230可以包括绝缘部分(未示出)，绝缘部分将接触焊盘彼此电绝缘。例如，该端子层230的这些绝缘部件可以包括氧化硅或氮化硅。接触焊盘可以电连接至有源器件部件。例如，接触焊盘可以设置在平面功率MOSFET的源极、漏极和栅极区域之上。
该互连部件270、272、274可以在该端子层230中的接触焊盘和该引线框架264、266、268的外围部分(所谓的外部焊盘)之间建立导电路径。这种互连可以是直径范围在16μm和500μm之间的线结合。例如，线结合可以包括Au、Cu、Ag或Al。预定义的结构(所谓的线夹)的预制造(冲压出)的金属部分可以替换地被采用以代替线结合。通常地，对于未在图2中示出的其他的可用的元件体系结构，在该芯片210的顶部区域和该载体260之间的互连还可以通过其他的方式形成，例如，通过采用垂直穿过该芯片210建立并且通过焊球接合的方式连接至该载体260的直通通孔。
此外，该封装的电元件200包括密封剂280，其全部或部分地围住该芯片210、该载体260以及互连部件270、272、274。该密封剂280可以包括环氧树脂、聚丙烯酸酯、聚亚安酯、聚砜、聚酰亚胺或聚醚酰亚胺化合物，或其他的聚合物化合物。当使用包括弹性模量E值在13000MPa左右的灌封材料时，可能期望灌封体280对作用于关键器件区域的机械力的贡献保持为小的。可替换地，密封剂280可以是叠层而不是模塑料。
在多种实施例中，靠近该半导体衬底220的顶表面的区域225包括平行于该第一主表面222的拉伸应力。配置该拉伸应力区域225以提供在大约0.1A和100A之间的电流。该区域225可以设置在该半导体器件210的第一源/漏区域与该半导体器件的第二源/漏区域之间。在一些实施例中，拉伸应力值等于或高于100MPa。在其他实施例中，避免高于1GPa的拉伸应力值以便最小化在该封装的元件200中的应力引起的缺陷，例如分层或裂纹。
在该半导体衬底220的顶部区域225内的拉伸应力主要由在该管芯210/载体260接合处的机械力引起。在一些实施例中，该半导体衬底220和该载体260对该拉伸应力区域具有最强的影响，而其他的来源，例如管芯/密封剂210/280的界面、该BSM层240或者该连接层250起次要作用。
在各种实施例中，影响器件区域225中的拉伸应力的最具影响力的参数是该半导体衬底220和该载体260的CTE的差。在一些实施例中，如果该半导体衬底220的厚度Dsub大于该载体260的)厚度Dcarr，则器件210性能提高。例如，Dsub应当尽可能大并且Dcarr应当尽可能薄。在一些实施例中，避免了在区域225处或者在顶表面222处的压缩应力。
在一些实施例中，该连接层250尽可能小以避免缓冲效果。特别地，厚连接层250可以减轻在该半导体衬底220和该载体之间的CTE差。
在一些实施例中，在该半导体器件210的表面处的拉伸应力改善了平面器件的电子迁移率。特别地，相比于传统的器件，大大降低了电阻率。
在一些实施例中，该衬底220的CTE与该载体260的CTE之间的较大的差在接合区域中产生了更高的应力。在多种实施例中，该载体的CTE比该半导体器件的CTE高至少2倍。
图3和4示出了在芯片底面(图3)和芯片顶面(图4)处对于不同的硅衬底220和引线框架260厚度的所得到的应力值。这两个图示出关于一组具有变化的硅和引线框架厚度值的硅管芯/铜引线框架组件的实验数据。硅厚度在10μm和725μm之间变化，并且铜引线框架的厚度在50μm和1000μm之间变化。在从300℃的结合温度冷却之后，测量的应力值涉及该组装的半导体器件200。
关于图3，在硅厚度和铜引线框架厚度的整个研究范围内在芯片底面处发现了压缩应力。对于从250μm至1000μm的铜厚度范围，随着硅厚度增加，该压缩应力降低(意味着向较低的负值偏移)。这一趋势对于超过200μm的硅厚度趋于稳定，除了50μm Cu情况之外，在该情况中该趋势继续升高至研究的硅厚度范围(725μm)的上部端点。
图4示出了在芯片顶部区域处的应力值，该芯片顶部区域包括与电子迁移率/器件性能增强相关的硅区域。对于从250μm至1000μm的厚度范围的铜引线框架，硅芯片厚度的增加与从压缩应力到拉伸应力的逐步偏移一致。对于50μm的引线框架厚度，对于60μm和100μm的硅厚度发现了最高的拉伸应力值，但是如果该硅厚度进一步升高超过100μm，则该拉伸应力降低。
在一个实施例中，该半导体衬底220的厚度Dsub与该载体260厚度Dcarr的比率在1和2之间变化(例如，1≤Dsub/Dcarr≤1.33；1.33≤Dsub/Dcarr≤1.66或者1.66≤Dsub/Dcarr≤2)。相反，传统建造的元件的半导体衬底厚度在很多情况下明显薄于所采用的载体的厚度。通常传统元件的总芯片厚度是其载体厚度的大约一半。
图5示出了制造封装的平面半导体元件的实施例的流程图，该封装的平面半导体元件在其半导体衬底的顶部区域中包括拉伸应力。
在第一步骤510中，在半导体衬底之中/之上制造多个平面半导体器件。步骤510代表致力于沿着该半导体衬底的上部主表面形成有源器件部件和互连的一系列处理步骤。在步骤515中，在该半导体衬底的上部主表面上形成端子或钝化层。该端子层使该半导体器件的第一主表面上的接触焊盘彼此绝缘。
在步骤520中，可选地减薄该半导体衬底。晶片典型地开始为标准厚度并且需要减薄至预定的最佳厚度值。例如，可以通过磨削或研磨实现晶片薄化。磨削工具可以采用磨轮。研磨工具使用包括在两个表面之间起作用的磨料颗粒的液体(称为“浆”)。化学机械抛光(CMP)是晶片薄化的进一步的工艺选择，其利用机械磨蚀和化学腐蚀的结合。
在接下来的步骤525中，背面金属化(BSM)层可以可选地形成在该半导体衬底的背面之上(例如，晶片的背面)。该晶片可以暂时将其上部主表面粘合至支撑晶片。然后在该衬底背面之上沉积背面金属化(BSM)层。该BSM层可以包括一层或多层金属或金属合金。可能的材料选择已经在上文中提到。例如，可以通过离子束溅射、反应溅射、电镀或化学气相沉积(CVD)来沉积该BSM层。较高的溅射温度可以促成在顶部芯片区域中的较高的拉伸应力。
在步骤530中，将包括器件的半导体晶片切割或者分离成独立的芯片。例如，可以通过锯或激光切割该半导体晶片。
随后，在步骤535中，准备载体以用于通过在该载体的顶表面处的定义的区域之上沉积连接层材料来附着被单体化的芯片中的至少一个。在一个实施例中，应用高刚性的扩散焊接材料。AuSn、AgSn、CuSn或AgIn可以用作焊接材料。可以通过施加电镀、气相沉积或蒸发溅射技术以毯式沉积(blanket deposition)在整个载体之上形成焊料层。随后，通过传统的光刻和蚀刻步骤的结合，或者通过采用高能量的Nd：YAG或准分子激光器的激光烧蚀，可以从预期为无焊料的区域移除该焊料。可替换地，通过施加例如边缘屏蔽、喷涂/喷洒施加或丝网印刷(例如施加焊膏)的技术来选择性地置放焊料层。
在另一个实施例中，金属油墨层可以选择性地施加至该载体。金属油墨包括包含金属/合金材料的颗粒，所述金属/合金材料例如为Ag、Cu或涂覆Ag的Cu或Ni。金属油墨颗粒可以是几十nm的尺寸。
在另一个实施例中，使用膏分配系统，导电或者不导电的粘接膏可以作为连接层施加至该载体上的定义的位置。粘接膏包括溶剂。在膏沉积之后，在烤箱里通过干燥工艺或者通过热气流去除该溶剂。该粘接膏的干燥之后是在大约100℃至大约250℃的温度的几分钟的对其固化。可替换地，粘接材料可以以粘接箔的预制部分的形式(称为预制件)被施加。这种预制件的厚度可以从5μm变动至10μm。如果预制件材料包括UV敏感元件，该预制件可以被UV固化达大约1秒至大约20秒，固化时间取决于预制件的厚度。可替换地，可以在大约130℃至大约160℃的范围内的温度下实施热固化，固化时间从大约20秒变动至大约60秒。
在步骤540中，将至少一个半导体芯片附着至该载体，其中非有源芯片背面面对该载体。第一芯片利用常规的拾取和放置设备被拾取并且放置在预热的载体的定义的部分之上。随后在高温将准确对准的芯片结合至该载体。在一些实施例中，可以重复拾取、放置和芯片至载体结合。
结合温度取决于连接材料的性质。如果选择的附着层包括扩散焊接材料，可以施加热压缩结合以将芯片附着至载体。对于扩散焊接材料的结合温度通常在大约300℃至大约400℃的范围内。为了在管芯/载体接合处获得更高的应力，可以优选在大约350℃和大约400℃之间变动的温度下实施结合。对于75％Au/25％Sn焊料结合的典型的工艺条件是：1200nm、360℃、350ms、结合力3.3N/mm2、结合软延迟150ms、在结合通道中形成气氛(85％N2+15％H2)。
在进一步的实施例中，该芯片和该载体可以与断续的金属油墨层在大约200℃和大约250℃之间的温度下烧结在一起，同时施加在大约1MPa至大约5MPa的范围内的压强达1分钟至2分钟。在再一个实施例中，该芯片/载体结合可以涉及结合至粘接膜或膏的导电或不导电层。对于这种材料，结合温度可以在大约180℃和大约250℃之间变动。
在步骤545中，附着互连部件。将线结合或外部线夹的末端结合至该半导体芯片和该载体的端子层处的相应的接触焊盘。如果该载体是金属引线框架，则该互连部件被结合至该引线框架的外围的外部焊盘。对于单个互连，经常使用直径范围在大约16μm至大约40μm的Au线结合。显著地，直径范围在大约100μm和大约500μm之间的较厚的Al线通常被施加用于电气系统的加载路径中的互连。结合的线末端可以是球形或者是楔形。可以使用氢火焰或者通过应用电容放电技术来实现球形线末端的形成。可以在具有10％H2的Ar的屏蔽气氛中实施球形结合，同时将N2+10％H2用于楔形结合。
三种不同线结合技术是可用的：超声结合、热压缩结合和热超声结合。超声结合仅可应用于楔形结合形成。另两种技术可以用于球形结合或者用于楔形结合。超声结合利用在大约20kHz至大约60kHz范围内的超声能量，在20ms左右的结合时间期间在室温施加每一线结合0.5g至2.5g的结合负荷。对于铝线，超声楔形结合是优选的结合方法。在大约300℃和大约500℃之间变动的温度下实施热压缩结合，施加每一线结合15g至25g的结合负荷。热超声结合使用热、超声能量(在60-120kHz的范围内)和压强的组合。相比于热压缩结合所使用的，可以采用较低的热量和较低的压强来实施热超声结合。对于这种结合技术，从125℃变动至150℃的温度以及在每一线结合0.5g和2.5g之间的结合负荷是足够的。
在步骤550中，全部或者部分地灌封附着的元件、附着的互连以及该载体。灌封材料可以包括模塑料、叠层或团块状顶部涂层。可以应用用于具有介电材料的灌封的各种技术，例如压缩模塑、传递模塑、注射模塑、粉料或液体模塑、配给或层压。
在高容量制造中，将多个电元件附着至载体。在一个实施例中，通过锯或者激光器切割包含一个载体和多个半导体元件的灌封的组件，并且从而将其分离成独立的封装的半导体元件。这在步骤555中示出。
虽然已经详细地描述了本发明及其优点，但是应当理解在不脱离如由所附权利要求限定的本发明的精神和范围的情况下，在此能够进行各种改变、替换和更改。
此外，本申请的范围不打算局限于说明书中描述的工艺、机器、制造、物质的成分、方式、方法和步骤的特定实施例。本领域普通技术人员将容易地从本发明的公开意识到，根据本发明可以利用当前存在的或者后来开发的工艺、机器、制造、物质的成分、方式、方法或步骤，其与在此描述的相应实施例执行基本相同的功能或者实现基本相同的结果。因此，所附权利要求打算将这种工艺、机器、制造、物质的成分、方式、方法或步骤包括在它们的范围之内。

Claims (20)

1.一种组装的器件，包括：
包含第一厚度的载体；
设置在该载体上的连接层；以及
设置在该连接层上的芯片，该芯片包含第二厚度，
其中该第二厚度大于该第一厚度。
2.根据权利要求1所述的组装的器件，其中该第二厚度等于或大于50μm并且该第一厚度等于或小于50μm。
3.根据权利要求1所述的组装的器件，其中该第二厚度等于或大于100μm并且该第一厚度等于或小于100μm。
4.根据权利要求1所述的组装的器件，其中该连接层包含第三厚度，该第三厚度在1μm和3μm之间。
5.根据权利要求4所述的组装的器件，其中该连接层是扩散焊料层。
6.根据权利要求1所述的组装的器件，其中该芯片的顶表面包含拉伸应力并且其中该芯片的底表面包含压缩应力。
7.根据权利要求6所述的组装的器件，其中该拉伸应力等于或大于100MPa。
8.一种组装的器件，包括：
载体；
设置在该载体上的连接层；以及
包含顶表面和底表面的平面芯片，该平面芯片以底表面设置在该连接层上，
其中该平面芯片的该顶表面包含拉伸应力。
9.根据权利要求8所述的组装的器件，其中该拉伸应力等于或大于100MPa。
10.根据权利要求9所述的组装的器件，在该芯片的该底表面处进一步包含压缩应力。
11.根据权利要求10所述的组装的器件，进一步包含
连接芯片接触焊盘与载体接触焊盘的互连；以及
灌封该载体、该连接层和该平面芯片的灌封件。
12.根据权利要求8所述的组装的器件，其中该连接层包含等于或小于20μm的厚度。
13.一种组装的器件，包括：
载体；
设置在该载体上的连接层；以及
包含顶表面和底表面的芯片，该芯片以底表面设置在该连接层上，该芯片进一步包含在该顶表面处的第一源/漏接触以及在该顶表面处的第二源/漏接触，
其中该芯片包含在该第一源/漏接触和该第二源漏接触之间的拉伸应力。
14.根据权利要求13所述的组装的器件，其中该拉伸应力等于或大于100MPa。
15.根据权利要求13所述的组装的器件，其中该芯片包含功率半导体器件。
16.根据权利要求15所述的组装的器件，其中该连接层包含具有等于或小于20μm的厚度的有机粘接层或无机粘接层。
17.根据权利要求15所述的组装的器件，其中该连接层包含具有等于或小于3μm的厚度的扩散焊接层。
18.一种制造半导体器件的方法，该方法包括：
将具有底部主表面的半导体衬底放置在引线框架之上从而在该半导体衬底的顶部主表面处形成拉伸应力，该引线框架包含比该半导体衬底大的厚度。
19.根据权利要求18所述的方法，进一步包含在将该半导体衬底放置在该引线框架上之前，减薄该半导体衬底。
20.根据权利要求18所述的方法，其中将该半导体衬底放置在该引线框架之上包含将该半导体衬底扩散焊接在该引线框架之上。
CN201310756734.8A 2012-11-30 2013-11-30 具有拉伸应力的封装半导体器件及其制造方法 Pending CN103855121A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/691,587 2012-11-30
US13/691,587 US10229870B2 (en) 2012-11-30 2012-11-30 Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress

Publications (1)

Publication Number Publication Date
CN103855121A true CN103855121A (zh) 2014-06-11

Family

ID=50726162

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310756734.8A Pending CN103855121A (zh) 2012-11-30 2013-11-30 具有拉伸应力的封装半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US10229870B2 (zh)
CN (1) CN103855121A (zh)
DE (1) DE102013113232A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599787A (zh) * 2019-02-20 2020-08-28 英飞凌科技股份有限公司 以压缩应变可靠安装的电子芯片

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9726587B2 (en) * 2015-01-30 2017-08-08 Stmicroelectronics S.R.L. Tensile stress measurement device with attachment plates and related methods
US9412848B1 (en) * 2015-02-06 2016-08-09 Globalfoundries Inc. Methods of forming a complex GAA FET device at advanced technology nodes
US9728934B2 (en) * 2015-08-31 2017-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Back-side-emitting vertical cavity surface emitting laser (VCSEL) wafer bonded to a heat-dissipation wafer, devices and methods
DE202016101688U1 (de) 2016-03-30 2016-04-21 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit einem Schaltungsträger
IT201800004756A1 (it) 2018-04-20 2019-10-20 Procedimento di realizzazione di un dispositivo semiconduttore sottoposto a sollecitazioni e relativo dispositivo semiconduttore sottoposto a sollecitazioni
EP3627546A1 (en) 2018-09-24 2020-03-25 Infineon Technologies AG Power semiconductor module arrangement
CN113299549A (zh) * 2021-05-21 2021-08-24 深圳市联冀电子有限公司 小信号管芯背金工艺

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876053B1 (en) * 1999-08-13 2005-04-05 Intel Corporation Isolation structure configurations for modifying stresses in semiconductor devices
US20090166826A1 (en) * 2007-12-27 2009-07-02 Janducayan Omar A Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049976A (en) * 1989-01-10 1991-09-17 National Semiconductor Corporation Stress reduction package and process
US6333553B1 (en) * 1999-05-21 2001-12-25 International Business Machines Corporation Wafer thickness compensation for interchip planarity
MY133357A (en) * 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
US6703707B1 (en) 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
US7145254B2 (en) * 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
US20040089926A1 (en) 2002-11-12 2004-05-13 Taiwan Ic Packaging Corporation Ultra thin semiconductor device
US7452786B2 (en) 2004-06-29 2008-11-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film integrated circuit, and element substrate
US7679145B2 (en) 2004-08-31 2010-03-16 Intel Corporation Transistor performance enhancement using engineered strains
US7626275B2 (en) * 2005-12-16 2009-12-01 Mitsubishi Electric Corporation Semiconductor device
US7534715B2 (en) 2005-12-29 2009-05-19 Intel Corporation Methods including fluxless chip attach processes
US7508012B2 (en) * 2006-01-18 2009-03-24 Infineon Technologies Ag Electronic component and method for its assembly
US20070205253A1 (en) * 2006-03-06 2007-09-06 Infineon Technologies Ag Method for diffusion soldering
US20080023805A1 (en) * 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US9147665B2 (en) 2007-11-06 2015-09-29 Fairchild Semiconductor Corporation High bond line thickness for semiconductor devices
US7808100B2 (en) * 2008-04-21 2010-10-05 Infineon Technologies Ag Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element
US8178976B2 (en) 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
JP2010040835A (ja) * 2008-08-06 2010-02-18 Toshiba Corp 積層型半導体装置の製造方法
US8124983B2 (en) * 2008-08-28 2012-02-28 Infineon Technologies Ag Power transistor
US8177878B2 (en) * 2009-11-30 2012-05-15 Infineon Technologies Ag Bonding material with exothermically reactive heterostructures
US8513798B2 (en) 2010-09-09 2013-08-20 Infineon Technologies Ag Power semiconductor chip package
US8802553B2 (en) * 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
US8461645B2 (en) 2011-03-16 2013-06-11 Infineon Technologies Austria Ag Power semiconductor device
US20120313190A1 (en) 2011-06-09 2012-12-13 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Packaged device including interposer for increased adhesive thickness and method of attaching die to substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6876053B1 (en) * 1999-08-13 2005-04-05 Intel Corporation Isolation structure configurations for modifying stresses in semiconductor devices
US20090166826A1 (en) * 2007-12-27 2009-07-02 Janducayan Omar A Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599787A (zh) * 2019-02-20 2020-08-28 英飞凌科技股份有限公司 以压缩应变可靠安装的电子芯片

Also Published As

Publication number Publication date
US20140151866A1 (en) 2014-06-05
DE102013113232A1 (de) 2014-06-05
US10229870B2 (en) 2019-03-12

Similar Documents

Publication Publication Date Title
CN103855121A (zh) 具有拉伸应力的封装半导体器件及其制造方法
US10090185B2 (en) Semiconductor device and manufacturing method thereof
US9685426B2 (en) Package-on-package semiconductor device
US20220181314A1 (en) Semiconductor device using emc wafer support system and fabricating method thereof
US20200043817A1 (en) Integrated circuits protected by substrates with cavities, and methods of manufacture
CN102683279B (zh) 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法
CN102881665B (zh) 用于晶片级封装的系统和方法
US8513061B2 (en) Method of fabricating a TSV for 3D packaging of semiconductor device
US10276545B1 (en) Semiconductor package and manufacturing method thereof
US8883566B2 (en) Method of manufacturing semiconductor device, semiconductor device and multilayer wafer structure
US20070025684A1 (en) Connection Structure Semiconductor Chip and Electronic Component Including the Connection Structure and Methods for Producing the Connection Structure
US9418922B2 (en) Semiconductor device with reduced thickness
US9093437B2 (en) Packaged vertical power device comprising compressive stress and method of making a packaged vertical power device
TWI713171B (zh) 半導體裝置以及其製造方法
JP2011003715A (ja) 半導体装置
CN113471188B (zh) 半导体封装及其制造方法
US9165792B2 (en) Integrated circuit, a chip package and a method for manufacturing an integrated circuit
EP1949441A2 (en) Chip assembly and method of manufacturing thereof
US7811862B2 (en) Thermally enhanced electronic package
US20140077388A1 (en) Semiconductor device and method of manufacturing the same
TWI841586B (zh) 晶片封裝方法
JP2018182125A (ja) 半導体素子及び半導体装置
CN117790417A (zh) 半导体电路和器件制造方法、晶圆复合体和半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140611