CN103839870A - Method for reducing side-wall roughness of TSV during TSV etching - Google Patents
Method for reducing side-wall roughness of TSV during TSV etching Download PDFInfo
- Publication number
- CN103839870A CN103839870A CN201210470510.6A CN201210470510A CN103839870A CN 103839870 A CN103839870 A CN 103839870A CN 201210470510 A CN201210470510 A CN 201210470510A CN 103839870 A CN103839870 A CN 103839870A
- Authority
- CN
- China
- Prior art keywords
- etching
- tsv
- silicon
- silicon via
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
The invention discloses a method for reducing the side-wall roughness of a through silicon via (TSV) during TSV etching. The method includes the following steps: step1: after the TSV etching is completed, oxidizing the side wall of the TSV in a reaction chamber; and step2: in the reaction chamber, etching the oxidized side wall of the TSV and removing an oxidization layer formed through oxidization of the side wall of the TSV. The method for reducing the side-wall roughness of the TSV during the TSV etching is capable of reducing the roughness of the side wall of the TSV.
Description
Technical field
The present invention relates to a kind of TSV etching technics, particularly a kind of method of improving through-silicon via sidewall roughness for TSV etching.
Background technology
Along with the integrated level of integrated circuit improves constantly, the develop rapidly that semiconductor technology also continues.Semiconductor technology evolves is walked miniaturization Road Development along Moore's Law and has been arrived 22nm at present, has approached its physics limit.Now, introduce other relevant new technologies and just can facilitate further developing of integrated circuit.Wherein, silicon through hole (Through Silicon Via, TSV) technology be current rare one fast-developing, and can have influence on widely the technical field of consumption and industrial electronics, 3-D IC that it brings is integrated is constantly promoting the integrated development with encapsulation technology of multi-chip.
TSV is by between chip and chip, make vertical conducting between wafer and wafer, realize the state-of-the-art technology interconnecting between chip, it has realized short, the abundantest Z direction interconnection, chip-stacked integrated by difference in functionality, can realize simultaneously more function, better performance, lower power consumption and cost, strive for larger manufacture flexibility.
The most key in TSV technology is exactly etching, i.e. the formation of silicon through hole.Because semi-conductor silicon chip substrate all has suitable thickness conventionally, the technique that forms through hole is plasma etch process, at present, the conventional technology in TSV etching field is the assorted etching technics of ripple (Bosch process), can form the vertical through hole that depth-to-width ratio is quite high.In the time keeping higher rate of etch, it is used for maintaining vertical section to keep dark etching characteristic.Even, in the extremely short time interval of switching, under the detection of high power, still can see the surface that it is coarse between etching and passivation.This roughness is unwanted, and process engineer need to constantly be minimized or remove.
Summary of the invention
The object of this invention is to provide a kind of method of improving through-silicon via sidewall roughness for TSV etching, can greatly lower the roughness of through-silicon via sidewall.
In order to realize above object, the present invention is achieved by the following technical solutions:
Improve a method for through-silicon via sidewall roughness for TSV etching, first form silicon through hole, also comprise following steps:
Step 1: through-silicon via sidewall is oxidized, to form oxide layer;
Step 2: the sidewall to the silicon through hole after oxidation carries out etching, removes the sidewall of silicon through hole through being oxidized the oxide layer forming.
In described step 1, adopt containing oxygen plasma or other carrier of oxygen and excite the plasma of generation to be oxidized the sidewall of silicon through hole.
The described plasma containing oxygen plasma or oxygen-containing gas is following any one or appoints multinomial: O
2, O
3, N
2o, CO
2, steam.
In described step 2, adopt the plasma of carbon containing fluorine to carry out etching to the sidewall of silicon through hole.
The plasma of described carbon containing fluorine is by following any one or appoint multinomial generation: the C that excites
4f
8, CF
4, C
4f
6, CHF
3, CH
2f
2.
The rf frequency of the etching in described step 2 is double frequency, and its medium-high frequency frequency is 27MHz ~ 60MHz, and Frequency is 2MHz ~ 13.56MHz.
In described step 2, the technological parameter of etching is: power is 200W ~ 1000W, and bias power is 300W ~ 1500W, and the cavity air pressure of reaction chamber is 20Mt ~ 200Mt.
In described step 2, adopt plasma, the O of carbon containing fluorine
2and/or A
rplasma carry out etching.
In described step 2, when the plasma of employing carbon containing fluorine carries out etching, its optionally ratio to silica and silicon is greater than 5:1.
After step 2 etching, the height of the out-of-flatness projection of through-silicon via sidewall is less than or equal to 51nm.
The present invention compared with prior art, has the following advantages:
Can greatly lower the roughness of through-silicon via sidewall.
Brief description of the drawings
Fig. 1 is after TSV etching, the shape schematic diagram of through-silicon via sidewall;
Fig. 2 is the principle schematic that step 1 of the present invention is oxidized through-silicon via sidewall;
Fig. 3 is the principle schematic of the effect after oxidation in Fig. 2;
Fig. 4 is that step 2 of the present invention is carried out the effect schematic diagram after etching to the through-silicon via sidewall after being oxidized;
Fig. 5 a is the design sketch of Fig. 1;
Fig. 5 b is the design sketch of Fig. 4.
Embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
Improve a method for through-silicon via sidewall roughness for TSV etching, first form silicon through hole, also comprise following steps:
Step 1: after TSV etching completes (state of silicon through hole as shown in Figure 1), in reaction chamber, sidewall 1 to silicon through hole is oxidized, as shown in Figures 2 and 3, the rough surface of the sidewall 1 of silicon through hole will be oxidized to different forms, between the key area of two relatively flats or at many recesses in fan-shaped, it is the out-of-flatness projection 11 of the sidewall 1 of silicon through hole, for oxidized more region, the not concordant oxidation of rough surface is by not concordant oxide layer 2 of 1 output of the sidewall at silicon through hole, out-of-flatness projection 11 places that are the sidewall 1 of silicon through hole can produce relatively more oxide layer 2(as shown in Figure 3).In the present embodiment, adopt containing oxygen plasma or other carrier of oxygen and excite the plasma of generation to be oxidized the sidewall 1 of silicon through hole, wherein, be following any one or appoint multinomial containing the plasma of oxygen plasma or oxygen-containing gas: O
2, O
3, N
2o, CO
2, steam.
Step 2: in reaction chamber, the sidewall 1 of the silicon through hole after oxidation is carried out to etching, remove the sidewall 1 of silicon through hole through being oxidized the oxide layer forming.In the present embodiment, adopt the plasma of carbon containing fluorine to carry out etching to the sidewall 1 of silicon through hole, wherein, the plasma of carbon containing fluorine is by following any one or appoint multinomial generation: the C that excites
4f
8, CF
4, C
4f
6, CHF
3, CH
2f
2, certainly, in step 2, can also adopt the plasma of carbon containing fluorine and other gases (for example: O
2and/or A
rplasma) carry out etching.The rf frequency of the etching in this step is double frequency, and its medium-high frequency frequency is 27MHz ~ 60MHz, and Frequency is 2MHz ~ 13.56MHz.Concrete etching technics parameter is: power: 200W ~ 1000W, bias power: 300 ~ 1500W, the cavity air pressure of reaction chamber: 20 ~ 200Mt.In the present embodiment, when the plasma of employing carbon containing fluorine carries out etching, its optionally ratio to silica and silicon is greater than 5:1, therefore, oxide layer can be removed fast, very small but silicon layer damages, as shown in Figure 4, therefore, can effectively remove by the out-of-flatness projection 11 of how oxidized through-silicon via sidewall 1.Therefore, after step 2 etching, the height of the out-of-flatness projection 11 of through-silicon via sidewall 1 is not more than 51nm(as shown in Figure 5 b), because the height of the out-of-flatness projection 11 after TSV etching is 238nm left and right (as shown in Figure 5 a), therefore, greatly lowered the roughness of through-silicon via sidewall 1.
In sum, the present invention improves the method for through-silicon via sidewall roughness for TSV etching, has greatly lowered the roughness of through-silicon via sidewall.
Above-mentioned execution mode just to exemplary illustration of the present invention and and non-limiting its protection range, therefore, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art have read after foregoing, for the replacement that is equal to of of the present invention done partial structurtes, will be all apparent, all within protection scope of the present invention.
Claims (10)
1. a method of improving through-silicon via sidewall roughness for TSV etching, first forms silicon through hole, it is characterized in that, also comprises following steps:
Step 1: through-silicon via sidewall is oxidized, to form oxide layer;
Step 2: the sidewall to the silicon through hole after oxidation carries out etching, removes the sidewall of silicon through hole through being oxidized the oxide layer forming.
2. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 1, is characterized in that, in described step 1, adopts containing oxygen plasma or other carrier of oxygen and excites the plasma of generation to be oxidized the sidewall of silicon through hole.
3. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 2, is characterized in that, the described plasma containing oxygen plasma or oxygen-containing gas is following any one or appoints multinomial: O
2, O
3, N
2o, CO
2, steam.
4. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 1, is characterized in that, in described step 2, adopts the plasma of carbon containing fluorine to carry out etching to the sidewall of silicon through hole.
5. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 4, is characterized in that, the plasma of described carbon containing fluorine is by following any one or appoint multinomial generation: the C that excites
4f
8, CF
4, C
4f
6, CHF
3, CH
2f
2.
6. as described in claim 1 or 4, improve the method for through-silicon via sidewall roughness for TSV etching, it is characterized in that, the rf frequency of the etching in described step 2 is double frequency, and its medium-high frequency frequency is 27MHz ~ 60MHz, and Frequency is 2 MHz ~ 13.56MHz.
7. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 6, it is characterized in that, in described step 2, the technological parameter of etching is: power is 200W ~ 1000W, and bias power is 300W ~ 1500W, and the cavity air pressure of reaction chamber is 20Mt ~ 200Mt.
8. as described in claim 1 or 4, improve the method for through-silicon via sidewall roughness for TSV etching, it is characterized in that, in described step 2, adopt plasma, the O of carbon containing fluorine
2and/or A
rplasma carry out etching.
9. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 4, is characterized in that, in described step 2, when the plasma of employing carbon containing fluorine carries out etching, its optionally ratio to silica and silicon is greater than 5:1.
10. the method for improving through-silicon via sidewall roughness for TSV etching as claimed in claim 1, is characterized in that, after step 2 etching, the height of the out-of-flatness projection of through-silicon via sidewall is less than or equal to 51nm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210470510.6A CN103839870B (en) | 2012-11-20 | 2012-11-20 | The method improving through-silicon via sidewall roughness in TSV etches |
| TW102139827A TWI544540B (en) | 2012-11-20 | 2013-11-01 | A method for improving the sidewall roughness of silicon vias in TSV etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210470510.6A CN103839870B (en) | 2012-11-20 | 2012-11-20 | The method improving through-silicon via sidewall roughness in TSV etches |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103839870A true CN103839870A (en) | 2014-06-04 |
| CN103839870B CN103839870B (en) | 2016-08-17 |
Family
ID=50803245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210470510.6A Active CN103839870B (en) | 2012-11-20 | 2012-11-20 | The method improving through-silicon via sidewall roughness in TSV etches |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103839870B (en) |
| TW (1) | TWI544540B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611027A (en) * | 2017-08-16 | 2018-01-19 | 江苏鲁汶仪器有限公司 | A kind of method for improving deep silicon etching sidewall roughness |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070047016A (en) * | 2005-11-01 | 2007-05-04 | 매그나칩 반도체 유한회사 | Method of forming a deep trench in semiconductor device |
| TW200919606A (en) * | 2007-10-09 | 2009-05-01 | Shinko Electric Ind Co | Method of manufacturing substrate |
| TW201044461A (en) * | 2009-05-08 | 2010-12-16 | Lam Res Corp | Strip with reduced low-k dielectric damage |
| CN102315157A (en) * | 2010-08-11 | 2012-01-11 | 上海集成电路研发中心有限公司 | Method for forming and correcting TSV (through silicon via) |
-
2012
- 2012-11-20 CN CN201210470510.6A patent/CN103839870B/en active Active
-
2013
- 2013-11-01 TW TW102139827A patent/TWI544540B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070047016A (en) * | 2005-11-01 | 2007-05-04 | 매그나칩 반도체 유한회사 | Method of forming a deep trench in semiconductor device |
| TW200919606A (en) * | 2007-10-09 | 2009-05-01 | Shinko Electric Ind Co | Method of manufacturing substrate |
| TW201044461A (en) * | 2009-05-08 | 2010-12-16 | Lam Res Corp | Strip with reduced low-k dielectric damage |
| CN102315157A (en) * | 2010-08-11 | 2012-01-11 | 上海集成电路研发中心有限公司 | Method for forming and correcting TSV (through silicon via) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611027A (en) * | 2017-08-16 | 2018-01-19 | 江苏鲁汶仪器有限公司 | A kind of method for improving deep silicon etching sidewall roughness |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201426849A (en) | 2014-07-01 |
| TWI544540B (en) | 2016-08-01 |
| CN103839870B (en) | 2016-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7344867B2 (en) | Selective deposition of SiN on horizontal surfaces | |
| TWI654760B (en) | High aspect ratio etch with combination mask | |
| KR20130141436A (en) | Etching method | |
| CN101752291B (en) | Method for making shallow groove isolation structure | |
| CN101800174A (en) | Plasma etching method of carbon-containing layer | |
| JP6093929B2 (en) | Method for manufacturing silicon substrate having concavo-convex structure with high aspect ratio | |
| KR20110011571A (en) | Plasma etch method to reduce micro-loading | |
| CN102130045B (en) | Processing method of through holes | |
| CN104658962A (en) | Through hole forming method | |
| CN102737961A (en) | Method for reducing collapsing or shift of photoresist (PR) mask | |
| CN102610560B (en) | Method for modifying appearances of side walls of through holes | |
| WO2009036053A2 (en) | Tuning via facet with minimal rie lag | |
| CN101562122B (en) | Dry etching method and silicon wafer etching method | |
| CN103839870B (en) | The method improving through-silicon via sidewall roughness in TSV etches | |
| US20090065479A1 (en) | Dry etching method of high-k film | |
| CN110854019A (en) | Semiconductor manufacturing method | |
| CN103700622B (en) | The forming method of silicon through hole | |
| CN101567313A (en) | Grid manufacturing method | |
| CN105390433A (en) | Semiconductor device manufacturing method | |
| JP2014150149A (en) | Etching method and etching device | |
| CN113410136A (en) | Silicon carbide groove etching method | |
| CN103887146B (en) | Utilize the high aspect ratio microstructures lithographic method of switchable power generator | |
| JP5961794B2 (en) | Method for manufacturing silicon substrate having concavo-convex structure with high aspect ratio | |
| CN102420124B (en) | Etching method of dielectric layer | |
| CN102903667A (en) | Method for forming semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee after: Medium and Micro Semiconductor Equipment (Shanghai) Co., Ltd. Address before: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee before: Advanced Micro-Fabrication Equipment (Shanghai) Inc. |
|
| CP01 | Change in the name or title of a patent holder |