CN103832970A - Low-temperature wafer bonding method - Google Patents
Low-temperature wafer bonding method Download PDFInfo
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- CN103832970A CN103832970A CN201210491190.2A CN201210491190A CN103832970A CN 103832970 A CN103832970 A CN 103832970A CN 201210491190 A CN201210491190 A CN 201210491190A CN 103832970 A CN103832970 A CN 103832970A
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Abstract
The invention discloses a low-temperature wafer bonding method which comprises the steps: cleaning two wafers; depositing an oxide layer on the surfaces of the two cleaned wafers; activating the surface of at least one of the two wafers; enabling the surfaces of the two wafers the surfaces of which are activated in a non-vacuum environment to be in mutual contact and applying an external force to ensure that the two wafers are bonded; and performing low-temperature annealing on the bonded wafers.
Description
Technical field
The present invention relates to wafer bond techniques field, especially a kind of low-temperature wafer bonding method, at least one in two wafers can have the device of processing or can process at least partly in the method.The method of this preparation is for silicon and non-silicon base CMOS device, IC device, the integrated wafer bond techniques of photoelectric device.
Background technology
Along with the development of integrated circuit, insulator silicon (SOI) technology is known as the era of nanotechnology by industry and replaces one of solution of existing single crystal silicon material, is large sharp weapon that maintain Moore's Law tendency.
SOI material is the basis of SOI technical development, and high-quality SOI material is the primary factor that restriction SOI technology enters large-scale industrial production always.In recent years, along with the continuous maturation of SOI material preparation technology, the problem of materials of restriction SOI technical development is just progressively solved.The technology of preparing of SOI material comprises two kinds after all, i.e. the injection oxygen isolation technology take Implantation as representative (Sepration-by-oxygen implantation, i.e. SIMOX) and wafer bond techniques.
SIMOX Technology Need high temperature Implantation and the annealing of follow-up superhigh temperature, this technology can have damage to SIMOX material.Because thereby not guaranteeing to make cost, the stability of quality of materials increasing.Wafer bond techniques is the technology that same SIMOX synchronized development gets up, and both lay particular emphasis on different application demand separately.Wafer bond techniques (Wafer Bonding) is to utilize two bright finished, clean crystal column surfaces to combine.While adopting wafer bonding and thinning technique formation soi structure, not only have technique simple, with low cost, to advantages such as device not damageds, and the SOI material of preparing still has good characteristic.Wafer current bonding techniques mainly comprises anode linkage, silicon direct bonding, eutectic bonding, thermocompression bonding, metal bonding, glass solder bonding etc., above-mentioned wafer bond techniques all relates to the high temperature anneal, process time is long, the high temperature producing in bonding process causes adverse effect to MEMS device performance, such as high temperature causes cause thermal damage (as the high temperature that exceedes 400 ℃ will damage CMOS aluminium circuit) to the temperature-sensitive circuit on wafer and micro-structural; High temperature is easily introduced impurity, causes the redistribution of substrate doping; For two larger wafers of thermal expansion coefficient difference, after high-temperature process, can cause very large distortion and residual thermal stress, directly have influence on device performance and encapsulation yield rate.
Proposed in recent years the thought of low-temperature wafer bonding, low-temperature wafer bonding mainly contains solder bonding, viscose bonding, surface active bonding etc.But because the bond strength of viscose bonding and solder bonding is lower, device serviceability temperature is limited, and application is very limited.Although and the low-temperature surface activation bonding bonding technology time is long, due to surface activation process and process annealing, thereby make bond strength can meet follow-up element manufacturing.
The development of MEMS and photoelectric technology, integrated and the system in package of three-dimensional has been proposed to new requirement, research can meet the larger homogeneity of coefficient of thermal expansion differences or two heterogeneous backing material bondings require and bonding after device is become to the inevitable of technical development without the new low-temperature wafer bonding techniques damaging.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to overcome the defect of prior art, and a kind of method of low-temperature wafer bonding is provided, and to meet the bonding between any two level and smooth backing materials, makes bonding techniques not be subject to the impact of backing material character.
(2) technical scheme
For achieving the above object, the invention provides a kind of low-temperature wafer bonding method, comprising: two wafers are cleaned; Two crystal column surface deposition one deck oxides after cleaning; At least one in two wafers carried out to surface activation process; Two wafers after surface activation process are contacted and apply external force relative to each other at non-vacuum environment lower surface and make its bonding; And wafer after para-linkage carries out process annealing processing.
In such scheme, in the described step that two wafers are cleaned, adopt chemical cleaning method.
In such scheme, described two wafers are also comprised after cleaning: two wafers are cleaned and/or polishing.
In such scheme, in the step of described two crystal column surface deposition one deck oxides after cleaning, described deposition adopts MOCVD, PECVD, ALD, sputter, means of electron beam deposition or pulse laser deposition, and described oxide is the one in silica, aluminium oxide, hafnium oxide or lanthana.
In such scheme, described at least one in two wafers carried out in the step of surface activation process, and described surface activation process is to adopt O
2, N
2, SF
6in plasma-activated processing, a kind of at least one in two wafers carried out surface activation process, or adopts O
2, N
2, SF
6multiplely in plasma-activated processing successively at least one in two wafers carried out to surface activation process.
In such scheme, described at least one in two wafers carried out in the step of surface activation process, and described surface activation process is to carry out in the temperature range of 16 ℃-26 ℃.
In such scheme, described two wafers after surface activation process are contacted relative to each other and applied in the step that external force makes its bonding at non-vacuum environment lower surface, non-vacuum environment refers to the environment of air ambient or thousand grades of ultra-clean chambers.
In such scheme, described two wafers after surface activation process are contacted relative to each other and applied in the step that external force makes its bonding at non-vacuum environment lower surface, the bonding pressure adopting is 100Kg-1000kg, and preferably, described bonding pressure is 200kg-500kg.
In such scheme, the wafer after described para-linkage carries out in the step of process annealing processing, and the annealing temperature of employing is 100 ℃-400 ℃.
(3) beneficial effect
Compared with existing wafer bond techniques, tool of the present invention has the following advantages:
1, because bonding region is oxide, so low-temperature wafer bonding method provided by the invention can any two substrates of bonding or device.
2, low-temperature wafer bonding method provided by the invention, adopts low-temperature wafer bonding techniques, avoided the destruction to temperature-sensitive circuit and micro-structural, and efficiency is high.
3, low-temperature wafer bonding method provided by the invention need to not complete under vacuum or low vacuum environment, and the extruding force needing in the time of bonding is smaller.
Accompanying drawing explanation
Fig. 1 is the method flow diagram according to the low-temperature wafer bonding of the embodiment of the present invention;
Fig. 2 is the schematic diagram according to the wafer before bonding of the embodiment of the present invention;
Fig. 3 is the process chart before bonding according to the embodiment of the present invention, and wherein Fig. 3 (a) is flow chart of steps, and Fig. 3 (b) is the effect schematic diagram corresponding with step shown in Fig. 3 (a).
Fig. 4 is according to the structural representation after the wafer bonding of the embodiment of the present invention.
Fig. 5 is according to the ultrasonic scanning figure after the wafer bonding of the embodiment of the present invention.
The specific embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This low-temperature wafer bonding method provided by the invention, first two wafers are cleaned, then deposit the thin oxide layer of one deck at the bonding region of two plates respectively, and the oxide layer depositing at least one wafer is wherein carried out to surface activation process, the oxide layer of two wafers handling well is sticked together relatively, finally send into bonder and apply extruding force, thereby realize the bonding of two wafers.
As shown in Figure 1, Fig. 1 shows the method flow diagram according to the low-temperature wafer bonding of the embodiment of the present invention, and the method comprises the following steps:
Step 1: two wafers are cleaned; In this step, adopt chemical cleaning method to clean two wafers, specifically comprise: utilize organic solvent (isopropyl alcohol, absolute ethyl alcohol, methyl alcohol or acetone) to wash surface and oil contaminant, utilize the method for ultrasonic cleaning to remove surperficial adsorption particle, then utilize the method for pickling to get rid of metal ion and stain.
In addition, after being cleaned, two wafers also comprise: two wafers are cleaned and/or polishing, specifically comprise: in the time that the roughness of crystal column surface is larger (being conventionally greater than 2nm), generally need to carry out surface chemical mechanical polishing polishing, make its surface roughness reach the demand (being conventionally less than 1nm) that is applicable to bonding chip.
Step 2: two crystal column surface deposition one deck oxides after cleaning; At least one in two wafers carried out to surface activation process; In this step, described deposition adopts MOCVD, PECVD, ALD, sputter, means of electron beam deposition or pulse laser deposition, and described oxide is the one in silica, aluminium oxide, hafnium oxide or lanthana; Described surface activation process is to adopt O
2, N
2, SF
6in plasma-activated processing, a kind of at least one in two wafers carried out surface activation process, or adopts O
2, N
2, SF
6multiplely in plasma-activated processing successively at least one in two wafers carried out to surface activation process; Described surface activation process is at room temperature to carry out, and preferably in the temperature range of 16 ℃-26 ℃, carries out.
Step 3: two wafers after surface activation process are contacted and apply external force relative to each other at non-vacuum environment lower surface and make its bonding; In this step, non-vacuum environment refers to the environment of air ambient or thousand grades of ultra-clean chambers, and the bonding pressure of employing is 100Kg-1000kg, and preferably, described bonding pressure is 200kg-500kg.
Step 4: the wafer after para-linkage carries out process annealing processing; In this step, the annealing temperature of employing is 100 ℃-400 ℃.
Fig. 2 to Fig. 4 shows the process chart according to the low-temperature wafer bonding of the embodiment of the present invention.
As shown in Figure 2, being used for the former substrate 1 of bonding is Silicon Wafer, and former substrate 2 is gaas wafers.
As shown in Figure 3, substrate 1 and substrate 2 through a series of processing, comprising: cleaning, deposition oxide, surface activation process before bonding.For the improved RCA cleaning method of substrate 1 use, 2 of substrates are used simple cleaning method.On clean substrate 1 after cleaning and substrate 2, with method deposition one deck oxide 3 of ALD, oxide 3 is aluminium oxide.Then use O
2plasma, then carries out activation processing with N2 plasma on oxide 3 surfaces.
Two crystal column surfaces by manual mode, Fig. 3 being handled well under the environment of thousand grades of ultra-clean chambers as shown in Figure 4 stick together relatively, then put into bonder and apply certain extruding force.Wafer after extruding for example, is annealed by suitable temperature (100 ℃-400 ℃) to being placed in annealing furnace.
As shown in Figure 5, the ultrasonic scanning figure after bonding shows: when the power of oxygen gas plasma activation is 100W, when the power of nitrogen gas plasma activation is 100W, effectively bonding area accounts for 98% of whole area.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a low-temperature wafer bonding method, is characterized in that, comprising:
Two wafers are cleaned;
Two crystal column surface deposition one deck oxides after cleaning;
At least one in two wafers carried out to surface activation process;
Two wafers after surface activation process are contacted and apply external force relative to each other at non-vacuum environment lower surface and make its bonding; And
Wafer after para-linkage carries out process annealing processing.
2. low-temperature wafer bonding method according to claim 1, is characterized in that, in the described step that two wafers are cleaned, adopts chemical cleaning method.
3. low-temperature wafer bonding method according to claim 1, is characterized in that, described two wafers is also comprised after cleaning:
Two wafers are cleaned and/or polishing.
4. low-temperature wafer bonding method according to claim 1, it is characterized in that, in the step of described two crystal column surface deposition one deck oxides after cleaning, described deposition adopts MOCVD, PECVD, ALD, sputter, means of electron beam deposition or pulse laser deposition, and described oxide is the one in silica, aluminium oxide, hafnium oxide or lanthana.
5. low-temperature wafer bonding method according to claim 1, is characterized in that, described at least one in two wafers carried out in the step of surface activation process, and described surface activation process is to adopt O
2, N
2, SF
6in plasma-activated processing, a kind of at least one in two wafers carried out surface activation process, or adopts O
2, N
2, SF
6multiplely in plasma-activated processing successively at least one in two wafers carried out to surface activation process.
6. low-temperature wafer bonding method according to claim 1, is characterized in that, described at least one in two wafers carried out in the step of surface activation process, and described surface activation process is to carry out in the temperature range of 16 ℃-26 ℃.
7. low-temperature wafer bonding method according to claim 1, it is characterized in that, described two wafers after surface activation process are contacted relative to each other and applied in the step that external force makes its bonding at non-vacuum environment lower surface, non-vacuum environment refers to the environment of air ambient or thousand grades of ultra-clean chambers.
8. low-temperature wafer bonding method according to claim 1, it is characterized in that, described two wafers after surface activation process are contacted relative to each other and applied in the step that external force makes its bonding at non-vacuum environment lower surface, the bonding pressure of employing is 100Kg-1000kg.
9. low-temperature wafer bonding method according to claim 8, is characterized in that, described bonding pressure is 200kg-500kg.
10. low-temperature wafer bonding method according to claim 1, is characterized in that, the wafer after described para-linkage carries out in the step of process annealing processing, and the annealing temperature of employing is 100 ℃-400 ℃.
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Cited By (13)
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| CN105118804A (en) * | 2015-09-29 | 2015-12-02 | 厦门大学 | Method of preparing germanium on insulator by passivating ultrathin silicon film |
| CN105185720A (en) * | 2015-08-03 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Ultrathin thermo-oxidizing wafer bonding technology for bonding strength enhancement |
| CN105206536A (en) * | 2015-08-17 | 2015-12-30 | 武汉新芯集成电路制造有限公司 | Wafer bonding method for improving bonding strength and structure |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN108288582A (en) * | 2018-01-11 | 2018-07-17 | 北京华碳科技有限责任公司 | A kind of wafer scale GaN device substrate transfer method |
| CN108365083A (en) * | 2018-02-07 | 2018-08-03 | 济南晶正电子科技有限公司 | The manufacturing method of composite piezoelectric substrate for SAW device |
| WO2019029237A1 (en) * | 2017-08-10 | 2019-02-14 | Yangtze Memory Technologies Co., Ltd. | Wafer bonding method and structure thereof |
| CN109346495A (en) * | 2018-11-21 | 2019-02-15 | 德淮半导体有限公司 | Wafer bonding method |
| CN110148603A (en) * | 2019-05-28 | 2019-08-20 | 上海华力微电子有限公司 | The manufacturing method of back-illuminated type CMOS optical sensor |
| CN110164894A (en) * | 2019-05-28 | 2019-08-23 | 上海华力微电子有限公司 | A kind of bonding method |
| CN110289209A (en) * | 2019-07-05 | 2019-09-27 | 长春长光圆辰微电子技术有限公司 | A kind of processing method of SOI wafer |
| CN110993607A (en) * | 2019-11-21 | 2020-04-10 | 长江存储科技有限责任公司 | Memory device with barrier structure and preparation method thereof |
| CN117174728A (en) * | 2023-11-02 | 2023-12-05 | 合肥新晶集成电路有限公司 | Wafer processing method and wafer structure |
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| CN105185720A (en) * | 2015-08-03 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Ultrathin thermo-oxidizing wafer bonding technology for bonding strength enhancement |
| CN105206536A (en) * | 2015-08-17 | 2015-12-30 | 武汉新芯集成电路制造有限公司 | Wafer bonding method for improving bonding strength and structure |
| CN105206536B (en) * | 2015-08-17 | 2018-03-09 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method and structure for strengthening bond strength |
| CN105118804A (en) * | 2015-09-29 | 2015-12-02 | 厦门大学 | Method of preparing germanium on insulator by passivating ultrathin silicon film |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| US10679854B2 (en) | 2017-08-10 | 2020-06-09 | Yangtze Memory Technologies Co., Ltd. | Wafer bonding method and structure thereof |
| WO2019029237A1 (en) * | 2017-08-10 | 2019-02-14 | Yangtze Memory Technologies Co., Ltd. | Wafer bonding method and structure thereof |
| US11342185B2 (en) | 2017-08-10 | 2022-05-24 | Yangtze Memory Technologies Co., Ltd. | Wafer bonding method and structure thereof |
| CN108288582A (en) * | 2018-01-11 | 2018-07-17 | 北京华碳科技有限责任公司 | A kind of wafer scale GaN device substrate transfer method |
| CN108288582B (en) * | 2018-01-11 | 2020-12-01 | 北京华碳科技有限责任公司 | Wafer-level GaN device substrate transfer method |
| CN108365083A (en) * | 2018-02-07 | 2018-08-03 | 济南晶正电子科技有限公司 | The manufacturing method of composite piezoelectric substrate for SAW device |
| CN109346495A (en) * | 2018-11-21 | 2019-02-15 | 德淮半导体有限公司 | Wafer bonding method |
| CN110164894A (en) * | 2019-05-28 | 2019-08-23 | 上海华力微电子有限公司 | A kind of bonding method |
| CN110148603B (en) * | 2019-05-28 | 2021-05-07 | 上海华力微电子有限公司 | Method for manufacturing back-illuminated CMOS optical sensor |
| CN110148603A (en) * | 2019-05-28 | 2019-08-20 | 上海华力微电子有限公司 | The manufacturing method of back-illuminated type CMOS optical sensor |
| CN110289209A (en) * | 2019-07-05 | 2019-09-27 | 长春长光圆辰微电子技术有限公司 | A kind of processing method of SOI wafer |
| CN110993607A (en) * | 2019-11-21 | 2020-04-10 | 长江存储科技有限责任公司 | Memory device with barrier structure and preparation method thereof |
| CN117174728A (en) * | 2023-11-02 | 2023-12-05 | 合肥新晶集成电路有限公司 | Wafer processing method and wafer structure |
| CN117174728B (en) * | 2023-11-02 | 2024-02-20 | 合肥新晶集成电路有限公司 | Wafer processing method and wafer structure |
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