CN110993607A - Memory device with barrier structure and preparation method thereof - Google Patents
Memory device with barrier structure and preparation method thereof Download PDFInfo
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- CN110993607A CN110993607A CN201911147935.1A CN201911147935A CN110993607A CN 110993607 A CN110993607 A CN 110993607A CN 201911147935 A CN201911147935 A CN 201911147935A CN 110993607 A CN110993607 A CN 110993607A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a memory device with a barrier structure and a preparation method thereof, wherein the method comprises the following steps: providing a first wafer and a second wafer, wherein the first wafer comprises a first wafer bonding surface, the first wafer comprises a memory cell array, the memory cell array comprises at least one channel column, the second wafer comprises a second wafer bonding surface, and the second wafer comprises peripheral circuits; embedding a hydrogen barrier layer in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed close to the bonding surface of the first wafer and/or close to the bonding surface of the second wafer; bonding the first wafer and the second wafer through the first wafer bonding surface and the second wafer bonding surface; annealing is performed under a hydrogen atmosphere. The hydrogen barrier layer can effectively prevent free hydrogen generated in annealing from diffusing into the peripheral circuit structure in the second wafer, reduce adverse effects on the peripheral circuit structure and improve the reliability of the peripheral circuit structure.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a memory device with a barrier structure and a preparation method thereof.
Background
The 3D NAND memory is a flash memory device with three-dimensional stacked memory cells, and is used for higher storage density per unit area compared with a planar NAND memory, and the existing 3D NAND memory cell architecture is generally designed by a vertical channel and horizontal control gate layer, so that the integration level can be increased by times on a wafer per unit area, and the cost can be reduced.
In the novel 3D NAND memory, a CMOS circuit area (CMOS device) is formed by adopting a semiconductor substrate, a memory cell Array area (Array device) is formed by adopting a laminated structure, then the circuits of the CMOS circuit area and the memory cell Array area are connected together by a three-dimensional special process, a wafer where the memory cell Array area is located is thinned from the back, and the circuit is connected, namely the X-stacking technology.
Generally, a hydrogen atmosphere annealing process is performed in a process of forming a 3D NAND memory to repair a semiconductor layer (polysilicon layer) in a channel column in a memory cell array region, and the process may damage a CMOS circuit region and affect reliability of the CMOS circuit region.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a memory device with a blocking structure and a method for manufacturing the same, which are used to solve the problems in the prior art that the annealing process of a hydrogen atmosphere in the manufacturing process of a 3D NAND memory damages a peripheral circuit region, affects the reliability of the peripheral circuit region, and the like.
To achieve the above and other related objects, the present invention provides a method for fabricating a memory device having a barrier structure, the method at least comprising:
providing a first wafer and a second wafer, wherein the first wafer comprises a first wafer bonding surface, the first wafer comprises a memory cell array, the memory cell array comprises at least one channel column, the second wafer comprises a second wafer bonding surface, and the second wafer comprises peripheral circuits;
embedding a hydrogen barrier layer in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed near the first wafer bonding surface and/or near the second wafer bonding surface;
bonding the first wafer and the second wafer through the first wafer bonding surface and the second wafer bonding surface;
annealing is performed under a hydrogen atmosphere.
Optionally, the first wafer further includes a first through array connection portion and a first through array contact portion connected thereto; the second wafer also comprises a second through array connecting part and a second through array contact part connected with the second through array connecting part; when the first wafer and the second wafer are bonded, the first through array contact part is electrically connected with the second through array contact part; and before the annealing step is carried out under the hydrogen atmosphere, a welding pad leading-out layer is formed on one surface of the first wafer, which is far away from the bonding surface of the first wafer, and a welding pad in the welding pad leading-out layer is electrically connected with the first through array connecting part.
Optionally, the distance between the hydrogen barrier layer and the first wafer bonding surface is between 0.5 μm and 1 μm and/or the distance between the hydrogen barrier layer and the second wafer bonding surface is between 0.5 μm and 1 μm.
Optionally, the hydrogen barrier layer has a thickness between
In the meantime.
Optionally, the material of the hydrogen barrier layer comprises aluminum oxide or silicon nitride.
Optionally, at least one hydrogen barrier layer is embedded in the first wafer and/or the second wafer.
Optionally, the hydrogen barrier layer is formed by a furnace tube process, an atomic layer deposition process or a chemical vapor deposition process.
The present invention also provides a memory device having a barrier structure, the memory device comprising at least:
the first wafer comprises a first wafer bonding surface, the first wafer comprises a storage unit array, and the storage unit array comprises at least one channel column;
a second wafer comprising a second wafer bonding surface, the second wafer comprising peripheral circuitry therein;
the first wafer and the second wafer are in bonding connection through the first wafer bonding surface and the second wafer bonding surface;
a hydrogen barrier layer embedded in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed proximate to the first wafer bonding face and/or proximate to the second wafer bonding face.
Optionally, the first wafer further includes a first through array connection portion and a first through array contact portion connected thereto; the second wafer also comprises a second through array connecting part and a second through array contact part connected with the second through array connecting part; the first through array contact part is electrically connected with the second through array contact part; and a welding pad leading-out layer is formed on one surface of the first wafer, which is far away from the bonding surface of the first wafer, and a welding pad in the welding pad leading-out layer is electrically connected with the first through array connecting part.
Optionally, the distance between the hydrogen barrier layer and the first wafer bonding surface is between 0.5 μm and 1 μm and/or the distance between the hydrogen barrier layer and the second wafer bonding surface is between 0.5 μm and 1 μm.
Optionally, the hydrogen barrier layer has a thickness between
In the meantime.
Optionally, the material of the hydrogen barrier layer comprises aluminum oxide or silicon nitride.
Optionally, at least one hydrogen barrier layer is embedded in the first wafer and/or the second wafer.
As described above, according to the memory device with the blocking structure and the manufacturing method thereof of the present invention, the hydrogen blocking layer is embedded in the first wafer and/or the second wafer, and when the subsequent annealing process of the hydrogen atmosphere is performed, the hydrogen blocking layer can effectively block diffusion of the free hydrogen generated during the annealing process from entering the peripheral circuit structure in the second wafer, so as to reduce adverse effects on the peripheral circuit structure and improve reliability of the peripheral circuit structure.
Drawings
Fig. 1 shows an equivalent circuit diagram of a memory cell string of a 3D NAND memory device.
Fig. 2 shows a schematic structure of a memory cell string of a 3D NAND memory device.
Fig. 3 is a flow chart of a method for manufacturing a memory device with a barrier structure according to the present invention.
Fig. 4 to 11 are cross-sectional views showing steps of a method for fabricating a memory device having a barrier structure according to the present invention.
Figure 12 illustrates a cross-sectional view of one embodiment of a memory device having a barrier structure in accordance with the present invention.
Description of the element reference numerals
10 first wafer
101 first wafer bonding surface
102 first through array connection part
103 first through array contact
20 second wafer
201 second wafer bonding face
202 second through array connection
203 second through array contact
30 hydrogen barrier layer
40 pad extraction layer
401 pad
50 memory cell string
501502503 Gate conductor layer
504 channel pillar
505 channel layer
506 tunnel dielectric layer
507 charge storage layer
508 grid dielectric layer
Bonding a D1 hydrogen barrier layer to a first wafer
Distance between faces
Bonding a D2 hydrogen barrier layer to a second wafer
Distance between faces
Thickness of D3 Hydrogen Barrier layer
S1-S8
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the 3D NAND memory formed by adopting the X-stacking technology, the 3D NAND memory comprises a memory cell array wafer and a peripheral circuit wafer. The memory cell array wafer has memory cell transistors, i.e., memory cell strings, formed therein with vertical direction strings on a lateral substrate, so that the memory cell strings extend in a vertical direction with respect to the substrate. A peripheral circuit wafer may be understood to be a peripheral device for 3D NAND memory that includes any suitable digital, analog, and/or mixed signal peripheral circuitry to facilitate 3D memory operations. For example, the peripheral devices may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or active or passive components in any circuit (e.g., transistors, diodes, resistors, or capacitors). In X-stacking technology, the peripheral circuit wafer is typically formed using complementary metal semiconductor (CMOS) technology, so the wafer includes several transistors.
As shown in fig. 1 and 2, an equivalent circuit diagram and a structure diagram of a memory cell string of a 3D NAND memory device are shown. In the case that the memory cell string shown in this example includes 4 memory cells, those skilled in the art will understand that the number of memory cells in the memory cell string is not limited to that shown in the figure, and may be any number, for example, 32 or 64. As shown in fig. 1, the memory cell string 50 has a first terminal connected to a Bit-Line (BL) and a second terminal connected to a Source Line (SL). The memory cell string 50 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The Gate of the first select transistor Q1 is connected to a string select line (SGD), and the Gate of the second select transistor Q2 is connected to a Source select line (SGS). The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.
As shown in fig. 2, the selection transistors Q1 and Q2 of the memory cell string 50 include gate conductor layers 501 and 502, respectively, and the memory transistors M1 to M4 include gate conductor layers 503, respectively. The gate conductor layers 501, 502, and 503 are in accordance with a stacking order of the transistors in the memory cell string 50, adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer to form a gate stack structure, and the memory cell string 50 further includes a channel pillar 504, the channel pillar 504 being adjacent to or penetrating the gate stack structure. In the middle portion of the channel pillar 504, a tunneling dielectric layer 506, a charge storage layer 507, and a gate dielectric layer 508 are interposed between the gate conductor layer 503 and the channel layer 505, thereby forming memory transistors M1 through M4. Gate dielectric layers 508 are sandwiched between gate conductor layers 501 and 502 and channel layer 505 at both ends of channel pillar 504, thereby forming select transistors Q1 and Q2.
Channel layer 505 in the middle portion of channel pillar 504 is typically a doped or undoped semiconductor layer, such as mostly polysilicon material. In the manufacturing process of the 3D NAND memory device, the channel layer 505 may be damaged, for example, by an annealing process, an etching process, or the like, which may cause surface dangling bonds, internal grain boundaries, and intragranular defects in the channel layer 505, and therefore, after the channel pillar manufacturing process is completed, the channel layer 505 in the channel needs to be passivated to remove the defects in the channel layer 505, and generally, an annealing process of a hydrogen atmosphere is applied to the 3D NAND memory device, so that free hydrogen is generated during gas annealing, and the hydrogen enters the channel pillar 504 by diffusion to combine with the defects in the semiconductor layer or the grain boundaries and the dangling bonds on the surface, so that the dangling bonds are saturated, thereby passivating the semiconductor layer (polysilicon layer) in the channel pillar 504.
However, in the X-stacking technique, when the channel pillars are passivated by an annealing process with a hydrogen atmosphere, hydrogen also diffuses into the peripheral circuit wafer, and since the peripheral circuit wafer includes a plurality of transistors, when the hydrogen diffuses into the peripheral wafer, various adverse effects, such as Hot Carrier Injection (HCI) effect, Negative Bias Temperature Instability (NBTI), may be caused, thereby reducing the reliability of the peripheral wafer.
For the above reasons, the present invention provides a method for manufacturing a memory device having a barrier structure, comprising:
providing a first wafer and a second wafer, wherein the first wafer comprises a first wafer bonding surface, the first wafer comprises a memory cell array, the memory cell array comprises at least one channel column, the second wafer comprises a second wafer bonding surface, and the second wafer comprises peripheral circuits;
embedding a hydrogen barrier layer in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed near the first wafer bonding surface and/or near the second wafer bonding surface;
bonding the first wafer and the second wafer through the first wafer bonding surface and the second wafer bonding surface;
annealing is performed under a hydrogen atmosphere.
By embedding a hydrogen barrier layer in the first wafer and/or in the second wafer, and forming the hydrogen barrier layer close to the first wafer bonding face and/or close to the second wafer bonding face. It should be noted that, as will be understood by those skilled in the art, the position of the hydrogen blocking layer in the first wafer and/or the second wafer is necessarily outside the memory cell array and/or outside the peripheral circuit structure. When the annealing process of hydrogen atmosphere is carried out on the memory device, hydrogen can be effectively blocked outside the peripheral circuit structure in the second wafer, and the adverse effect of the hydrogen on the peripheral circuit structure is reduced, so that the reliability of the second wafer provided with the peripheral circuit structure is improved.
The preparation method will be described in detail with reference to the specific drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 3 to 11, the present embodiment provides a method for manufacturing a memory device having a barrier structure, including the following steps:
as shown in fig. 3 and 4, step S1 is performed to provide a first wafer 10, where the first wafer 10 includes a first wafer bonding surface 101, and the first wafer 10 includes a memory cell array (for easy understanding, the memory cell array is not shown in fig. 4, and refer to fig. 1 and 2), and the memory cell array includes at least one trench pillar.
The first wafer 10 is used to form a memory cell area (Array device) of a memory device, so in addition to a memory cell Array, the first wafer 10 may further include a step region surrounding the memory cell Array, where the step region is used for electrical lead-out of the memory cell Array.
As shown in fig. 3 and 5, step S2 is performed to provide a second wafer 20, where the second wafer 20 includes a second wafer bonding surface 201, and the second wafer includes a CMOS circuit structure (for ease of understanding, the CMOS circuit structure is not shown in fig. 5).
The CMOS circuit structure includes any suitable digital, analog, and/or mixed-signal peripheral circuitry to facilitate memory operations, for example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or active or passive components (e.g., transistors, diodes, resistors, or capacitors) in any circuitry.
It should be noted that there is no sequence between step S1 and step S2, that is, step S1 may be completed first and then step S2 is performed, step S2 may be completed first and then step S1 is performed, or step S1 and step S2 may be performed simultaneously.
As shown in fig. 3 and fig. 6a to 6d, step S3 is performed to embed a hydrogen barrier layer 30 in the first wafer 10 and/or the second wafer 20, wherein the hydrogen barrier layer 30 is formed near the first wafer bonding surface 101 and/or near the second wafer bonding surface 201.
During the subsequent annealing process with hydrogen atmosphere, the hydrogen blocking layer 30 can effectively block the diffusion of the free hydrogen generated during the annealing process from entering the CMOS circuit structure in the second wafer 20, so as to reduce the adverse effect on the CMOS circuit structure, for example, HCI effect, where the free hydrogen forms a gate oxide layer of a transistor in the CMOS circuit structure by hot carrier injection, which generates an interface state and oxide layer trap charges, resulting in damage to the gate oxide layer; free hydrogen is injected into the channel layer of a transistor in the CMOS circuit structure and the surface of the gate oxide layer to form a silicon-hydrogen bond, and the silicon-hydrogen bond is easy to introduce new oxide layer charges under stress to cause NBTI effect. So as long as the hydrogen blocking layer 30 satisfies the characteristics of non-conductivity and compactness, it can have an effect of effectively blocking free hydrogen.
As an example, the material of the hydrogen barrier layer 30 includes aluminum oxide or silicon nitride. The material of the hydrogen barrier layer 30 may be any other non-conductive material as long as the effect of effectively blocking the free hydrogen is satisfied.
As shown in fig. 6a, the hydrogen barrier layer D3 has a thickness between that of
In the meantime. For example, can be
Or
As shown in fig. 6a, 6c, for example, the distance D1 between the hydrogen barrier layer and the first wafer bonding surface is between 0.5 μm and 1 μm and/or the distance D2 between the hydrogen barrier layer and the second wafer bonding surface is between 0.5 μm and 1 μm. For example, it may be 0.7 μm or 0.9. mu.m. It should be noted that D1 between the hydrogen barrier layer and the first wafer bonding surface refers to a distance between a side of the hydrogen barrier layer 30 closest to the first wafer bond 101 and the first wafer bonding surface 101 (as shown in fig. 6 b); the distance D2 between the hydrogen barrier layer and the second wafer bonding surface refers to the distance between the surface of the hydrogen barrier layer 30 closest to the second wafer bonding 201 and the second wafer bonding surface 201 (as shown in fig. 6D).
The hydrogen barrier layer 30 may be formed using various deposition processes known in the art, for example, a furnace process, an atomic layer deposition process (ALD), or a chemical vapor deposition process (CVD). As an example, a furnace tube process may be employed to form the hydrogen barrier layer 30 of an alumina material having a thickness of about 15 nm; the ALD technique may be used to form a hydrogen barrier layer 30 of alumina material having a thickness of about 20nm at 500 ℃; the hydrogen barrier layer 30 of silicon nitride material may also be formed by a CVD process at 700 c and low pressure.
The arrangement of the hydrogen barrier layer 30 in the first wafer 10 and/or the second wafer 20 is not limited, as long as the hydrogen barrier layer 30 is arranged in at least one of the two, and the number of layers arranged in the first wafer 10 and/or the second wafer 20 is not limited. As shown in fig. 6a, the hydrogen barrier layer 30 may be formed only in the first wafer 10; as shown in fig. 6b, two hydrogen barrier layers 30 may be formed only in the first wafer 10; as shown in fig. 6c, the hydrogen barrier layer 30 may be formed only in the second wafer 20; as shown in fig. 6d, two layers of the hydrogen barrier layer 30 may be formed only in the second wafer 20. It is needless to say that the arrangement may be other than the arrangement shown in fig. 6a to 6d, for example, at least one hydrogen barrier layer 30 is formed on both the first wafer 10 and the second wafer 10, and the number of the hydrogen barrier layers 30 formed on the first wafer 10 and the second wafer 10 may be the same or different.
As an example, only the first wafer 10 has one hydrogen barrier layer 30 embedded therein or only the second wafer 20 has one hydrogen barrier layer 30 embedded therein. Since the electrical connection structures (i.e., the subsequent first through array connection portion 102 and the subsequent second through array connection portion 202) need to be formed in the first wafer 10 and the second wafer 20 in the subsequent steps, the electrical connection structures are generally formed by etching through holes (VIA), and the etching of VIA holes has a strong sensitivity to the hole depth, the process of providing a layer of the hydrogen blocking layer 30 on the VIA holes has a small influence, and the isolation effect on the free hydrogen can be achieved.
As shown in fig. 3 and 7, step S4 is performed to form a first through array connection portion 102 and a first through array contact portion 103 connected thereto in the first wafer 10.
As shown in fig. 3 and 8, step S5 is performed to form a second through array connection portion 202 and a second through array contact portion 203 connected thereto in the second wafer 20.
The first through array connection portion 102, the first through array contact portion 103, the second through array connection portion 202 and the second through array contact portion 203 may be formed by conventional processes, and a specific process for manufacturing the same is not described herein.
It should be noted that there is no sequence between step S3 and step S4, that is, step S3 may be completed first and then step S4 is performed, step S4 may be completed first and then step S3 is performed, or step S3 and step S4 may be performed simultaneously.
As shown in fig. 3 and fig. 9a to 9c, step S6 is performed to bond the first wafer 10 and the second wafer 20 through the first wafer bonding surface 101 and the second wafer bonding surface 201, so that the first through array contact 103 and the second through array contact 203 are electrically connected.
Fig. 9a shows a bonding diagram of the hydrogen barrier layer 30 disposed on each of the first wafer 10 and the second wafer 20; as shown in fig. 9b, a bonding diagram of only one layer of the hydrogen barrier layer 30 disposed in the second wafer 20; as shown in fig. 9c, a bonding diagram of only one layer of the hydrogen barrier layer 30 disposed in the first wafer 10 is shown.
As shown in fig. 3 and fig. 10a-10b, step S7 is performed to form a pad extraction layer 40 on a surface of the first wafer 10 away from the first wafer bonding surface 101, where a pad 401 in the pad extraction layer 40 is electrically connected to the first through array connection portion 102.
As shown in fig. 10a, in the case where only one layer of the hydrogen barrier layer 30 is provided in the second wafer 20, a pad extraction layer is formed; as shown in fig. 10b, in the case where only one layer of the hydrogen barrier layer 30 is provided in the first wafer 10, a pad extraction layer is formed.
As shown in fig. 3 and 11, step S7 is performed to perform an annealing process under a hydrogen atmosphere on the structure formed in the above step.
In the annealing process under the hydrogen atmosphere, the hydrogen in a free state may be derived from a hydrogen source provided from the outside, or may be free hydrogen contained in an oxide or a nitride in the pad extraction layer 40. After the annealing process under the hydrogen atmosphere, the channel column in the first wafer can be effectively repaired, and meanwhile, under the action of the hydrogen barrier layer 30, free hydrogen can be effectively prevented from diffusing into the CMOS circuit structure in the first wafer, so that the CMOS circuit structure is effectively protected, and the reliability of the CMOS circuit structure is improved.
The present embodiment also provides a memory device having a barrier structure, which may be prepared by the above-described method, but may not be limited thereto.
As shown in fig. 1 to 12, the memory device having the barrier structure includes:
a first wafer 10, where the first wafer 10 includes a first wafer bonding surface 101, and the first wafer 10 includes a memory cell array, where the memory cell array includes at least one trench pillar;
a second wafer 20, the second wafer 20 including a second wafer bonding surface 201, the second wafer having a CMOS circuit structure formed therein;
the first wafer 10 and the second wafer 20 are bonded and connected through the first wafer bonding surface 101 and the second wafer bonding surface 201;
a hydrogen barrier layer 30 embedded in the first wafer 10 and/or in the second wafer 20, wherein the hydrogen barrier layer 30 is formed near the first wafer bonding face 101 and/or near the second wafer bonding face 201.
As an example, the first wafer 10 further includes a first through array connection portion 102 and a first through array contact portion 103 connected thereto; the second wafer 20 further includes a second through array connection portion 202 and a second through array contact portion 203 connected thereto; the first through array contact 103 is electrically connected to the second through array contact 203; a pad leading-out layer 40 is formed on one surface of the first wafer 10 away from the first wafer bonding surface 101, and a pad 401 in the pad leading-out layer 40 is electrically connected with the first through array connection part 102.
As an example, the distance D1 between the hydrogen barrier layer and the first wafer bonding surface is between 0.5 μm and 1 μm and/or the distance D2 between the hydrogen barrier layer and the second wafer bonding surface is between 0.5 μm and 1 μm.
As an example, the thickness D3 of the hydrogen barrier layer is between
In the meantime.
As an example, the material of the hydrogen barrier layer 30 includes aluminum oxide or silicon nitride.
As an example, only the first wafer 10 has one hydrogen barrier layer 30 embedded therein or only the second wafer 20 has one hydrogen barrier layer 30 embedded therein.
For the working principle of the memory device with the structure, the technical effect that can be achieved, the structural deformation of the memory device, and the like, please refer to the preparation method of the memory device, which is not described herein again.
In summary, according to the memory device with the blocking structure and the manufacturing method thereof provided by the present invention, the hydrogen blocking layer is embedded in the first wafer and/or the second wafer, and when the subsequent annealing process of the hydrogen atmosphere is performed, the hydrogen blocking layer can effectively block diffusion of the free hydrogen generated during the annealing process from entering the peripheral circuit structure in the second wafer, so as to reduce adverse effects on the peripheral circuit structure and improve reliability of the peripheral circuit structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A preparation method of a memory device with a barrier structure is characterized by at least comprising the following steps:
providing a first wafer and a second wafer, wherein the first wafer comprises a first wafer bonding surface, the first wafer comprises a memory cell array, the memory cell array comprises at least one channel column, the second wafer comprises a second wafer bonding surface, and the second wafer comprises peripheral circuits;
embedding a hydrogen barrier layer in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed near the first wafer bonding surface and/or near the second wafer bonding surface;
bonding the first wafer and the second wafer through the first wafer bonding surface and the second wafer bonding surface;
annealing is performed under a hydrogen atmosphere.
2. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: the first wafer further comprises a first through array connecting part and a first through array contact part connected with the first through array connecting part; the second wafer also comprises a second through array connecting part and a second through array contact part connected with the second through array connecting part; when the first wafer and the second wafer are bonded, the first through array contact part is electrically connected with the second through array contact part; and before the annealing step is carried out under the hydrogen atmosphere, a welding pad leading-out layer is formed on one surface of the first wafer, which is far away from the bonding surface of the first wafer, and a welding pad in the welding pad leading-out layer is electrically connected with the first through array connecting part.
3. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: the distance between the hydrogen barrier layer and the bonding surface of the first wafer is 0.5-1 μm and/or the distance between the hydrogen barrier layer and the bonding surface of the second wafer is 0.5-1 μm.
4. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: the thickness of the hydrogen barrier layer is between
In the meantime.
5. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: the material of the hydrogen barrier layer comprises aluminum oxide or silicon nitride.
6. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: at least one hydrogen barrier layer is embedded in the first wafer and/or the second wafer.
7. The method of manufacturing a memory device with a barrier structure according to claim 1, wherein: and forming the hydrogen barrier layer by adopting a furnace tube process, an atomic layer deposition process or a chemical vapor deposition process.
8. Memory device with a barrier structure, characterized in that it comprises at least:
the first wafer comprises a first wafer bonding surface, the first wafer comprises a storage unit array, and the storage unit array comprises at least one channel column;
a second wafer comprising a second wafer bonding surface, the second wafer comprising peripheral circuitry therein;
the first wafer and the second wafer are in bonding connection through the first wafer bonding surface and the second wafer bonding surface;
a hydrogen barrier layer embedded in the first wafer and/or the second wafer, wherein the hydrogen barrier layer is formed proximate to the first wafer bonding face and/or proximate to the second wafer bonding face.
9. The memory device with barrier structures of claim 8, wherein: the first wafer further comprises a first through array connecting part and a first through array contact part connected with the first through array connecting part; the second wafer also comprises a second through array connecting part and a second through array contact part connected with the second through array connecting part; the first through array contact part is electrically connected with the second through array contact part; and a welding pad leading-out layer is formed on one surface of the first wafer, which is far away from the bonding surface of the first wafer, and a welding pad in the welding pad leading-out layer is electrically connected with the first through array connecting part.
10. The memory device with barrier structures of claim 8, wherein: the distance between the hydrogen barrier layer and the bonding surface of the first wafer is 0.5-1 μm and/or the distance between the hydrogen barrier layer and the bonding surface of the second wafer is 0.5-1 μm.
11. The memory device with barrier structures of claim 8, wherein: the thickness of the hydrogen barrier layer is between
In the meantime.
12. The memory device with barrier structures of claim 8, wherein: the material of the hydrogen barrier layer comprises aluminum oxide or silicon nitride.
13. The memory device with barrier structures of claim 8, wherein: at least one hydrogen barrier layer is embedded in the first wafer and/or the second wafer.
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