TWI766796B - semiconductor memory device - Google Patents

Abstract

The embodiment provides a small and high-performance semiconductor memory device. The semiconductor memory device of the embodiment has a plurality of memory cell array layers, the memory cell array layer has a first surface and a second surface opposite to the first surface and does not include a substrate, and includes: a plurality of memory cells, These are arranged in three dimensions in the memory cell array region; and the surface wiring layer is embedded in the first surface or/and the second surface; and the surface wiring layer of each of the above-mentioned memory cell array layers is perpendicular to the above-mentioned first surface. The surface wiring layers are arranged so as to overlap when viewed in the direction of the plane, and the surface wiring layers are bonded to each other, whereby a plurality of the memory cell array layers are laminated.

Description

semiconductor memory device

Embodiments of the present invention relate to semiconductor memory devices.

The present invention proposes a semiconductor memory device with a three-dimensional structure, wherein a laminate of a plurality of electrode layers is laminated on a substrate and an insulating layer to form a memory hole, and a charge accumulation film is interposed in the memory hole. There is a silicon body that becomes a channel. Furthermore, there is proposed a technique of disposing the control circuit of the memory cell array having the 3-dimensional structure directly below or directly above the memory cell array.

However, in this example, the memory density per unit area cannot be sufficiently increased.

The embodiment provides a small and high-performance semiconductor memory device.

According to an embodiment, there is provided a semiconductor memory device having a plurality of memory cell array layers, the memory cell array layer having a first surface and a second surface opposite to the first surface and not including a substrate, and including: a plurality of memory cells, which are arranged in three dimensions in the memory cell array region; and a surface wiring layer, which is embedded in the first surface or/and the second surface; and The surface wiring layers of each of the memory cell array layers are arranged to overlap when viewed from a direction perpendicular to the first surface, and the surface wiring layers are bonded to each other, whereby a plurality of the memory cell array layers are stacked.

Hereinafter, an embodiment will be described with reference to the drawings. In addition, the same code|symbol is attached|subjected to the same element in each drawing.

(first embodiment) FIG. 1 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment. The semiconductor memory device of the first embodiment has the following structure: a peripheral circuit layer 100 including a control circuit for controlling writing, erasing, and reading of data to memory cells, and a first memory cell including a plurality of first memory cells arranged in three dimensions. 1. The memory cell array layer 200 is joined to the stacked layers in an opposite manner, and bonded. Furthermore, it has a structure in which the first memory cell array layer 200 and the second memory cell array layer 300 including a plurality of second memory cells arranged three-dimensionally are joined and laminated so as to face each other, and are bonded together.

First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (lower surface) Sa1 in FIG. 1 and a second surface (upper surface) Sa2 on the opposite side of the first surface, and has a first memory cell array 10a having a three-dimensional structure. FIG. 2 is a schematic perspective view of the semiconductor memory device according to the first embodiment, and is a schematic perspective view of the first memory cell array 10a. In addition, in FIG. 2, illustration of a part of insulating layers, such as an inter-electrode insulating layer, is abbreviate|omitted. 2 is vertically opposite to FIG. 1 , the upper side in FIG. 2 is the first surface side, and the lower side is the second surface side.

In FIG. 2, two directions orthogonal to each other are referred to as the X direction and the Y direction, and the direction orthogonal to these X direction and the Y direction (XY plane) and on which a plurality of electrode layers WL are stacked is referred to as Z. direction (stacking direction).

The first memory cell array 10a includes a first laminate 12a in which the electrode layer WL and the insulating layer 11 are alternately laminated layer by layer. In this 1st laminated body 12a, the some 1st columnar part 13a extended in the Z direction is provided. The first columnar portion 13a is provided in, for example, a columnar shape or an elliptical columnar shape. The plurality of first columnar portions 13a are arranged in a zigzag grid or a square grid, for example, on the XY plane. The electrode layer WL is separated into a plurality of blocks in the Y direction and extends in the X direction.

The electrode layer WL is, for example, a layer containing silicon as a main component. Furthermore, the electrode layer WL contains boron as an impurity for making the silicon layer conductive. In addition, the electrode layer WL may also include metal silicide.

The insulating layer 11 mainly includes silicon and oxygen, for example, and is a silicon oxide film (SiO), a silicon oxynitride film (SiON), a silicon oxide film containing carbon (SiOC), or the like.

The drain side selection gate SGD is provided on the first surface Sa1 side, ie, the upper portion, of the first columnar portion 13a, and the source side selection gate SGS is provided on the second surface Sa2 side, ie, the lower portion. The drain side selective gate SGD is disposed on the uppermost electrode layer WL through the insulating layer 11 . The source-side selective gate SGS is an intervening insulating layer 11 disposed under the lowermost electrode layer WL. Here, for example, the drain side selection gate SGD and the source side selection gate SGS may be formed thicker than the one-layer electrode layer WL.

The first bit line 16a is connected to the upper end portion on the side of the first surface Sa1 of the first columnar portion 13a. A plurality of first bit lines 16a are provided, and metal is used. The plurality of first bit lines 16a are separated in the X direction and extend in the Y direction. The first bit line 16a is disposed on the drain side select gate SGD via the insulating layer 11 and the interlayer insulating layer 14.

The first source line 17a is connected to the lower end portion on the second surface Sa2 side of the first columnar portion 13a. The first source line 17a is provided under the source side selection gate SGS via the interlayer insulating layer 15 . Further, a first source side wiring layer 19a is provided in the interlayer insulating layer 18 at the lower end portion of the first columnar portion 13a and further below the first source line 17a. The interlayer insulating layer 18 may also be a layered layer.

3 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment, and is a schematic cross-sectional view of the vicinity of the first columnar portion. FIG. 4 is a schematic cross-sectional view of part A in the vicinity of the first columnar part in FIG. 3 in an enlarged manner. 3 and 4 show cross sections parallel to the YZ plane of FIG. 2 .

As shown in FIG. 3 , the first columnar portion 13a is formed in an I-shaped memory hole formed in the first laminate 12a including a plurality of electrode layers WL and a plurality of insulating layers 11 . Inside the memory hole, there is a channel body 20 serving as a semiconductor channel. The channel body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than that of the electrode layer WL.

As shown in FIG. 4 , the memory cell MC is provided with a memory membrane 21 between the inner wall of the memory hole and the channel body 20 . The memory film 21 has, for example, a block insulating film 22 , a charge accumulation film 23 , and a tunnel insulating film 24 . Between the electrode layer WL and the channel body 20, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24 are sequentially provided from the electrode layer WL side.

The channel main body 20 is provided in a cylindrical shape extending in the lamination direction of the laminate, and the memory film 21 is extended in the lamination direction of the laminate so as to surround the outer peripheral surface of the channel main body 20 and provided in a cylindrical shape. The electrode layer WL surrounds the periphery of the channel body 20 through the memory film 21 . Moreover, inside the channel main body 20, a core insulating film 25 is provided. The core insulating film 25 is, for example, a silicon oxide film.

The block insulating film 22 is in contact with the electrode layer WL, the tunnel insulating film 24 is in contact with the channel body 20 , and a charge accumulation film 23 is provided between the block insulating film 22 and the tunnel insulating film 24 .

The channel body 20 functions as a channel of the memory cell MC, and the electrode layer WL functions as a control gate of the memory cell. The charge accumulation film 23 functions as a data memory layer that accumulates charges injected from the channel body 20 . That is, at the intersecting portion of the channel body 20 and each electrode layer WL, a memory cell MC that controls the structure in which the gate electrode surrounds the surrounding of the channel is formed.

The semiconductor memory device of the first embodiment is a non-volatile semiconductor memory device that can electrically and freely perform data erasing and writing, and can retain the memory contents even when the power is turned off.

The memory cell MC is, for example, a charge trap type memory cell. The charge accumulating film 23 has a plurality of trapping sites for trapping charges, and is, for example, a silicon nitride film. It can also be a floating gate type memory cell.

The tunnel insulating film 24 becomes a potential energy barrier when charges are injected from the channel body 20 to the charge storage film 23 or when the charges stored in the charge storage film 23 are diffused to the channel body 20 . The tunnel insulating film 24 is, for example, a silicon oxide film.

Alternatively, as the tunnel insulating film, a build-up film (ONO film) having a structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films may be used. If the ONO film is used as the tunnel insulating film, the erasing operation can be performed at a lower electric field than a single layer of a silicon oxide film.

The block insulating film 22 prevents the charges accumulated in the charge accumulation film 23 from diffusing to the electrode layer WL. The block insulating film 22 includes, for example, a silicon nitride film 221 provided in contact with the electrode layer WL, and a silicon oxide film 222 provided between the silicon nitride film 221 and the charge accumulation film 23 .

By arranging the silicon nitride film 221 having a higher dielectric constant than the silicon oxide film 222 in contact with the electrode layer WL, tunnel electrons injected from the electrode layer WL during erasing can be suppressed. That is, by using a laminated film of a silicon oxide film and a silicon nitride film as the block insulating film 35, the charge blocking property can be improved.

As shown in FIGS. 2 and 3 , a drain side selection transistor STD is provided on the upper portion of the first columnar portion 13 a , and a source side selection transistor STS is provided on the other lower portion.

The memory cell MC, the drain side selection transistor STD, and the source side selection transistor STS are vertical transistors through which current flows in the lamination direction (Z direction) of the lamination body.

The drain-side selection gate SGD functions as a gate electrode (control gate) of the drain-side selection transistor STD. Between the drain side selection gate SGD and the channel body 20, an insulating film 26 (FIG. 3) that functions as a gate insulating film of the drain side selection transistor STD is provided. The channel body 20 of the drain side selection transistor STD disposed in the first column portion 13a is above the drain side selection gate SGD, and is connected to the bit line BL.

The source side selection gate SGS functions as a gate electrode (control gate) of the source side selection transistor STS. Between the source side selection gate SGS and the channel body 20, an insulating film 27 (FIG. 3) that functions as a gate insulating film of the source side selection transistor STS is provided. The channel body 20 of the source-side selection transistor STS provided in the first columnar portion 13a is connected to the source line SL below the source-side selection gate SGS.

Further below the source line SL, a first source-side wiring layer 19 a is provided in the interlayer insulating layer 18 .

The plurality of memory cells MC, the drain side selection transistor STD, and the source side selection transistor STS are connected in series through the channel body 20 to form a memory string MS in the shape of an I shape. By arranging a plurality of memory strings MS in the X direction and the Y direction, the plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

FIG. 1 shows the region of the end portion in the X direction of the first memory cell array 10a described above. A stepped structure portion 29 of the electrode layer WL extending in the X direction is formed at the end of the first memory cell array region 28a in which the plurality of memory cells MC are arranged. In the step structure portion 29, the end portion in the X direction of the electrode layer WL of each layer is formed in a step shape. The stepped structure portion 29 is provided with a plurality of contact plugs 30 connected to the electrode layers WL of the respective layers formed in a stepped shape. The contact plug 30 penetrates through the interlayer insulating layer 31 and is connected to the electrode layers WL of the stepped layers.

In addition, in the stepped structure portion 29 , the selection gate SG (the drain side selection gate SGD, the source side selection gate SGS) is connected to the contact plug 32 .

The contact plug 30 connected to the electrode layer WL is connected to the word wiring layer 33 . The contact plug 32 connected to the selection gate SG is connected to the selection gate wiring layer 34 . The word wiring layer 33 and the selection gate wiring layer 34 are provided on the same layer.

The first memory cell array layer 200 does not include a substrate. Moreover, the 1st source side wiring layer 19a is further provided in the 2nd surface side rather than the 1st source line SL.

At least a part of the word wiring layer 33 and the selection gate wiring layer 34 is drawn out from the first line perpendicular to the first line as the word line lead-out portion 35 and the selection gate line lead-out portion 36 through other wiring layers or plugs. The outer side of the first memory cell array region 28a when viewed in the direction of the plane. The word line lead-out portion 35 and the selection gate line lead-out portion 36 led out to the outside of the first cell array region 28a are connected to the first signal line lead-out electrode 37a provided outside the first cell array region 28a.

In addition, the channel body 20 of the first columnar portion 13a is electrically connected to the first bit line BL and the first source line SL. Furthermore, at least a part of the first bit line BL and the first source line SL is similarly used as the first bit line lead-out portion and the first source line lead-out portion through other wiring layers or plugs, and It is drawn out to the outside (not shown) of the first memory cell array region 28a when viewed from the direction perpendicular to the first surface. The first bit line lead-out portion and the first source line lead-out portion led out to the outside of the first memory cell array region 28a are connected to the first signal line lead-out electrode 37a provided outside the first memory cell array region 28a.

A first surface wiring layer 38a and a second surface wiring layer 39a are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200 . The 1st surface wiring layer 38a and the 2nd surface wiring layer 39a are respectively embedded in the 1st surface Sa1 and the 2nd surface Sa2, and the surface is exposed from the interlayer insulating layer which is not shown in figure. Here, for example, the first signal line lead-out electrode 37a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The first signal line lead-out electrode 37 a, the first surface wiring layer 38 a, and the second surface wiring layer 39 a penetrate through the first memory cell array layer 200 .

Moreover, the 1st external connection electrode 40a is provided in the outer side of the 1st memory cell array area|region 28a. That is, the 1st external connection electrode 40a is provided in the area|region outside the step structure part of the memory cell array. The first external connection electrode 40a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. The 1st surface wiring layer 38a and the 2nd surface wiring layer 39a are respectively embedded in the 1st surface Sa1 and the 2nd surface Sa2, and the surface is exposed from the interlayer insulating layer which is not shown in figure. The first external connection electrode 40 a, the first surface wiring layer 38 a, and the second surface wiring layer 39 a penetrate through the first memory cell array layer 200 .

The peripheral circuit layer 100 includes the circuit board 1 . The circuit substrate 1 of the peripheral circuit layer 100 is, for example, a silicon substrate. A control circuit is formed on the circuit formation surface of the circuit board 1 of the peripheral circuit layer. As the control circuit, it is formed as an integrated circuit including transistors. The transistor has a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure including a gate electrode, source/drain regions, and the like. The source/drain regions of the MOSFET are connected to the circuit-side connection electrode 41 through other wiring layers or plugs. The circuit-side connection electrode 41 is electrically connected to the circuit-side wiring layer 42 provided on the circuit formation surface of the peripheral circuit layer 100 . The circuit-side wiring layer 42 is buried in the circuit formation surface, and the surface is exposed from an interlayer insulating layer (not shown).

The second memory cell array layer 300 has the same configuration as the first memory cell array layer 200 shown in FIGS. 1 to 4 . That is, the second memory cell array layer 300 has the third surface (lower surface) Sb1 in FIG. 1 and the fourth surface (upper surface) Sb2 on the opposite side of the third surface, and has the second memory cell array 10b having a three-dimensional structure . In addition, description about the same structure is abbreviate|omitted.

The second memory cell array layer 300 does not include a substrate. Moreover, the 2nd source side wiring layer 19b is further provided in the 4th surface side rather than the 2nd source line SL.

Similar to the first memory cell array layer 200 , at least a part of the word wiring layer 33 and the selection gate wiring layer 34 is used as the word line lead-out portion 35 and the selection gate line lead-out portion through other wiring layers or plugs. 36, and is drawn out to the outside of the second memory cell array region 28b when viewed from a direction perpendicular to the third surface. The word line lead-out portion 35 and the selection gate line lead-out portion 36 led out to the outside of the second cell array region 28b are connected to the second signal line lead-out electrode 37b provided outside the second cell array region 28b.

In addition, the channel body 20 of the second columnar portion 13b is electrically connected to the second bit line BL and the second source line SL. Furthermore, at least a part of the second bit line BL and the second source line SL is drawn out to the second bit line lead-out portion and the second source line lead-out portion through other wiring layers or plugs. The outer side of the second memory cell array region 28b is viewed from a direction perpendicular to the third surface. The second bit line lead-out portion and the second source line lead-out portion led out to the outside of the first memory cell array region 28b are connected to the second signal line lead-out electrode 37b provided outside the second memory cell array region 28b. In addition, since the structure in the 2nd memory cell array area 28b is the same as that of the 1st memory cell array layer 200, description of a code|symbol is abbreviate|omitted.

A third surface wiring layer 38b and a fourth surface wiring layer 39b are provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300 . The third surface wiring layer 38b and the fourth surface wiring layer 39b are buried in the third surface Sb1 and the fourth surface Sb2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). Here, for example, the second signal line lead-out electrode 37b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third and fourth surfaces of the second memory cell array layer 300, respectively. The second signal line lead-out electrode and the third and fourth surface wiring layers penetrate through the second memory cell array layer 300 .

Moreover, the 2nd external connection electrode 40b is provided outside the 2nd memory cell array area|region 28b. That is, the second external connection electrode 40b is provided in a region further outside than the stepped structure portion of the memory cell array. The second external connection electrode 40b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300, respectively. The third surface wiring layer 38b and the fourth surface wiring layer 39b are buried in the third surface Sb1 and the fourth surface Sb2, respectively, and their surfaces are exposed from an interlayer insulating layer (not shown). The second external connection electrode 40 b , the third surface wiring layer 38 b and the fourth surface wiring layer 39 b penetrate through the second memory cell array layer 300 . In the fourth surface wiring layer 39b, an external connection pad 52 is provided on the surface wiring layer electrically connected to the second external connection electrode 40b.

As shown in FIG. 1, the 1st surface wiring layer 38a provided in the 1st surface Sa1 and the circuit side wiring layer 42 provided in the circuit formation surface are adhere|attached and joined. The first surface wiring layer 38a and the circuit-side wiring layer 42 are, for example, copper or a copper alloy mainly composed of copper. An insulating film (not shown) is provided around the first surface wiring layer 38 a and the circuit-side wiring layer 42 . The insulating film is, for example, an inorganic film, a resin film, or the like. The first memory cell array layer 200 and the peripheral circuit layer 100 are electrically connected via the first surface wiring layer 38 a and the circuit-side wiring layer 42 .

Moreover, as shown in FIG. 1, the 2nd surface wiring layer 39a provided in the 2nd surface Sa2, and the 3rd surface wiring layer 38b provided in the 3rd surface Sb1 are bonded and joined. The second surface wiring layer 39a and the third surface wiring layer 38b are, for example, copper or a copper alloy mainly composed of copper. An insulating film (not shown) is provided around the second surface wiring layer 39a provided on the second surface and the third surface wiring layer 38b provided on the third surface Sb1. The insulating film is, for example, an inorganic film and includes a silicon nitride film. The first memory cell array layer and the second memory cell array layer are electrically connected via the second surface wiring layer 39a and the third surface wiring layer 38b.

In addition, when the insulating film around the wiring layer is an inorganic film, the bonding of the wiring layers can be performed on the bonding surface, and the bonding by hydrogen bonding of the inorganic films can be performed. Thereby, when an inorganic film is used as an insulating film, it is preferable in that it is not necessary to perform underfilling using a resin mold, since it is difficult to generate a gap between the bonding surfaces.

5 is a schematic perspective view of the semiconductor memory device according to the first embodiment, and is a schematic perspective view related to the electrical connection state of the peripheral circuit layer, the first memory cell array layer, and the second memory cell array layer.

As shown in FIG. 5 , the peripheral circuit layer 100 , the first memory cell array layer 200 and the second memory cell array layer 300 are connected by a first signal line lead-out electrode, a second signal line lead-out electrode, a first external connection electrode and a second 2 are externally connected to electrodes (not shown) for electrical connection. Signal line lead-out electrodes are arranged on the outside of the memory cell array regions 28a and 28b, and external connection electrodes are arranged on the outside of the memory cell array region and outside the stepped structure portion of the memory cell array. When viewed from the direction perpendicular to the first surface Sa1, the signal line lead-out electrodes and the external connection electrodes of the memory cell array layer are respectively disposed in overlapping regions. The signal line lead-out electrodes are electrically connected to the surface wiring layers 39 a and 39 b , and the external connection electrodes of the second memory cell array layer 300 serving as the uppermost layer are electrically connected to the external connection pads 52 . In addition, in FIG. 5, only a part of the electrical connection state of the 1st signal line extraction electrode, the 2nd signal line extraction electrode, the 1st external connection electrode, the 2nd external connection electrode, etc. is shown, and illustration is abbreviate|omitted.

The manufacturing method of the semiconductor memory device of the first embodiment will be described with reference to FIGS. 6 to 9 . 6 to 9 are cross-sectional views of the semiconductor memory device relating to the manufacturing method of the semiconductor memory device according to the first embodiment.

As shown in FIG. 6, a control circuit including transistors and the like is formed on the circuit board 1, and a peripheral circuit layer 100 having a circuit-side wiring layer 42 whose surface is exposed from an insulating film (not shown) is formed. In addition, a first insulating layer 50, such as a silicon oxide film, is formed under the other substrate 2 as a buffer layer, and a first source line side wiring layer 19a and a first source line 17a are formed under the first insulating layer 50. A first selection gate SG, a plurality of electrode layers WL, and the like are formed under the source line 17a. Next, the memory string MS, the stepped structure portion 29 and the like are formed. Furthermore, the first surface wiring layer 38a whose surface is exposed from the first external connection electrode 40a, the first signal line lead-out electrode 37a, and the insulating film (not shown) is formed, and the first memory cell array layer 200 is formed. Next, the circuit-side wiring layer 42 of the peripheral circuit layer 100 and the first surface wiring layer 38a of the first memory cell array layer 200 are laminated so as to face each other.

Next, as shown in FIG. 7 , the peripheral circuit layer 100 and the first memory cell array layer 200 are laminated. At this time, the circuit-side wiring layer 42 and the first surface wiring layer 38a are joined. As the bonding method, for example, mechanical pressure is applied to bond, and diffusion bonding is performed. Alternatively, the bonding surface is subjected to inert plasma treatment, and the bonding surface is bonded by hydrogen bonding generated by the formation of OH groups on the bonding surface. Alternatively, bonding is performed using an organic adhesive or the like. After that, the substrate 2 is removed with a chemical solution such as KOH, for example. At this time, the insulating films around each wiring layer may be bonded to each other.

It is considered that since the memory cell array layer does not have a substrate, it is easily deformed by the stress applied to the memory cell array layer, resulting in warping of the laminated semiconductor memory device. Therefore, the second insulating layer 51 is formed. The second insulating layer 51 is a layer having a stress in the opposite direction to the bending generated after the substrate is removed, and is formed as a stress adjustment film. As the second insulating layer 51, for example, a silicon nitride film is formed. Thereby, the stress generated in the semiconductor memory device can be alleviated, and the bending of the semiconductor memory device can be suppressed.

Next, the first insulating layer 50 and the second insulating layer 51 are removed so that the upper surfaces of the first external connection electrode 40a and the first signal line lead-out electrode 37a are exposed to form a groove. As shown in FIG. 8, the 2nd surface wiring layer 39a which becomes a bonding metal is formed in this groove|channel, and the upper surface of the 2nd surface wiring layer 39a is exposed.

Next, following FIG. 8 , the peripheral circuit layer 100 shown in FIG. 6 is replaced by a first memory cell array layer 200 , and the first memory cell array layer 200 shown in FIG. 6 is replaced by a second memory cell array layer. 300, repeat the same steps as in FIG. 6 to FIG. 8 . As shown in FIG. 9 , in the fourth surface wiring layer 39b exposed on the upper surface, an external connection pad 52 is formed on the surface wiring layer electrically connected to the second external connection electrode 40b. In this way, a semiconductor memory device in which the peripheral circuit layer 100 , the first memory cell array layer 200 and the second memory cell array layer 300 are stacked can be formed.

In the first embodiment, the second memory cell array layer 300 is laminated on the first memory cell array layer 200 , but one or more other memory cell array layers may be further laminated on the second memory cell array layer 300 . At this time, at least a portion of the one or more other memory cell array layers may also include a substrate. In this case, the warp of the laminated semiconductor memory device can be reduced.

In addition, the peripheral circuit layer 100 may not be laminated, and only the laminated body of the memory cell array layer may be formed.

(1st Variation) 10 is a schematic cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment. A wiring layer 61 connecting the memory strings MS1 of the first memory cell array layer 200 and the memory strings MS2 of the second memory cell array layer 300 is provided. The wiring layer 61 is disposed inside the memory cell array region, and is connected to the first source side wiring layer 19 a of the first memory cell array layer 200 and the second bit line 16 b of the second memory cell array layer 300 . The first memory cell array layer and the second memory cell array layer are not connected via signal line lead-out electrodes provided outside the memory cell array region.

In the first modification example, the first memory cell array layer and the second memory cell array layer are connected with the wiring layer provided on the inner side of the memory cell array area in addition to the signal line lead-out electrodes arranged on the outer side of the memory cell array area. .

By forming in this way, the electrode area required for the connection of the memory cell array layer can be reduced, and the chip area can be reduced.

(Second modification example) 11 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. The description of external connection electrodes is omitted.

At least a part of the word wiring layer and the selection gate wiring layer of the first memory cell array layer 200 is drawn out as the word line lead-out portion 35 and the selection gate line lead-out portion 36 through other wiring layers or plugs, When viewed in the direction perpendicular to the first surface Sa1, it is folded back to the inside of the first memory cell array region 28a. The word line lead-out portion 35 and the select gate line lead-out portion 36 led out to the inner side of the first memory cell array region 28a are connected to the first signal line lead-out electrode 37a provided inside the first memory cell array region 28a.

Also, at least a part of the first bit line BL and the first source line SL is similarly drawn out as the first bit line lead-out portion and the first source line lead-out portion through other wiring layers or plugs, When viewed from the direction perpendicular to the first surface Sa1, it is folded back to the inside of the first memory cell array region 28a (not shown). The first bit line lead-out portion and the first source line lead-out portion led out to the inner side of the first memory cell array region 28a are connected to the first signal line lead-out electrode 37a provided inside the first memory cell array region 28a.

In addition, the first source-side wiring layer 19a on the side of the second surface Sa2 is connected to the first signal line lead-out electrode 37a provided inside the first memory cell array region 28a. Here, a part of the first signal line lead-out electrode 37a may also be disposed outside the first memory cell array region 28a.

The first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200 are respectively provided with a first surface wiring layer 38a and a second surface wiring layer 39a inside the memory cell array region. The first surface wiring layer 38a and the second surface wiring layer 39a provided on the inner side of the memory cell array region are electrically connected to the first signal line lead-out electrodes 37a.

Similar to the first memory cell array layer 200, the second memory cell array layer 300 has at least a part of the word wiring layer and the selection gate wiring layer used as the word line lead-out portion 35 and the selection gate via other wiring layers or plugs. The gate line lead-out portion 36 is led out, and is folded back to the inside of the second memory cell array region 28b when viewed from a direction perpendicular to the third surface Sb1. The word line lead-out portion 35 and the selection gate line lead-out portion 36 led out to the inner side of the second memory cell array region 28b are connected to the second signal line lead-out electrode 37b provided inside the second memory cell array region 28b.

In addition, at least a part of the second bit line BL and the second source line SL is drawn out as a second bit line lead-out portion and a second source line lead-out portion through other wiring layers or plugs, and is perpendicular to the When viewed from the direction of the third surface, it is folded back to the inside of the second memory cell array region 28b (not shown). The second bit line lead-out portion and the second source line lead-out portion led out to the inner side of the second memory cell array region 28b are connected to the second signal line lead-out electrode 37b provided inside the second memory cell array region 28b. Here, a part of the second signal line lead-out electrode 37b may also be disposed outside the second memory cell array region 28b.

On the third surface Sb1 of the second memory cell array layer 300, a third surface wiring layer 38b is provided inside the memory cell array region. The third surface wiring layer 38 disposed inside the memory cell array region is electrically connected to the second signal line lead-out electrode 37b. Here, on the fourth surface Sb2 of the second memory cell array layer 300, a fourth surface wiring layer (not shown) may also be provided inside the memory cell array region. In this case, the fourth surface wiring layer disposed inside the memory cell array region is electrically connected to the second signal line lead-out electrode 37b.

Therefore, the signal line lead-out electrodes of each memory cell array layer are connected to the surface wiring layer disposed inside the memory cell array region. When viewed from the direction perpendicular to the first surface, the surface wiring layers of each memory cell array layer can be respectively arranged in overlapping areas. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

According to the second modification, at least a part of the bit line, word line, etc. is folded back to the inside of the memory cell array region. The signal line lead-out electrodes connected through the bit line lead-out portion and the word line lead-out portion are arranged inside the memory cell array region. In addition, the signal line lead-out electrodes of each memory cell array layer are connected to the surface wiring layer disposed on the inner side of the memory cell array region. When viewed from the direction perpendicular to the first surface, the surface wiring layers of each memory cell array layer can be respectively set. in overlapping areas. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

According to the first embodiment, the first memory cell array layer 200 and the second memory cell array layer 300 do not have a substrate (eg, a silicon substrate). Therefore, when the first memory cell array layer 200 and the second memory cell array layer 300 are laminated and electrically connected, they can be connected without forming a TSV (Through Silicon Via). Thereby, it is not necessary to perform an etching step of the substrate, which is expensive or processing time, or to form an insulating film for preventing a short circuit between the substrate and the through hole, thereby reducing the cost and increasing the throughput.

In addition, since the memory cell array layer and the peripheral circuit layer are formed by different wafer processes, when a high temperature heat treatment is required for the formation of the memory cell array layer, impurity diffusion of the transistors in the peripheral circuit layer or metal ionization can be suppressed. Deterioration of wiring layers and other adverse effects.

In addition, the memory cell array layer is laminated so that the first surface faces the peripheral circuit layer. The bit line or word line is drawn out to the first surface side of the memory cell array layer, and the bit line or word line is connected to the signal line lead-out electrode. Since the memory cell array layer is laminated so that the first surface and the peripheral circuit layer face each other, the wiring distance of the electrode layer can be reduced, and the adverse effect on the operation speed can be suppressed.

Furthermore, according to the first embodiment, a plurality of memory cell array layers are laminated on the peripheral circuit layer. In this way, when the laminate of one memory cell array layer is 48 layers, for example, by laminating two memory cell array layers and using the 48-layer process technology, the memory of 96 layers, which is twice the 48 layers, can be realized. cell array. Therefore, the memory density can be easily increased.

Furthermore, at least a part of the bit lines or word lines, etc. are led out to the outside of the memory cell array area, and the signal line lead-out electrodes connected through the bit line lead-out portion and the word line lead-out portion are arranged on the outside of the memory cell array area. outside. In addition, on the outside of the memory cell array region, and the region outside the stepped structure portion of the memory cell array, an external connection electrode is provided. When viewed from the direction perpendicular to the first surface, the signal line lead-out electrodes and the external connection electrodes of each memory cell array layer are respectively disposed in overlapping regions. Thereby, when a plurality of memory cell array layers are laminated, the wiring length can be suppressed, and the operation delay can be suppressed.

Alternatively, at least a part of the bit line or word line is folded back to the inner side of the memory cell array area. The signal line lead-out electrodes connected through the bit line lead-out portion and the word line lead-out portion are arranged inside the memory cell array region. In addition, the signal line lead-out electrodes of each memory cell array layer are connected to the surface wiring layer disposed on the inner side of the memory cell array region, and the surface wiring layers of each memory array layer are respectively disposed in the direction perpendicular to the first surface when viewed from the direction perpendicular to the first surface. overlapping area. Thereby, when a plurality of memory cell array layers are laminated, the chip area can be further reduced, the wiring length can be suppressed, and the operation delay can be suppressed.

In addition, the external connection electrodes and the surface wiring layers connected to the external connection electrodes pass through at least the upper and lower layers (here, the first memory cell array layer) sandwiched by the memory cell array layer or/and the peripheral circuit layer. set up. In addition, the signal line lead-out electrode and the surface wiring layer connected to the signal line lead-out electrode pass through at least the upper and lower layers sandwiched by the memory cell array layer or/and the peripheral circuit layer (here, the first memory cell array layer). way to set. Therefore, when a plurality of memory cell array layers are laminated, the wiring length can be further suppressed, the operation delay can be further suppressed, and the reliability can be improved.

Furthermore, the external connection electrodes can be arranged such that they are not connected to the memory cells, and external signals can be input to the peripheral circuit layer from the external connection pads without going through the memory cells. Thereby, adverse effects such as operation delay can be further suppressed. In addition, since the signal line lead-out electrodes are electrically connected to each memory cell array layer even in the path not connected to the memory cells, the signal lines of each layer are connected without going through the memory cells. Thereby, adverse effects such as operation delay can be further suppressed.

In addition, the memory cell array layer does not have a substrate, and there is no need to form through-silicon electrodes such as TSVs. Instead of providing the substrate, a source side wiring layer is provided on the second surface side (fourth surface side) of the memory cell array layer. Thereby, the stacked memory cell array layers can be connected arbitrarily, and the wiring area can be increased without increasing the chip area.

Furthermore, the first source-side wiring layer can be used as the first source lead-out portion of the first source line SL. The second source side wiring layer can be used as the second source line lead-out portion of the second source line SL. In this way, in the memory cell array having the memory cell string in which the columnar portion is in the shape of an I, by providing the source side wiring layer on the second surface side (the fourth surface side) of the source line, it is possible to effectively suppress the source electrode The wiring length from the line to the signal line lead-out electrode.

In addition, the signal line lead-out electrodes and the surface wiring layer of the second memory cell array layer may be formed so as to penetrate through the second memory cell array layer similarly to the first memory cell array layer. In this case, the device structure of the first memory cell array layer and the second memory cell array layer can be commonized, and the characteristics such as stress generated by the memory cell array layer can be made uniform. In addition, it is preferable that the process of the first memory cell array layer and the second memory cell array layer can be commonized, and the memory cell array layer can be efficiently produced.

Further, in the first memory cell array layer or the second memory cell array layer, the bit line or the word line is drawn out to the first surface side or the third surface side, and the bit line or the word line is connected to the signal line Extract the electrode. The first memory cell array layer is stacked so that the first surface faces the peripheral circuit layer, and the second memory cell array layer is stacked so that the third surface faces the first memory cell array layer. That is, the first memory cell array layer and the second memory cell array layer lead out signal lines in the same direction, and are stacked so that the orientations of the first memory cell array layer and the second memory cell array layer are the same. In this way, since the bit line or word line is drawn out to the side where the peripheral circuit layer is provided (the lower side in FIG. 1 ) and is laminated on the peripheral circuit layer, the wiring distance of the electrode layer can be reduced, and the counter-action can be suppressed. adverse effects of speed.

In addition, assuming that the orientations of the first memory cell array layer and the second memory cell array layer are not aligned to face the laminate, for example, a memory cell array layer must be arranged on a tape, etc., after removing the substrate from the tape, Laminate in such a way that the surface after the substrate is removed faces the peripheral circuit or another memory cell array layer. If the orientation of the first memory cell array layer and the second memory cell array layer are aligned and stacked, there is no need to use a tape or the like. That is, it can be formed by laminating the memory cell array layer formed on the substrate directly on the peripheral circuit layer with the substrate surface on top, and removing the substrate. Thereby, it is also preferable that the memory cell array layer and the second memory cell array layer are laminated so that the orientations of the memory cell array layer and the second memory cell array layer are aligned, and that they can be easily formed without using for a tape or the like.

(Second Embodiment) Next, the semiconductor memory device of the second embodiment will be described. In addition, since the basic structure is the same as that of the first embodiment, the description of the matters described in the first embodiment is omitted.

FIG. 12 is a schematic cross-sectional view of the semiconductor memory device of the second embodiment. In FIG. 12, for the semiconductor memory device of FIG. 1, one memory cell array layer is further laminated, and the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer are sequentially provided from the bottom. 300. The third memory cell array layer 400.

Here, as shown in FIG. 12 , the second memory cell array layer 300 is laminated between the third surface wiring layer 38b provided on the third surface Sb1 and the fourth surface wiring layer 39b provided on the fourth surface Sb2 , and a wiring layer 71 connected to the memory string MS3 is provided. That is, the second memory cell array layer 300 is connected to the upper and lower memory cell array layers via the memory string MS3 and the wiring layer 71 .

FIG. 13 is a circuit diagram of the semiconductor memory device of the second embodiment. In FIG. 13, a portion of the circuit of the memory string MS3 connected to the wiring layer 71 is shown. There are plural memory cells, and some illustrations are omitted. A drain side selection transistor STD and a source side selection transistor STS are arranged in the plurality of memory cells, and the ID of the array layer disposed in each memory cell array layer is stored. The circuit of the memory string MS3 functions as part of the selection circuit of the array layer which selects the array layer.

FIG. 14 is a block diagram showing the system configuration of the semiconductor memory device of the second embodiment. In FIG. 14, the structure of the system of the semiconductor memory device including the array layer selection circuit provided in the memory string MS3 connected to the wiring layer 71 is shown.

In each memory cell array layer, the input address line and the array layer selection signal line are used as the signal line. In the memory cell array layer, by selecting the signal line and the ID of the array layer to be memorized by the array layer, it is judged whether to select the memory cell array layer, and the address line is input to the memory cell array.

By forming in this way, it is possible to select the memory cell array layer by using the transistors and memory cells in the memory string MS3 instead of using each signal line individually to select the memory cell array layer, even if it is a semiconductor having a plurality of stacked memory cell array layers. The memory device can also greatly reduce the number of wires.

In addition, in this case, for each of the memory regions or memory blocks of the second memory cell array layer, the wiring layers 71 may be used to connect the upper and lower memory cell array layers respectively. By forming in this way, each transistor and each memory cell in each memory string MS can be used to select a memory region or a memory block, and even a semiconductor memory device having a plurality of stacked memory cell array layers can be used. Significantly reduces the number of wires.

The above has described the embodiment with reference to the drawings. However, the present invention is not limited to this.

In the present invention, the case where the circuit board is included is described, but the case where only the memory cell array layer is laminated is also included in the scope of the present invention.

Those skilled in the art who have made various design changes regarding the configuration of the memory cell array constituting the present invention are also included in the scope of the present invention as long as they do not depart from the gist of the present invention.

Furthermore, according to yet another aspect, there is provided a semiconductor memory device characterized by having a three-dimensional memory cell array having another configuration.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the invention described in the scope of the patent application and its equivalents.

1: Circuit board 2: Substrate 10a: 1st memory cell array 10b: 2nd memory cell array 11: Insulation layer 12a: 1st layered body 13a: 1st columnar part 13b: Second columnar part 14: Interlayer insulating film 15: Interlayer insulating film 16a: 1st bit line 16b: 2nd bit line 17a: 1st source line 18: Interlayer insulating film 19a: First source side wiring layer 19b: Second source side wiring layer 20: Channel body 21: Memory film 22: Block insulating film 23: Charge accumulation film 24: Tunnel insulating film 25: Core insulating film 26: Insulating film 27: Insulating film 28a: first memory cell array area 28b: 2nd memory cell array area 29: Step structure part 30: Contact plug 31: Interlayer insulating layer 32: Contact plug 33: Character wiring layer 34: Select gate wiring layer 35: Word line lead-out 36: Select gate line lead-out 37a: 1st signal line lead-out electrode 37b: 2nd signal line lead-out electrode 38a: 1st surface wiring layer 38b: 3rd surface wiring layer 39a: Second surface wiring layer 39b: 4th surface wiring layer 40a: 1st external connection electrode 40b: Second external connection electrode 41: Connecting electrodes on the circuit side 42: Circuit side wiring layer 50: 1st insulating layer 51: 2nd insulating layer 52: External connection pad 61: wiring layer 71: wiring layer 100: Peripheral circuit layer 200: 1st memory cell array layer 221: silicon nitride film 222: Silicon oxide film 300: 2nd memory cell array layer 400: The third memory cell array layer A: Part BL: bit line MC: memory cell MS: memory string MS1: memory string MS2: memory string MS3: Memory String Sa1: side 1 Sa2: side 2 Sb1: side 3 Sb2: Side 4 SG: select gate SGD: drain side select gate SGS: Source Side Select Gate SL: source line STD: Drain Side Select Transistor STS: Source Side Select Transistor WL: electrode layer X: direction Y: direction Z: direction

FIG. 1 is a schematic cross-sectional view showing the semiconductor memory device of the first embodiment. FIG. 2 is a schematic perspective view showing the semiconductor memory device of the first embodiment. FIG. 3 is a schematic cross-sectional view showing the semiconductor memory device of the first embodiment. FIG. 4 is a schematic cross-sectional view of a part of the semiconductor memory device of the first embodiment enlarged. FIG. 5 is a schematic perspective view showing the semiconductor memory device of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a method of manufacturing the semiconductor memory device of the first embodiment. FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the semiconductor memory device of the first embodiment. FIG. 8 is a schematic cross-sectional view showing a method of manufacturing the semiconductor memory device of the first embodiment. 9 is a schematic cross-sectional view showing a method of manufacturing the semiconductor memory device of the first embodiment. 10 is a schematic cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment. 11 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. FIG. 12 is a schematic cross-sectional view showing the semiconductor memory device of the second embodiment. FIG. 13 is a circuit diagram of the semiconductor memory device of the second embodiment. FIG. 14 is a block diagram showing the system configuration of the semiconductor memory device of the second embodiment.

1: Circuit board

10a: 1st memory cell array

10b: 2nd memory cell array

19a: First source side wiring layer

19b: Second source side wiring layer

28a: first memory cell array area

28b: 2nd memory cell array area

29: Step structure part

30: Contact plug

31: Interlayer insulating layer

32: Contact plug

33: Character wiring layer

34: Select gate wiring layer

35: Word line lead-out

36: Select gate line lead-out

37a: 1st signal line lead-out electrode

37b: 2nd signal line lead-out electrode

38a: 1st surface wiring layer

38b: 3rd surface wiring layer

39a: Second surface wiring layer

39b: 4th surface wiring layer

40a: 1st external connection electrode

40b: Second external connection electrode

41: Connecting electrodes on the circuit side

42: Circuit side wiring layer

52: External connection pad

100: Peripheral circuit layer

200: 1st memory cell array layer

300: 2nd memory cell array layer

BL: bit line

Sa1: side 1

Sa2: side 2

Sb1: side 3

Sb2: Side 4

SG: select gate

SL: source line

WL: electrode layer

X: direction

Z: direction

Claims (8)

A semiconductor memory device comprising: a peripheral circuit layer, comprising: a substrate; a peripheral circuit arranged in contact with the upper part of the substrate; and a first bonding metal located above the peripheral circuit and arranged on a bonding surface facing the memory cell array layer; a memory cell array layer, which is attached to the above-mentioned peripheral circuit layer; and an external connection pad, which is electrically connected to the above-mentioned peripheral circuit; and The above-mentioned memory cell array layer includes: A laminated body, wherein electrode layers and insulating layers are alternately laminated in the first direction with a plurality of layers; a columnar portion extending in the first direction in the laminate, and having a memory cell formed in a portion intersecting with the electrode layer; a first wiring layer provided between the bonding surface and the laminate; a first plug connecting the first wiring layer and the external connection pads and extending in the first direction; a second bonding metal disposed on the first bonding metal and electrically connected to the first wiring layer; and a second plug connecting the second bonding metal and the first wiring layer and extending in the first direction; and The first plug does not overlap with the second plug when viewed from the first direction. The semiconductor memory device of claim 1, wherein the first bonding metal and the second bonding metal are directly bonded. The semiconductor memory device of claim 1, wherein the memory cell array layer has a first surface adjacent to the bonding surface and a second surface opposite to the first surface, and does not include a substrate; and The above-mentioned semiconductor memory device further includes: a second wiring layer provided between the second surface and the laminate; a third bonding metal provided on the second surface, overlapped with the laminate when viewed from the first direction, and electrically connected to the second wiring layer; and The signal line lead-out electrode is electrically connected to the first wiring layer and the second wiring layer, and extends in the first direction. The semiconductor memory device of claim 3, wherein a bit line is electrically connected to the first surface side of the columnar portion, a source line is electrically connected to the second surface side of the columnar portion, and a relatively The source line is further provided with the second wiring layer on the second surface side. The semiconductor memory device of claim 3 or 4, further comprising at least one other memory cell array layer of the same type as the above-mentioned memory cell array layer laminated in a manner opposite to the above-mentioned memory cell array layer, and having two or more layers a plurality of memory cell array layers. The semiconductor memory device of claim 5, wherein at least one of the plurality of memory cell array layers is provided with a memory string as a part of the array layer selection circuit, and the memory string has a circuit for selecting the memory cell array layer. The memory cell of the ID of the crystal and memory array layers. The semiconductor memory device of claim 6, wherein the plurality of memory cell array layers are memory cell array layers of at least three layers, and a part of the array layer selection circuit is provided in the plurality of the memory cell array layers and is replaced by other memory cells. A memory cell array layer sandwiched between the upper and lower array layers. The semiconductor memory device of claim 6, wherein a part of the array layer selection circuit is disposed in each memory region or memory block of the at least one memory cell array layer.

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