TWI778143B - semiconductor memory device - Google Patents

semiconductor memory device Download PDF

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TWI778143B
TWI778143B TW107134997A TW107134997A TWI778143B TW I778143 B TWI778143 B TW I778143B TW 107134997 A TW107134997 A TW 107134997A TW 107134997 A TW107134997 A TW 107134997A TW I778143 B TWI778143 B TW I778143B
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memory device
semiconductor memory
contact
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TW107134997A
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TW201904023A (en
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內海哲章
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日商鎧俠股份有限公司
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本發明之實施形態提供配線之佈局容易之半導體記憶裝置。 實施形態之半導體記憶裝置包括:半導體基板;複數個電晶體,其形成於上述半導體基板之上表面,沿著第1方向排列,且最小週期為第1週期;積層體,設置於上述半導體基板上且具有複數片電極膜;第1觸點,其下端連接於上述電極膜;及第2觸點,其貫通上述積層體,且下端連接於上述電晶體之源極、汲極之一者。上述積層體之第1部分之形狀係於每個上述電極膜形成有階面之階梯狀。於上述第1部分,沿著上述第1方向設定有第1區域及第2區域。配置於上述第2區域之上述階面之上述第1方向上之長度較上述第1週期更長。配置於上述第1區域之上述階面之上述第1方向上之長度較上述第1週期更短。Embodiments of the present invention provide a semiconductor memory device with an easy wiring layout. The semiconductor memory device according to the embodiment includes: a semiconductor substrate; a plurality of transistors formed on the upper surface of the semiconductor substrate, arranged along a first direction, and having a minimum period of the first period; a laminate provided on the semiconductor substrate and has a plurality of electrode films; a first contact whose lower end is connected to the electrode film; and a second contact that penetrates through the laminate and whose lower end is connected to one of the source and drain of the transistor. The shape of the 1st part of the said laminated body is a step shape in which a step surface is formed in each said electrode film. In the said 1st part, the 1st area|region and the 2nd area|region are set along the said 1st direction. The length in the first direction of the step surface arranged in the second region is longer than the first period. The length in the first direction of the step surface arranged in the first region is shorter than the first period.

Description

半導體記憶裝置semiconductor memory device

實施形態係關於一種半導體記憶裝置。The embodiment relates to a semiconductor memory device.

近年來,提出將記憶單元三維地集成而成之積層型半導體記憶裝置。此種積層型半導體記憶裝置中,於半導體基板上設置有電極膜與絕緣膜交替地積層而成之積層體,且設置有貫通積層體之半導體柱。由此,於電極膜與半導體柱之每個交叉部分形成有記憶單元電晶體。另一方面,於積層體之周邊設置有對是否向電極膜供給電位進行切換之電晶體。積層體之端部被加工成階梯狀,觸點連接於各電極膜,該觸點經由上層配線而連接於電晶體。此種半導體記憶裝置中,若電極膜之積層數增加,則上層配線之條數增加,從而佈局之製作將變得困難。In recent years, a multilayer semiconductor memory device in which memory cells are three-dimensionally integrated has been proposed. In such a build-up type semiconductor memory device, a laminate in which electrode films and insulating films are alternately laminated is provided on a semiconductor substrate, and a semiconductor pillar penetrating the laminate is provided. Thereby, a memory cell transistor is formed at each intersection of the electrode film and the semiconductor column. On the other hand, a transistor for switching whether or not to supply a potential to the electrode film is provided around the laminate. The end portion of the laminated body is processed into a stepped shape, and the contact is connected to each electrode film, and the contact is connected to the transistor through the upper layer wiring. In such a semiconductor memory device, if the number of layers of the electrode films is increased, the number of upper layer wirings is increased, and it becomes difficult to fabricate the layout.

實施形態提供一種配線之佈局容易之半導體記憶裝置。 實施形態之半導體記憶裝置包括:半導體基板;複數個電晶體,其形成於上述半導體基板之上表面,沿著與上述上表面平行之第1方向排列,上述排列之最小週期為第1週期;積層體,其設置於上述半導體基板上;第1觸點;第2觸點;及第1配線,其連接於上述第1觸點與上述第2觸點之間。上述積層體包括:複數片電極膜,其沿著上下方向相互隔開而積層;半導體構件,其於上述電晶體之除正上方區域外之區域貫通上述複數片電極膜;及電荷累積構件,其設置於上述半導體構件與上述複數片電極膜之一片之間。上述積層體中之配置於上述電晶體之正上方區域之第1部分之形狀係於每個上述電極膜形成有階面之階梯狀。於上述第1部分,沿著上述第1方向設定有兩個第1區域及配置於上述兩個第1區域間之第2區域。於各上述第1區域配置有複數個上述階面。於上述第2區域配置有一個上述階面。配置於上述第2區域之上述階面之上述第1方向上之長度較上述第1週期更長。配置於上述第1區域之上述階面之上述第1方向上之長度較上述第1週期更短。上述第1觸點之下端於上述階面連接於上述複數片電極膜之一片。上述第2觸點貫通上述積層體,下端連接於上述電晶體之源極、汲極之一者。Embodiments provide a semiconductor memory device with easy wiring layout. The semiconductor memory device of the embodiment includes: a semiconductor substrate; a plurality of transistors formed on the upper surface of the semiconductor substrate and arranged along a first direction parallel to the upper surface, and the minimum period of the arrangement is the first period; A body provided on the semiconductor substrate; a first contact; a second contact; and a first wiring connected between the first contact and the second contact. The above-mentioned laminated body includes: a plurality of electrode films, which are spaced apart from each other and laminated along an up-down direction; a semiconductor member that penetrates the plurality of electrode films in a region other than a region directly above the transistor; and a charge accumulating member, which It is provided between the semiconductor member and one of the plurality of electrode films. The shape of the 1st part arrange|positioned in the area|region just above the said transistor in the said laminated body is a step shape in which the step surface is formed in each said electrode film. In the said 1st part, two 1st area|regions and the 2nd area arrange|positioned between the said two 1st area|regions are set along the said 1st direction. A plurality of the above-mentioned stepped surfaces are arranged in each of the above-mentioned first regions. One of the above-mentioned steps is arranged in the above-mentioned second region. The length in the first direction of the step surface arranged in the second region is longer than the first period. The length in the first direction of the step surface arranged in the first region is shorter than the first period. The lower end of the first contact is connected to one of the plurality of electrode films at the step surface. The second contact penetrates through the laminate, and the lower end is connected to one of the source and the drain of the transistor.

(第1實施形態) 首先,對第1實施形態進行說明。 圖1係表示本實施形態之半導體記憶裝置之剖視圖。 圖2係表示本實施形態之半導體記憶裝置之配線部之俯視圖。 圖3係表示本實施形態之半導體記憶裝置之基板面之俯視圖。 圖4係表示圖1之區域A之局部放大剖視圖。 本實施形態之半導體記憶裝置例如為非揮發性半導體記憶裝置,例如為積層型NAND快閃記憶體。 如圖1~圖3所示,本實施形態之半導體記憶裝置1中設置有半導體基板10。以下,本說明書中,為了方便說明而採用XYZ正交座標系。將與半導體基板10之上表面10a平行且相互正交之2個方向設為「X方向」及「Y方向」,將與半導體基板10之上表面垂直之方向設為「Z方向」。又,將Z方向中之從半導體基板10朝向後述之積層體30之方向稱作「上」,將其相反方向稱作「下」,但該表述係方便說明,與重力之方向無關。 半導體基板10例如由矽之單晶形成。於半導體基板10之上層部分之一部分形成有例如p型阱21。於阱21之上層部分之一部分呈格子狀設置有STI(Shallow Trench Isolation,淺溝槽隔離)26,將阱21之上層部分劃分為複數個主體區域21a。主體區域21a沿著X方向及Y方向排列成矩陣狀。於各主體區域21a之上表面,即,半導體基板10之上表面10a中之由STI26包圍之區域,設置有場效型電晶體20。於各主體區域21a之Y方向兩端部之上部,相互隔開而形成有n型擴散區域22及23。擴散區域22及23係電晶體20之源極、汲極區域。又,阱21上設置有閘極絕緣膜24,閘極絕緣膜24上設置有閘極電極25。 X方向上之電晶體20之排列週期大致固定。更詳細而言,於半導體基板10之上表面10a中之特定之區域內設置有複數個電晶體20,該區域內,X方向上之電晶體20之排列週期為固定。本說明書中,將該排列週期稱作「最小排列週期」。本實施形態中,該區域僅示出一個,有時亦如後述第9實施形態般,設置有複數個。該情形時,相鄰之區域間之距離大於由最小排列週期決定之電晶體20間之間隔。 於半導體基板10上且電晶體20上,自下向上設置有觸點27、下層配線28及源極線29。再者,下層配線28設置有多層,亦可經由穿孔觸點(via contact)而相互連接。觸點27之下端連接於擴散區域22,上端連接於下層配線28。源極線29設置於下層配線28上,其形狀為沿著XY平面擴展之板狀。 於源極線29上設置有積層體30。於積層體30中,絕緣膜31及電極膜32沿著Z方向交替地積層。絕緣膜31例如由矽氧化物(SiO)等絕緣性材料形成,電極膜32例如由導入了鎢(W)或雜質之多晶矽(Si)等導電性材料形成。電晶體20係用以驅動電極膜32之電晶體。於半導體記憶裝置1中,除設置電晶體20外,例如亦可設置有構成周邊電路(未圖示)之電晶體。 如圖2所示,電極膜32被分割為沿著Y方向排列之複數個帶狀部分。各帶狀部分沿X方向延伸。本實施形態中,最下層之電極膜32之帶狀部分作為源極側選擇閘極SGS發揮功能,最上層之電極膜32之帶狀部分作為汲極側選擇閘極SGD發揮功能,除此以外之電極膜32之帶狀部分作為字元線WL發揮功能。再者,自最下層算起之多層電極膜32之帶狀部分可作為源極側選擇閘極SGS發揮功能,自最上層算起之多層電極膜32之帶狀部分亦可作為汲極側選擇閘極SGD發揮功能。Y方向上之汲極側選擇閘極SGD之排列週期為源極側選擇閘極SGS及字元線WL之排列週期之一半。即,於1條字元線WL之正上方區域配置有2根汲極側選擇閘極SGD。再者,亦可於1條字元線WL之正下方區域,配置有1根或3根以上之汲極側選擇閘極SGD。 積層體30之X方向之端部30a之形狀係於每個電極膜32形成有階面之階梯狀。階面係電極膜32之X方向之端部之上表面。於階面之正上方區域,未配置更上層之電極膜32。端部30a配置於電晶體20之正上方區域。另一方面,積層體30中之X方向之中央部30b未配置於電晶體20之正上方區域。 端部30a之上表面沿著自積層體30中之X方向中央部30b朝向端部30a之方向,中途不上升而階段性地下降。然而,其下降方式並非週期性。具體而言,於端部30a,沿著X方向交替地配置有區域R1及區域R2。區域R1中,寬度窄之複數個階面33a沿著X方向排列。另一方面,區域R2中,配置有寬度較寬之一個階面33b。X方向上之階面33b之長度L2較階面33a之長度L1長。又,X方向上,階面33a之長度L1較電晶體20之最小排列週期P短,階面33b之長度L2較電晶體20之最小排列週期P長。即,L1<P<L2。 於半導體基板10上,以覆蓋積層體30之方式設置有層間絕緣膜40。於層間絕緣膜40內設置有複數個觸點41及複數個觸點42。於各觸點41之上端與各觸點42之上端之間連接有上層字元線43。上層字元線43配置於層間絕緣膜40內之較積層體30靠上方處。 觸點41沿Z方向延伸,觸點41之下端於階面33a或階面33b連接於電極膜32。因此,電極膜32中之階面33a位於區域R1內之電極膜32連接於位於區域R1內之觸點41。另一方面,階面33b位於區域R2內之電極膜32連接於位於區域R2內之觸點41。因此,觸點41配置於區域R1及區域R2之雙方。 觸點42配置於區域R2內。觸點42沿Z方向延伸,貫通積層體30之端部30a及源極線29。觸點42之下端連接於下層配線28。於觸點42之周圍設置有絕緣膜44。觸點42利用絕緣膜44而與電極膜32及源極線29絕緣。 如此,各電極膜32經由觸點41、上層字元線43、觸點42、下層配線28及觸點27而連接於電晶體20之擴散區域22。又,階面33a位於區域R1內之電極膜32經由區域R1內之觸點41及區域R2內之觸點42而連接於擴散區域22。階面33b位於區域R2內之電極膜32經由區域R2內之觸點41及區域R2內之觸點42而連接於擴散區域22。 另一方面,於積層體30之中央部30b內設置有沿Z方向延伸之矽柱50。矽柱50例如由多晶矽構成,其形狀為下端閉合之圓筒形。矽柱50之下端連接於源極線29。矽柱50之上端經由穿孔觸點46連接於位元線47。位元線47配置於積層體30之中央部30b上,且沿Y方向延伸。 如圖4所示,矽柱50內設置有例如由矽氧化物構成之芯構件51。再者,亦可不設置芯構件51。於矽柱50之側面上設置有穿隧絕緣膜52。穿隧絕緣膜52係通常為絕緣性、但若被施加半導體記憶裝置1之驅動電壓之範圍內之特定電壓則流通穿隧電流之膜。穿隧絕緣膜52例如由單層之矽層構成,或由氧化矽層、氮化矽層及氧化矽層依次積層而成之ONO膜構成。 於穿隧絕緣膜52之表面上設置有電荷累積膜53。電荷累積膜53係具有累積電荷之能力之膜,例如由具有電子之陷阱(trap site)之材料形成,例如由矽氮化物(SiN)形成。 於電荷累積膜53之表面上設置有阻擋絕緣膜54。阻擋絕緣膜54係即便於半導體記憶裝置1之驅動電壓之範圍內被施加電壓亦不會實質流通電流之膜。阻擋絕緣膜54係例如自電荷累積膜53側積層氧化矽層及氧化鋁層而成之雙層膜。 由穿隧絕緣膜52、電荷累積膜53及阻擋絕緣膜54構成能夠記憶資料之記憶膜55。因此,記憶膜55配置於矽柱50與電極膜32之間。 由此,於矽柱50與字元線WL之每個交叉部分,經由記憶膜55而構成MONOS(Metal-Oxide-Nitride-Oxide-Silicon,金屬氧化氮氧化矽)構造之記憶單元電晶體MC。矽柱50沿著X方向及Y方向排列成矩陣狀,字元線WL沿著Z方向排列,因而記憶單元電晶體MC排列成三維矩陣狀。由此,於位元線47與源極線29之間,形成有複數個記憶單元電晶體MC串聯連接而成之NAND串。又,藉由對各電晶體20之導通/斷開進行切換,而選擇性地對字元線WL等施加電位,從而能夠選擇任意之記憶單元電晶體MC。 接下來,對本實施形態之效果進行說明。 本實施形態之半導體記憶裝置1中,將選擇字元線WL等之電晶體20配置於半導體基板10與積層體30之間。由此,與將電晶體20配置於積層體30之周圍之情形相比,可減小晶片面積。其結果,可提高半導體記憶裝置1之集成度,並降低成本。 又,本實施形態中,於積層體30之X方向端部30a,交替地排列形成有較電晶體20之最小排列週期P更窄之階面33a之區域R1、及形成有較最小排列週期P更寬之階面33b之區域R2。由此,電晶體20之最小排列週期P與階面33a及33b之平均之排列週期大致一致,各電極膜32與各電晶體20之連接變得容易。且,藉由上層字元線43將配置於區域R1之觸點41引出至區域R2,且經由配置於區域R2且貫通積層體30之觸點42而連接於擴散區域22。由此,可有效活用區域R2而降低觸點42之配置密度。其結果,觸點41、觸點42及上層字元線43之佈局變得容易。 再者,由於配置複數個電晶體20所需之區域之X方向之長度較端部30a之X方向之長度更長,因而即便設置區域R2,半導體記憶裝置1亦不會大型化。 進而,於將積層體30之端部30a加工成階梯狀時,於半導體基板10上之整個面形成積層體30,且於該積層體30上形成抗蝕劑膜,然後,交替地進行以該抗蝕劑膜為掩模之蝕刻與該抗蝕劑膜之細化,由此逐層地將電極膜32部分地除去,而形成階面。該情形時,抗蝕劑膜之一次之細化量越大,階面之寬度越廣,需要提高抗蝕劑膜之初始高度,而加工變得困難。 因此,本實施形態中,將抗蝕劑膜之形成、細化及蝕刻之複數次之重複、以及包含抗蝕劑膜之除去之單元製程實施複數次。由此,利用一次之單元製程或連續實施之複數次之單元製程,於一個區域R1形成有複數個階面33a。然後,用以形成某區域R1之一次或複數次之單元製程中之最終加工端、與用以形成下一區域R1之一次或複數次之單元製程中之最初之加工端之間為區域R2。如此,與形成均勻之寬度之階面之情形相比,可抑制一次之細化量,可降低抗蝕劑膜之初始高度。其結果,半導體記憶裝置1之製造變得容易。 (第2實施形態) 接下來,對第2實施形態進行說明。 圖5係表示本實施形態之半導體記憶裝置之俯視圖。 圖6係圖5所示之B-B'線處之剖視圖。 圖7係圖5所示之C-C'線處之剖視圖。 圖8係表示圖6之區域D之局部放大剖視圖。 如圖5~圖7所示,本實施形態之半導體記憶裝置2與上述第1實施形態之半導體記憶裝置1(參照圖1~圖4)相比,代替電晶體20而設置有電晶體20a。於電晶體20a中之兩個擴散區域22之間設置有一個擴散區域23。於擴散區域23連接有用以對電晶體20供給源極電位之觸點(未圖示)。又,閘極電極25設置有2根,配置於阱21中之擴散區域22與擴散區域23之間之區域之正上方區域。由此,一個電晶體20a內包含獨立地進行驅動之兩個電晶體元件。 又,半導體記憶裝置2中,端部30a之階梯不僅沿著X方向,亦沿著Y方向形成。因此,自Z方向觀察,階面33a及33b排列成柵格狀。由此,可縮短端部30a之X方向上之長度。再者,與上述第1實施形態同樣地,端部30a之上表面於Y方向上之任意位置,沿著自積層體30之中央部30b朝向端部30a之X方向,即,遠離矽柱50之方向,中途不上升而階段性地下降。 此外,半導體記憶裝置2中,將Y方向上排列之複數條字元線WL在中央部30b之X方向之兩側交替地引出。即,當將沿著Y方向排列之複數條字元線WL交替地命名為字元線WL_A及字元線WL_B時,圖5~圖7所示之端部30a中,觸點41僅與字元線WL_A連接。另一方面,字元線WL_B於積層體30之X方向之相反側之端部30a(未圖示),連接於觸點41。如此,於積層體30之X方向兩側交替地引出字元線WL,由此可使觸點41及上層字元線43之佈局具有裕度。 如上述般,圖5~圖7所示之端部30a中,觸點41僅連接於字元線WL_A。因此,觸點41僅配置於字元線WL_A之正上方區域。另一方面,觸點42貫通字元線WL_B。因此,上層字元線43自字元線WL_A之正上方區域跨越字元線WL_B之正上方區域而延伸。即,於上層字元線43存在沿Y方向延伸之部分。如此,半導體記憶裝置2中,配置於字元線WL_A之正上方區域之觸點41利用上層字元線43而引出至字元線WL_B之正上方區域,經由觸點42連接於電晶體20a之擴散區域22。由此,能夠將觸點41及觸點42於Y方向上分散地配置,因而觸點41、觸點42及上層字元線43之佈局之制約得以緩和。 又,本實施形態中,亦與上述第1實施形態同樣地,配置於區域R1之觸點41之一部分連接於配置在區域R2之觸點42。由此,X方向上之觸點42之配置之制約得以緩和。由此,觸點41、觸點42及上層字元線43之佈局變得容易。再者,於X方向相反側之端部30a(未圖示),亦同樣配置有觸點41、觸點42及上層字元線43。 進而,於各電晶體20a之擴散區域23上設置有觸點48。觸點48之下端連接於擴散區域23。觸點48沿Z方向延伸,貫通源極線29及積層體30之端部30a。其中,觸點48與源極線29及電極膜32絕緣。觸點48上設置有上層源極線49。觸點48之上端連接於上層源極線49。上層源極線49例如沿Y方向延伸。再者,圖5及圖6中,為了容易觀看圖,僅示出1條上層源極線49。 如圖8所示,本實施形態之半導體記憶裝置2中,形成有浮動電極型之記憶單元電晶體MC。即,於由芯構件51、矽柱50及穿隧絕緣膜52構成之柱狀體與電極膜32之間,例如設置有由多晶矽等導電性材料構成之浮動閘極電極56。浮動閘極電極56之形狀為包圍穿隧絕緣膜52之圓環狀。浮動閘極電極56作為電荷累積構件發揮功能。浮動閘極電極56與電極膜32之間設置有阻擋絕緣膜54。阻擋絕緣膜54中,例如設置有覆蓋浮動閘極電極56之上表面、下表面及電極膜32側之側面之氧化鋁層54a,覆蓋電極膜32之上表面、下表面及浮動閘極電極56側之側面之氧化鋁層54c,以及配置於氧化鋁層54a與氧化鋁層54c之間之氧化矽層54b。 接下來,對本實施形態之效果進行說明。 本實施形態中,觸點41配置於字元線WL_A之正上方區域,觸點42配置於字元線WL_B之配置區域,觸點41之上端與觸點42之上端利用上層字元線43而連接。由此,可有效利用本來為無效空間之字元線WL_B之配置區域,而將字元線WL_A連接於擴散區域22。其結果,能夠確保觸點41與觸點42之間隔,從而容易形成佈局。本實施形態中之上述以外之構成及效果與上述第1實施形態相同。 (第3實施形態) 接下來,對第3實施形態進行說明。 圖9係表示本實施形態之半導體記憶裝置之俯視圖。 圖10係圖9所示之E-E'線處之剖視圖。 圖11係圖9所示之F-F'線處之剖視圖。 如圖9~圖11所示,本實施形態之半導體記憶裝置3中,未設置源極線29(參照圖1),矽柱50之下端連接於半導體基板10。又,於積層體30之端部30a,於Y方向上相鄰之源極側選擇閘極SGS間及字元線WL間,形成有沿X方向延伸之狹縫60。狹縫60內未配置電極膜32,而埋入有層間絕緣膜40。又,電晶體20a僅形成於狹縫60之正下方區域,觸點42配置於狹縫60內。另一方面,觸點41配置於電極膜32之正上方區域。如此,觸點41與觸點42於Y方向上隔開。因此,全部上層字元線43中存在沿Y方向延伸之部分,一部分上層字元線43中亦存在沿X方向延伸之部分。又,本實施形態中,亦於積層體30之端部30a,沿著X方向形成有階梯。 本實施形態之半導體記憶裝置3中,未設置源極線29,半導體基板10作為源極線發揮功能。由此,可抑制半導體記憶裝置4之製造步驟數或加工時間,製造變得容易。又,於積層體30之端部30a設置狹縫60,將電晶體20a配置於狹縫60之正下方區域,由此可避免閘極電極25、觸點27及下層配線28等之電晶體20a之上部構造體及附屬構造體與下層側之電極膜32發生干涉。又,因配置有觸點41之區域與配置有觸點42之區域分離,所以觸點41及42之配置、以及上層字元線43之引繞變得容易。本實施形態中之上述以外之構成及效果與上述第2實施形態相同。 (第4實施形態) 接下來,對第4實施形態進行說明。 圖12係表示本實施形態之半導體記憶裝置之俯視圖。 如圖12所示,本實施形態之半導體記憶裝置4中,沿著Y方向排列之複數條字元線WL連接於一個電晶體20之擴散區域22。例如,連接於Y方向上相鄰之2條字元線WL之2個觸點41與連接於一個電晶體20之擴散區域22之1個觸點42連接於1條上層字元線43。 根據本實施形態,可減少電晶體20之個數。本實施形態中之上述以外之構成及效果與上述第1實施形態相同。 (第5實施形態) 接下來,對第5實施形態進行說明。 圖13係表示本實施形態之半導體記憶裝置之積層體之俯視圖。 圖14係表示本實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖15係表示本實施形態之半導體記憶裝置之剖視圖。 如圖13~圖15所示,本實施形態之半導體記憶裝置5中,一個記憶體區塊之電晶體20不僅沿著X方向,亦沿著Y方向排成複數列。又,一個電晶體20之擴散區域22連接於複數個,例如4個電極膜32。觸點42配置於區域R2,沿著X方向排成一行。本實施形態中,X方向上之階面33a之長度L1較電晶體20之最小排列週期P短,階面33b之長度L2較電晶體20之最小排列週期P長。即,L1<P<L2成立。 以下,對半導體記憶裝置5之構成進行詳細說明。 半導體記憶裝置5中,設置有沿著Z方向排列之13層之電極膜32。該等電極膜32自下層側開始依次設為電極膜32c~32o。其中,最下層之電極膜32c係源極側選擇閘極SGS。一個記憶體區塊中,電極膜32c沿著Y方向排列有4片,且連接於相同之電晶體20。自最下層算起之第二個電極膜32d至自最上層算起之第二個電極膜32n係字元線WL。一個記憶體區塊中,電極膜32d~32n各自沿著Y方向排列有4片,且各自連接於相同之電晶體20。 最上層之電極膜32o為汲極側選擇閘極SGD。一個記憶體區塊中,電極膜32o沿著Y方向排列有8片,且連接於互不相同之電晶體20。再者,將屬於一個記憶體區塊之8片電極膜32o稱作電極膜32o1~32o8。Y方向上之汲極側選擇閘極SGD之排列週期為字元線WL之排列週期之一半。因此,於某一條字元線WL之正上方區域配置有2根汲極側選擇閘極SGD。 於半導體記憶裝置5中設置有20個電晶體20。將該等電晶體20設為電晶體20c~20v。又,將電晶體20c之擴散區域22設為擴散區域22c。進而,將觸點27、下層配線28、觸點42、上層字元線43、觸點41中連接於電晶體20c者分別設為觸點27c、下層配線28c、觸點42c、上層字元線43c、觸點41c。對於電晶體20d~20v亦同。 電晶體20c之擴散區域22c係利用觸點27c、下層配線28c、觸點42c而朝大致正上方引出,利用上層字元線43c朝Y方向引出,呈U字狀繞半周,並經由4個觸點41c而連接於4片電極膜32c(源極側選擇閘極SGS)。 自電晶體20c觀察,電晶體20d配置於Y方向側。電晶體20d之擴散區域22d係利用下層配線28d被引出至擴散區域22c之正上方區域,利用觸點42d朝正上方引出,利用上層字元線43d繞上層字元線43c之外側半周,經由4個觸點41d而連接於4片電極膜32d(字元線WL)。 自電晶體20d觀察,電晶體20e配置於X方向側。電晶體20e之擴散區域22e係利用下層配線28e被引出至擴散區域22f之正上方區域,利用觸點42e朝正上方引出,利用上層字元線43e朝上層字元線43d之反方向繞半周,經由4個觸點41e而連接於4片電極膜32e(字元線WL)。 自電晶體20e觀察,電晶體20f配置於Y方向側。電晶體20f之擴散區域22f係利用觸點27f、下層配線28f、觸點42f朝大致正上方引出,利用上層字元線43f繞上層字元線43e之內側半周,經由4個觸點41f而連接於4片電極膜32f(字元線WL)。 如此,電晶體20c~20f分別連接於4片電極膜32c~32f。又,電晶體20c~20f之擴散區域23分別連接於下層配線39。下層配線39大致沿Y方向延伸。下層配線39之Z方向上之位置與下層配線28之Z方向上之位置相同。下層配線39亦可將其幹線部作為上層配線,該情形時,經由追加之觸點而將下層配線39連接於成為幹線部之上層配線。 利用與自電晶體20c~20f至電極膜32c~32f之電流路徑相同之繞半周之配線圖案,電晶體20g~20j分別連接於4片電極膜32g~32j。又,利用同樣繞半周之配線圖案,電晶體20k~20n分別連接於4片電極膜32k~32n。 電晶體20o之擴散區域22o利用觸點27o、下層配線28o、觸點42o引出至大致正上方,於利用上層字元線43o沿Y方向引出後,沿X方向引出,並經由1個觸點41o而連接於1片電極膜32o2(汲極側選擇閘極SGD)。自Z方向觀察,上層字元線43o之形狀為L字狀。 電晶體20p之擴散區域22p利用下層配線28p引出至擴散區域22o之正上方區域,利用觸點42p引出至正上方,利用上層字元線43p呈L字狀引繞在上層字元線43o之外側,經由1個觸點41p連接於1片電極膜32o1(汲極側選擇閘極SGD)。 利用與自電晶體20o及20p至電極膜32o2及32o1之電流路徑相同之L字狀之配線圖案,電晶體20q之擴散區域22q連接於電極膜32o4,電晶體20r之擴散區域22r連接於電極膜32o3。 利用同樣之L字狀之配線圖案,電晶體20s之擴散區域22s連接於電極膜32o7,電晶體20t之擴散區域22t連接於電極膜32o8。又,電晶體20u之擴散區域22u連接於電極膜32o5,電晶體20v之擴散區域22v連接於電極膜32o6。 接下來,對本實施形態之效果進行說明。 本實施形態中,電晶體20不僅於X方向上亦於Y方向上排列,因而可縮短電晶體20之配置區域及積層體30之端部30a之X方向上之長度。 本實施形態中之上述以外之構成及效果與上述第1實施形態相同。 (第6實施形態) 接下來,對第6實施形態進行說明。 圖16係表示本實施形態之半導體記憶裝置之積層體之俯視圖。 圖17係表示本實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖18係表示本實施形態之半導體記憶裝置之剖視圖。 如圖16~圖18所示,本實施形態之半導體記憶裝置6中,端部30a之階梯不僅沿著X方向亦沿著Y方向形成。沿著X方向之階梯跨越沿著Z方向排列之全部之電極膜32而形成,於2片電極膜32之每一片形成一個台階。沿著Y方向之階梯僅與1片電極膜32對應地形成,相對於該1片電極膜32形成一個台階。即,當將積層體30中沿著Z方向排列之電極膜32之片數設為n時,沿著X方向,於2片電極膜32之每一片形成有(n/2)段台階,沿著Y方向,僅形成有與1片電極膜32對應之1段台階。由此,能夠在n片電極膜32之全部形成階面。若觀察端部30a整體,則配置有較Y方向上相鄰之階面高1段之階面之區域H之形狀自Z方向觀察為梳狀。 又,半導體記憶裝置6中,沿著Y方向排列之複數條字元線WL向積層體30之X方向兩側每2條地交替引出。即,於將沿著Y方向排列之複數條字元線WL設為字元線WL_A、字元線WL_A、字元線WL_B、字元線WL_B、字元線WL_A、字元線WL_A…時,於圖16~圖18所示之端部30a,觸點41僅與字元線WL_A連接。另一方面,於相反側之端部30a(未圖示),觸點41連接於字元線WL_B。 此外,半導體記憶裝置6中,與上述第5實施形態之半導體記憶裝置5(參照圖13~圖15)同樣地,電晶體20不僅沿著X方向,亦沿著Y方向排列。又,一個電晶體20之擴散區域22例如連接於2個電極膜32。 又,於圖16~圖18所示之端部30a,觸點41配置於字元線WL_A之正上方區域。另一方面,觸點42配置於貫通字元線WL_B之位置。因此,上層字元線43自字元線WL_A之正上方區域延伸至字元線WL_B之正上方區域。因此,於上層字元線43存在沿Y方向延伸之部分。觸點42沿著X方向排成一行。 關於源極側選擇閘極SGS,亦與字元線WL同樣地,向積層體30之X方向兩側每2根地交替引出。汲極側選擇閘極SGD向積層體30之X方向兩側每4根地交替引出。 接下來,對本實施形態之效果進行說明。 本實施形態中,積層體30之端部30a,除形成沿著X方向之主階梯外,亦形成沿著Y方向之副階梯。由此,可縮短端部30a之X方向上之長度。 又,本實施形態中,將電極膜32向積層體30之X方向兩側交替地引出。由此,與將電極膜32向X方向單側引出之情形相比,能夠將形成於單方之端部30a之正下方區域之電晶體20之個數設為一半。其結果,上層字元線43等之佈局之製作變得容易。 進而,本實施形態中,觸點41配置於字元線WL_A之正上方區域,觸點42配置於字元線WL_B之配置區域。由此,可有效利用本來為無效空間之字元線WL_B之配置區域,而引繞配線。 本實施形態之上述以外之構成及效果與上述第1實施形態相同。 (第7實施形態) 接下來,對第7實施形態進行說明。 圖19係表示本實施形態之半導體記憶裝置之積層體之俯視圖。 圖20係表示本實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖21係表示本實施形態之半導體記憶裝置之剖視圖。 如圖19~圖21所示,本實施形態之半導體記憶裝置7與上述第6實施形態之半導體記憶裝置6(參照圖16~圖18)相比,於區域H之形狀為島狀這一方面有所不同。如上述般,區域H係配置有較Y方向上相鄰之階面高1段之階面之區域。 由此,本實施形態中,與第6實施形態相比,Y方向上相鄰之電晶體20間,所連接之電極膜32相反。又,於自積層體30之中央部30b朝向端部30a之方向上,區域H之中央部30b側之端緣為上升1段之台階US。然而,台階US係因加工上之理由而產生之形狀,以台階US為端面之電極膜32與實際發揮功能之電極膜孤立開而被絕緣,且不電性地發揮功能。關於實際發揮功能之電極膜,與其他實施形態同樣地,於自中間部30b朝向端部30a之方向上,中途不上升而階段性地下降。沿著Y方向排列之階面亦可與沿著X方向排列之階面同樣地,形成有多段。 本實施形態中,能夠將沿著Y方向排列之字元線WL與汲極側選擇閘極SGD於同一步驟中形成,從而可削減步驟數。 本實施形態中之上述以外之構成及效果與上述第6實施形態相同。 (第8實施形態) 接下來,對第8實施形態進行說明。 圖22係表示本實施形態之半導體記憶裝置之積層體之俯視圖。 圖23係表示本實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖24係表示本實施形態之半導體記憶裝置之剖視圖。 如圖22~圖24所示,本實施形態之半導體記憶裝置8與上述第7實施形態之半導體記憶裝置6(參照圖19~圖21)相比,觸點41及42之排列不同。 半導體記憶裝置8中,關於各個源極側選擇閘極SGS及字元線WL,連接於沿著Y方向排列之兩個階面之2個觸點41與經由上層字元線43連接於該等觸點41之2個觸點42,沿著Y方向排成一行。即,X方向上,2個觸點41之位置及2個觸點42之位置彼此相等。關於汲極側選擇閘極SGD,連接於沿著Y方向排列之兩個階面之4個觸點41沿著Y方向排成一行,連接於該4個觸點41之4個觸點42亦沿著Y方向排成一行。即,X方向上之4個觸點41之位置彼此相等,4個觸點42之位置亦彼此相等。然而,X方向上,觸點41之位置與觸點42之位置互不相同。 本實施形態中之上述以外之構成及效果與上述第7實施形態相同。 (第9實施形態) 接下來,對第9實施形態進行說明。 圖25係表示本實施形態之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖26係表示本實施形態之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖27係表示本實施形態之半導體記憶裝置之剖視圖。 如圖25~圖27所示,本實施形態之半導體記憶裝置9中,2塊晶片101及102經由凸塊103而貼合。晶片101中設置有積層體30。晶片102中形成有電晶體20。而且,設置於晶片101之電極膜32經由凸塊103而連接於形成在晶片102之電晶體20。半導體記憶裝置9中,圖25所示之晶片102與圖26所示之晶片101以各自之上表面側對向之方式貼合。再者,圖27表示包含凸塊103之中心之剖面,但為了方便說明,亦示出下層配線28及觸點42。 以下,更詳細地進行說明。 晶片101中,例如設置有包含矽之半導體基板11,於半導體基板11上設置有積層體30,以覆蓋積層體30之方式設置有層間絕緣膜40。然而,並未於半導體基板11形成有電晶體20,並未於半導體基板11與積層體30之間設置有源極線29(參照圖24)。又,於積層體30之各電極膜32之階面上設置有觸點41,觸點41上設置有上層字元線43,觸點41之上端連接於上層字元線43。然而,未設置觸點42(參照圖24)。於層間絕緣膜40之上層部分設置有焊墊64,露出於層間絕緣膜40之上表面。焊墊64例如由銅形成。上層字元線43與焊墊64之間連接有觸點63。 本實施形態中,與上述第6實施形態(參照圖16~圖18)同樣地,電極膜32向積層體30之X方向兩側引出。即,沿著Y方向排列之複數條源極側選擇閘極SGS及複數條字元線WL向積層體30之X方向兩側每2根地交替引出。又,沿著Y方向排列之複數條汲極側選擇閘極SGD向積層體30之X方向兩側每4根地交替引出。 而且,Y方向上相鄰之2根源極側選擇閘極SGS經由觸點41連接於共用之上層字元線43,經由1個觸點63連接於一個焊墊64。又,Y方向上相鄰之2條字元線WL經由觸點41而連接於共用之上層字元線43,經由1個觸點63連接於一個焊墊64。然而,Z方向上之位置互不相同之字元線WL連接於互不相同之上層字元線43。進而,沿著Y方向排列之4根汲極側選擇閘極SGD經由觸點41、上層字元線43及觸點63而連接於互不相同之焊墊64。如此,各電極膜32經由觸點41、上層字元線43及觸點63連接於任一焊墊64。 另一方面,晶片102中,例如設置有包含矽之半導體基板12,於半導體基板12上設置有層間絕緣膜66。於半導體基板12之上層部分內及層間絕緣膜66內形成有電晶體20,沿著X方向及Y方向排列成矩陣狀。電晶體20之構成與上述第1實施形態相同。於層間絕緣膜66之上層部分設置有焊墊67。焊墊67例如由銅形成。焊墊67與下層配線28之間連接有觸點42。如此,各電晶體20之擴散區域22經由觸點27、下層配線28及觸點42連接於任一焊墊67。 晶片101與晶片102以焊墊64與焊墊67對向之方式配置,焊墊64與焊墊67之間接合有凸塊103。凸塊103為由導電性材料構成之凸塊,例如,為焊錫球。利用凸塊103,焊墊64電連接於焊墊67,並且晶片101機械連結於晶片102。由此,晶片101之電極膜32連接於晶片102之電晶體20之擴散區域22。 X方向上,當將焊墊64之最小排列週期設為P1、電晶體20之最小排列週期設為P2時,X方向上之階面T之長度由週期P1及週期P2中之任一較大之週期P=MAX(P1,P2)所決定。配置於區域R1之階面33a之長度L1較週期P短。又,配置於區域R2之階面33b之長度L2較週期P長。即,L1<P<L2。 接下來,對本實施形態之效果進行說明。 本實施形態中,設置2塊晶片101及102,於晶片101形成積層體30,於晶片102形成電晶體20。由此,與於一塊晶片形成電晶體20及積層體30之雙方之情形相比,製造容易,且製造成本低。 又,因無需在晶片101內設置觸點42,所以能夠簡化上層字元線43之佈局。由此,上層字元線43之佈局之製作變得容易,並且可抑制伴隨配線之微細化之動作速度之降低、消耗電力之增大及可靠性之降低。 本實施形態中之上述以外之構成及效果與上述第1實施形態相同。 (第9實施形態之第1變化例) 接下來,對第9實施形態之第1變化例進行說明。 圖28係表示本變化例之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖29係表示本變化例之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖30係表示本變化例之半導體記憶裝置之剖視圖。 如圖28~圖30所示,本變化例之半導體記憶裝置9a中,晶片101與晶片102利用導電性之柱104而接合。柱104例如由銅形成,其形狀例如為圓柱形。晶片101及晶片102之構成與上述第9實施形態相同。 本變化例中之上述以外之構成及效果與上述第9實施形態相同。 (第9實施形態之第2變化例) 接下來,對第9實施形態之第2變化例進行說明。 圖31係表示本變化例之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖32係表示本變化例之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖33係表示本變化例之半導體記憶裝置之剖視圖。 如圖31~圖33所示,本變化例之半導體記憶裝置9b中,晶片101與晶片102直接貼合。例如,利用接著劑或機械手段將晶片101連結於晶片102,晶片101之焊墊64與晶片102之焊墊67接觸。焊墊64與焊墊67亦可利用導電性之接著劑而接著。晶片101及晶片102之構成與上述第9實施形態相同。 本變化例中之上述以外之構成及效果與上述第9實施形態相同。 根據以上說明實施形態及其變化例,可實現配線之佈局容易之半導體記憶裝置。 再者,於第1、第3、第4、第9實施形態以及第9實施形態之第1及第2變化例中,亦可於積層體30之端部30a沿著Y方向形成階梯。 以上,對本發明之幾個實施形態及其變化例進行了說明,但該等實施形態及變化例係作為示例而提示,並不意圖限定發明之範圍。該等新穎之實施形態及變化例能夠以其他各種形態實施,於不脫離發明之主旨之範圍內能夠進行各種省略、置換、變更。該等實施形態或其變化包含在發明之範圍或主旨內,並且包含在申請專利範圍所記載之發明及其等價物之範圍內。又,上述實施形態及變化例亦可相互組合而實施。 [相關申請案] 本申請案享有以美國臨時專利申請案62/374,034號(申請日:2016年8月12日)及日本專利申請案2017-16330號(申請日:2017年1月31日)為基礎申請案之優先權。本申請案藉由參照該等基礎申請案而包含基礎申請案之全部內容。 (1st Embodiment) First, 1st Embodiment is demonstrated. FIG. 1 is a cross-sectional view showing a semiconductor memory device of the present embodiment. FIG. 2 is a plan view showing a wiring portion of the semiconductor memory device of the present embodiment. FIG. 3 is a plan view showing the substrate surface of the semiconductor memory device of the present embodiment. FIG. 4 is a partially enlarged cross-sectional view showing a region A of FIG. 1 . The semiconductor memory device of the present embodiment is, for example, a non-volatile semiconductor memory device, such as a multilayer NAND flash memory. As shown in FIGS. 1 to 3 , the semiconductor memory device 1 of the present embodiment is provided with a semiconductor substrate 10 . Hereinafter, in this specification, the XYZ orthogonal coordinate system is used for convenience of description. The two directions parallel to the upper surface 10a of the semiconductor substrate 10 and orthogonal to each other are referred to as the "X direction" and the "Y direction", and the direction perpendicular to the upper surface of the semiconductor substrate 10 is referred to as the "Z direction". In the Z direction, the direction from the semiconductor substrate 10 toward the layered body 30 described later is referred to as "up", and the opposite direction is referred to as "down", but these expressions are for convenience of explanation and have nothing to do with the direction of gravity. The semiconductor substrate 10 is formed of, for example, a single crystal of silicon. For example, a p-type well 21 is formed in a portion of the upper layer portion of the semiconductor substrate 10 . An STI (Shallow Trench Isolation, Shallow Trench Isolation) 26 is disposed on a portion of the upper layer portion of the well 21 in a lattice shape, and the upper layer portion of the well 21 is divided into a plurality of body regions 21a. The main body regions 21a are arranged in a matrix along the X direction and the Y direction. The field effect transistor 20 is provided on the upper surface of each body region 21 a, that is, the region surrounded by the STI 26 in the upper surface 10 a of the semiconductor substrate 10 . The n-type diffusion regions 22 and 23 are formed to be spaced apart from each other on the upper portions of both end portions in the Y direction of each main body region 21a. The diffusion regions 22 and 23 are the source and drain regions of the transistor 20 . In addition, a gate insulating film 24 is provided on the well 21 , and a gate electrode 25 is provided on the gate insulating film 24 . The arrangement period of the transistors 20 in the X direction is substantially constant. In more detail, a plurality of transistors 20 are disposed in a specific area on the upper surface 10a of the semiconductor substrate 10, and in this area, the arrangement period of the transistors 20 in the X direction is fixed. In this specification, this arrangement period is referred to as a "minimum arrangement period". In the present embodiment, only one of the regions is shown, but as in the ninth embodiment described later, a plurality of regions may be provided. In this case, the distance between adjacent regions is greater than the interval between the transistors 20 determined by the minimum arrangement period. On the semiconductor substrate 10 and the transistor 20, a contact 27, a lower layer wiring 28 and a source line 29 are arranged from bottom to top. Furthermore, the lower layer wirings 28 are provided with multiple layers, and can also be connected to each other through via contacts. The lower end of the contact 27 is connected to the diffusion region 22 , and the upper end is connected to the lower layer wiring 28 . The source line 29 is provided on the lower layer wiring 28 and has a plate shape extending along the XY plane. The laminated body 30 is provided on the source line 29 . In the laminated body 30, the insulating films 31 and the electrode films 32 are alternately laminated along the Z direction. The insulating film 31 is formed of, for example, an insulating material such as silicon oxide (SiO), and the electrode film 32 is formed of, for example, a conductive material such as tungsten (W) or polysilicon (Si) into which an impurity has been introduced. The transistor 20 is a transistor for driving the electrode film 32 . In the semiconductor memory device 1, in addition to the transistor 20, for example, a transistor that constitutes a peripheral circuit (not shown) may also be provided. As shown in FIG. 2, the electrode film 32 is divided into a plurality of strip-shaped portions arranged along the Y direction. Each strip portion extends in the X direction. In this embodiment, the strip-shaped portion of the electrode film 32 of the lowermost layer functions as the source-side selective gate SGS, and the strip-shaped portion of the electrode film 32 of the uppermost layer functions as the drain-side selective gate SGD. The strip-shaped portion of the electrode film 32 functions as a word line WL. Furthermore, the strip-shaped portion of the multilayer electrode film 32 from the lowermost layer can function as the source-side selective gate SGS, and the strip-shaped portion of the multilayer electrode film 32 from the uppermost layer can also function as the drain-side selection electrode. The gate SGD functions. The arrangement period of the drain side selection gate SGD in the Y direction is half the arrangement period of the source side selection gate SGS and the word line WL. That is, two drain-side selection gates SGD are arranged in the region just above one word line WL. Furthermore, one or three or more drain-side selection gates SGD may be arranged in the region directly below one word line WL. The shape of the end portion 30 a of the layered body 30 in the X direction is a stepped shape in which each electrode film 32 is formed with a stepped surface. The step surface is the upper surface of the end portion of the electrode film 32 in the X direction. The upper electrode film 32 is not disposed in the region just above the step surface. The end portion 30 a is disposed in the region just above the transistor 20 . On the other hand, the central portion 30 b in the X direction in the laminated body 30 is not arranged in the region directly above the transistor 20 . The upper surface of the edge part 30a goes in the direction from the X direction center part 30b in the laminated body 30 to the edge part 30a, and does not rise in the middle, but descends stepwise. However, its decline is not cyclical. Specifically, at the end portion 30a, the regions R1 and R2 are alternately arranged along the X direction. In the region R1, a plurality of steps 33a having a narrow width are arranged along the X direction. On the other hand, in the region R2, one stepped surface 33b having a wider width is arranged. The length L2 of the step surface 33b in the X direction is longer than the length L1 of the step surface 33a. In addition, in the X direction, the length L1 of the step surface 33 a is shorter than the minimum arrangement period P of the transistor 20 , and the length L2 of the step surface 33 b is longer than the minimum arrangement period P of the transistor 20 . That is, L1<P<L2. On the semiconductor substrate 10 , an interlayer insulating film 40 is provided so as to cover the laminate 30 . A plurality of contacts 41 and a plurality of contacts 42 are provided in the interlayer insulating film 40 . Upper word lines 43 are connected between the upper ends of the contacts 41 and the upper ends of the contacts 42 . The upper-layer word line 43 is disposed above the build-up body 30 in the interlayer insulating film 40 . The contact 41 extends along the Z direction, and the lower end of the contact 41 is connected to the electrode film 32 at the stepped surface 33a or the stepped surface 33b. Therefore, the electrode film 32 in which the stepped surface 33a of the electrode film 32 is located in the region R1 is connected to the contact 41 in the region R1. On the other hand, the electrode film 32 of the step surface 33b located in the region R2 is connected to the contact 41 located in the region R2. Therefore, the contacts 41 are arranged in both the region R1 and the region R2. The contact 42 is arranged in the region R2. The contact 42 extends in the Z direction and penetrates the end portion 30 a of the laminate 30 and the source line 29 . The lower end of the contact 42 is connected to the lower layer wiring 28 . An insulating film 44 is provided around the contact 42 . The contact 42 is insulated from the electrode film 32 and the source line 29 by the insulating film 44 . In this way, each electrode film 32 is connected to the diffusion region 22 of the transistor 20 via the contact 41 , the upper word line 43 , the contact 42 , the lower wiring 28 , and the contact 27 . In addition, the electrode film 32 of the step surface 33a located in the region R1 is connected to the diffusion region 22 via the contact 41 in the region R1 and the contact 42 in the region R2. The electrode film 32 of the step surface 33b located in the region R2 is connected to the diffusion region 22 via the contact 41 in the region R2 and the contact 42 in the region R2. On the other hand, a silicon pillar 50 extending in the Z direction is provided in the central portion 30 b of the laminate 30 . The silicon pillar 50 is made of polysilicon, for example, and has a cylindrical shape with a closed lower end. The lower end of the silicon pillar 50 is connected to the source line 29 . The upper end of the silicon pillar 50 is connected to the bit line 47 through the through-hole contact 46 . The bit line 47 is arranged on the central portion 30b of the multilayer body 30 and extends in the Y direction. As shown in FIG. 4 , the silicon pillar 50 is provided with a core member 51 made of, for example, silicon oxide. In addition, the core member 51 may not be provided. A tunnel insulating film 52 is provided on the side surface of the silicon pillar 50 . The tunnel insulating film 52 is generally insulating, but when a specific voltage within the driving voltage range of the semiconductor memory device 1 is applied, a tunnel current flows. The tunnel insulating film 52 is formed of, for example, a single-layer silicon layer, or an ONO film formed by laminating a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer in this order. A charge accumulation film 53 is provided on the surface of the tunnel insulating film 52 . The charge accumulating film 53 is a film having the ability to accumulate charges, and is formed of, for example, a material having a trap site for electrons, such as silicon nitride (SiN). A blocking insulating film 54 is provided on the surface of the charge accumulating film 53 . The blocking insulating film 54 is a film that does not substantially flow current even when a voltage is applied within the range of the driving voltage of the semiconductor memory device 1 . The blocking insulating film 54 is, for example, a double-layer film formed by laminating a silicon oxide layer and an aluminum oxide layer from the charge accumulation film 53 side. A memory film 55 capable of storing data is constituted by the tunnel insulating film 52 , the charge accumulation film 53 and the blocking insulating film 54 . Therefore, the memory film 55 is disposed between the silicon pillar 50 and the electrode film 32 . Thus, a memory cell transistor MC of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure is formed at each intersection of the silicon pillar 50 and the word line WL through the memory film 55 . The silicon pillars 50 are arranged in a matrix along the X direction and the Y direction, and the word lines WL are arranged along the Z direction, so that the memory cell transistors MC are arranged in a three-dimensional matrix. Thereby, a NAND string in which a plurality of memory cell transistors MC are connected in series is formed between the bit line 47 and the source line 29 . In addition, by switching on/off of each transistor 20 to selectively apply a potential to the word line WL or the like, an arbitrary memory cell transistor MC can be selected. Next, the effect of this embodiment is demonstrated. In the semiconductor memory device 1 of the present embodiment, the transistors 20 for selecting the word lines WL and the like are arranged between the semiconductor substrate 10 and the laminate 30 . Thereby, compared with the case where the transistor 20 is arrange|positioned around the laminated body 30, the wafer area can be reduced. As a result, the integration degree of the semiconductor memory device 1 can be improved, and the cost can be reduced. In addition, in this embodiment, at the X-direction end portion 30a of the laminate 30, the regions R1 in which the steps 33a narrower than the minimum arrangement period P of the transistors 20 are formed and the regions R1 formed with the minimum arrangement period P are alternately arranged. The region R2 of the wider step surface 33b. As a result, the minimum arrangement period P of the transistors 20 and the average arrangement period of the step surfaces 33 a and 33 b are substantially identical, and the connection between the electrode films 32 and the transistors 20 is facilitated. Then, the contact 41 arranged in the region R1 is drawn out to the region R2 by the upper word line 43 , and is connected to the diffusion region 22 through the contact 42 arranged in the region R2 and penetrating the laminate 30 . As a result, the area R2 can be effectively utilized to reduce the arrangement density of the contacts 42 . As a result, the layout of the contact 41, the contact 42, and the upper word line 43 becomes easy. Furthermore, since the length in the X direction of the region required for arranging the plurality of transistors 20 is longer than the length in the X direction of the end portion 30a, even if the region R2 is provided, the size of the semiconductor memory device 1 is not increased. Furthermore, when the end portion 30 a of the layered body 30 is processed into a stepped shape, the layered body 30 is formed on the entire surface of the semiconductor substrate 10 , and a resist film is formed on the layered body 30 , and then the layered body 30 is alternately formed. The resist film is the etching of the mask and the thinning of the resist film, whereby the electrode film 32 is partially removed layer by layer to form a step surface. In this case, the larger the amount of thinning of the resist film at one time, the wider the width of the step surface, the need to increase the initial height of the resist film, and the processing becomes difficult. Therefore, in the present embodiment, the formation of the resist film, the thinning and the etching are repeated several times, and the unit process including the removal of the resist film is carried out several times. As a result, a plurality of steps 33 a are formed in one region R1 by one unit process or a plurality of unit processes performed continuously. Then, a region R2 is formed between the final processing end in one or more unit processes for forming a certain region R1 and the first processing end in one or more unit processes for forming the next region R1. In this way, the amount of thinning can be suppressed once, and the initial height of the resist film can be reduced as compared with the case where the step surface with a uniform width is formed. As a result, the manufacture of the semiconductor memory device 1 becomes easy. (Second Embodiment) Next, a second embodiment will be described. FIG. 5 is a plan view showing the semiconductor memory device of the present embodiment. FIG. 6 is a cross-sectional view taken along line BB' shown in FIG. 5 . FIG. 7 is a cross-sectional view taken along the line CC' shown in FIG. 5 . FIG. 8 is a partial enlarged cross-sectional view showing a region D of FIG. 6 . As shown in FIGS. 5 to 7 , the semiconductor memory device 2 of the present embodiment is provided with a transistor 20 a instead of the transistor 20 as compared with the semiconductor memory device 1 of the first embodiment (see FIGS. 1 to 4 ). A diffusion region 23 is disposed between the two diffusion regions 22 in the transistor 20a. A contact (not shown) for supplying a source potential to the transistor 20 is connected to the diffusion region 23 . In addition, two gate electrodes 25 are provided, and are arranged in the region just above the region between the diffusion region 22 and the diffusion region 23 in the well 21 . Thus, one transistor 20a includes two transistor elements that are independently driven. In addition, in the semiconductor memory device 2, the step of the end portion 30a is formed not only along the X direction but also along the Y direction. Therefore, when viewed from the Z direction, the stepped surfaces 33a and 33b are arranged in a grid shape. As a result, the length in the X direction of the end portion 30a can be shortened. Furthermore, as in the first embodiment described above, any position on the upper surface of the end portion 30 a in the Y direction is along the X direction from the central portion 30 b of the laminate 30 toward the end portion 30 a, that is, away from the silicon pillar 50 . In the direction of the direction, it does not rise in the middle, but declines in stages. In addition, in the semiconductor memory device 2, a plurality of word lines WL arranged in the Y direction are drawn out alternately on both sides of the central portion 30b in the X direction. That is, when the plurality of word lines WL arranged in the Y direction are alternately named as word line WL_A and word line WL_B, in the end portion 30a shown in FIGS. The element line WL_A is connected. On the other hand, the word line WL_B is connected to the contact 41 at the end 30 a (not shown) on the opposite side in the X direction of the laminate 30 . In this way, the word lines WL are drawn out alternately on both sides of the multilayer body 30 in the X direction, so that the layout of the contacts 41 and the upper word lines 43 can have a margin. As described above, in the end portion 30a shown in FIGS. 5 to 7, the contact 41 is connected only to the word line WL_A. Therefore, the contact 41 is arranged only in the area just above the word line WL_A. On the other hand, the contact 42 penetrates the word line WL_B. Therefore, the upper-layer word line 43 extends from the region immediately above the word line WL_A across the region immediately above the word line WL_B. That is, there is a portion extending in the Y direction in the upper word line 43 . In this way, in the semiconductor memory device 2 , the contact 41 disposed in the area just above the word line WL_A is led out to the area just above the word line WL_B by the upper word line 43 , and is connected to the transistor 20 a through the contact 42 . Diffusion region 22 . As a result, the contacts 41 and the contacts 42 can be dispersedly arranged in the Y direction, so that restrictions on the layout of the contacts 41 , the contacts 42 , and the upper-layer word lines 43 are eased. Moreover, also in this embodiment, like the said 1st Embodiment, a part of the contact 41 arrange|positioned in the area|region R1 is connected to the contact 42 arrange|positioned in the area|region R2. As a result, restrictions on the arrangement of the contacts 42 in the X direction are eased. Thereby, the layout of the contacts 41, the contacts 42, and the upper word lines 43 becomes easy. In addition, the contact 41, the contact 42, and the upper word line 43 are similarly arrange|positioned at the edge part 30a (not shown) on the opposite side in the X direction. Furthermore, a contact 48 is provided on the diffusion region 23 of each transistor 20a. The lower end of the contact 48 is connected to the diffusion region 23 . The contact 48 extends in the Z direction and penetrates the source line 29 and the end portion 30 a of the laminate 30 . Among them, the contact 48 is insulated from the source line 29 and the electrode film 32 . An upper layer source line 49 is provided on the contact 48 . The upper end of the contact 48 is connected to the upper source line 49 . The upper layer source line 49 extends, for example, in the Y direction. In addition, in FIGS. 5 and 6 , only one upper-layer source line 49 is shown for ease of viewing. As shown in FIG. 8, in the semiconductor memory device 2 of the present embodiment, a floating electrode type memory cell transistor MC is formed. That is, a floating gate electrode 56 made of, for example, a conductive material such as polysilicon is provided between the columnar body including the core member 51 , the silicon pillar 50 and the tunnel insulating film 52 and the electrode film 32 . The shape of the floating gate electrode 56 is an annular shape surrounding the tunnel insulating film 52 . The floating gate electrode 56 functions as a charge accumulation member. A barrier insulating film 54 is provided between the floating gate electrode 56 and the electrode film 32 . In the barrier insulating film 54 , for example, an aluminum oxide layer 54 a covering the upper and lower surfaces of the floating gate electrode 56 and the side surface of the electrode film 32 is provided, and covering the upper and lower surfaces of the electrode film 32 and the floating gate electrode 56 The aluminum oxide layer 54c on the side surface, and the silicon oxide layer 54b disposed between the aluminum oxide layer 54a and the aluminum oxide layer 54c. Next, the effect of this embodiment is demonstrated. In this embodiment, the contact 41 is arranged in the region just above the word line WL_A, the contact 42 is arranged in the arrangement region of the word line WL_B, and the upper end of the contact 41 and the upper end of the contact 42 are connected by the upper word line 43. connect. This makes it possible to connect the word line WL_A to the diffusion region 22 by effectively utilizing the arrangement area of the word line WL_B, which is originally an invalid space. As a result, the distance between the contact 41 and the contact 42 can be secured, and the layout can be easily formed. The configurations and effects of the present embodiment other than those described above are the same as those of the first embodiment described above. (3rd Embodiment) Next, 3rd Embodiment is demonstrated. FIG. 9 is a plan view showing the semiconductor memory device of the present embodiment. FIG. 10 is a cross-sectional view taken along the line EE' shown in FIG. 9 . FIG. 11 is a cross-sectional view taken along the line FF' shown in FIG. 9 . As shown in FIGS. 9 to 11 , in the semiconductor memory device 3 of the present embodiment, the source line 29 (see FIG. 1 ) is not provided, and the lower end of the silicon pillar 50 is connected to the semiconductor substrate 10 . In addition, slits 60 extending in the X direction are formed at the end portion 30a of the laminate 30 between adjacent source side selection gates SGS in the Y direction and between the word lines WL. The electrode film 32 is not disposed in the slit 60, but the interlayer insulating film 40 is embedded. In addition, the transistor 20 a is formed only in the region just below the slit 60 , and the contact 42 is arranged in the slit 60 . On the other hand, the contact 41 is arranged in the region just above the electrode film 32 . In this way, the contacts 41 and 42 are spaced apart in the Y direction. Therefore, all the upper word lines 43 have portions extending in the Y direction, and some upper word lines 43 also have portions extending in the X direction. Moreover, also in this embodiment, the edge part 30a of the laminated body 30 is formed with a step along the X direction. In the semiconductor memory device 3 of the present embodiment, the source line 29 is not provided, and the semiconductor substrate 10 functions as a source line. Thereby, the number of manufacturing steps and processing time of the semiconductor memory device 4 can be suppressed, and the manufacturing becomes easy. In addition, the slit 60 is provided at the end portion 30a of the laminated body 30, and the transistor 20a is disposed in the region directly under the slit 60, whereby the transistor 20a such as the gate electrode 25, the contact 27 and the lower layer wiring 28 can be avoided. The upper structure and the subsidiary structure interfere with the electrode film 32 on the lower layer side. In addition, since the area where the contacts 41 are arranged is separated from the area where the contacts 42 are arranged, the arrangement of the contacts 41 and 42 and the routing of the upper word line 43 are facilitated. The configurations and effects of the present embodiment other than those described above are the same as those of the second embodiment described above. (Fourth Embodiment) Next, a fourth embodiment will be described. FIG. 12 is a plan view showing the semiconductor memory device of the present embodiment. As shown in FIG. 12 , in the semiconductor memory device 4 of the present embodiment, a plurality of word lines WL arranged along the Y direction are connected to the diffusion region 22 of one transistor 20 . For example, two contacts 41 connected to two adjacent word lines WL in the Y direction and one contact 42 connected to the diffusion region 22 of one transistor 20 are connected to one upper word line 43 . According to this embodiment, the number of transistors 20 can be reduced. The configurations and effects of the present embodiment other than those described above are the same as those of the first embodiment described above. (Fifth Embodiment) Next, a fifth embodiment will be described. FIG. 13 is a plan view showing the laminate of the semiconductor memory device of the present embodiment. FIG. 14 is a plan view showing the semiconductor substrate of the semiconductor memory device of the present embodiment. FIG. 15 is a cross-sectional view showing the semiconductor memory device of the present embodiment. As shown in FIGS. 13 to 15 , in the semiconductor memory device 5 of the present embodiment, the transistors 20 of one memory block are arranged in plural rows not only along the X direction but also along the Y direction. Further, the diffusion region 22 of one transistor 20 is connected to a plurality of, for example, four electrode films 32 . The contacts 42 are arranged in the region R2 and are aligned in the X direction. In this embodiment, the length L1 of the step surface 33 a in the X direction is shorter than the minimum arrangement period P of the transistor 20 , and the length L2 of the step surface 33 b is longer than the minimum arrangement period P of the transistor 20 . That is, L1<P<L2 holds. Hereinafter, the configuration of the semiconductor memory device 5 will be described in detail. In the semiconductor memory device 5, 13 layers of electrode films 32 arranged along the Z direction are provided. These electrode films 32 are formed as electrode films 32c to 32o in this order from the lower layer side. Among them, the electrode film 32c of the lowermost layer is the source side selective gate SGS. In one memory block, four electrode films 32c are arranged along the Y direction and are connected to the same transistor 20 . The second electrode film 32d from the lowermost layer to the second electrode film 32n from the uppermost layer is the word line WL. In one memory block, four electrode films 32 d to 32 n are arranged along the Y direction, and are connected to the same transistor 20 . The uppermost electrode film 32o is the drain side selective gate SGD. In one memory block, eight electrode films 32 o are arranged along the Y direction, and are connected to different transistors 20 . Furthermore, the eight electrode films 32o belonging to one memory block are referred to as electrode films 32o1 to 32o8. The arrangement period of the drain side selection gate SGD in the Y direction is half the arrangement period of the word line WL. Therefore, two drain side selection gates SGD are arranged in the region just above one of the word lines WL. Twenty transistors 20 are provided in the semiconductor memory device 5 . These transistors 20 are referred to as transistors 20c to 20v. In addition, the diffusion region 22 of the transistor 20c is referred to as the diffusion region 22c. Furthermore, among the contacts 27 , lower wiring 28 , contacts 42 , upper word lines 43 , and contacts 41 that are connected to the transistor 20 c are referred to as contacts 27 c , lower wiring 28 c , contacts 42 c , and upper word lines, respectively 43c, contact 41c. The same applies to transistors 20d to 20v. The diffusion region 22c of the transistor 20c is led out substantially directly above by the contact 27c, the lower layer wiring 28c, and the contact 42c, and is led out in the Y direction by the upper word line 43c, which is half-circular in a U shape, and passes through four contacts. The point 41c is connected to the four electrode films 32c (source side selection gate SGS). When viewed from the transistor 20c, the transistor 20d is arranged on the Y direction side. The diffusion region 22d of the transistor 20d is led out to the region just above the diffusion region 22c by the lower layer wiring 28d, and is led out directly above by the contact 42d, and the upper word line 43d is used to surround the outer half circumference of the upper word line 43c through 4. Each of the contacts 41d is connected to the four electrode films 32d (word lines WL). When viewed from the transistor 20d, the transistor 20e is arranged on the X-direction side. The diffusion region 22e of the transistor 20e is led out to the region just above the diffusion region 22f by the lower layer wiring 28e, and is led out directly above by the contact 42e, and the upper word line 43e is used to make a half circle in the opposite direction of the upper word line 43d. It is connected to four electrode films 32e (word lines WL) via four contacts 41e. When viewed from the transistor 20e, the transistor 20f is arranged on the Y direction side. The diffusion region 22f of the transistor 20f is drawn substantially directly upward by the contact 27f, the lower layer wiring 28f, and the contact 42f, and is connected by four contacts 41f around the inner half circumference of the upper word line 43e by the upper word line 43f On four electrode films 32f (word lines WL). In this way, the transistors 20c to 20f are connected to the four electrode films 32c to 32f, respectively. Further, the diffusion regions 23 of the transistors 20c to 20f are connected to the lower layer wirings 39, respectively. The lower layer wiring 39 extends substantially in the Y direction. The position in the Z direction of the lower layer wiring 39 is the same as the position in the Z direction of the lower layer wiring 28 . The lower layer wiring 39 may use its trunk portion as the upper layer wiring, and in this case, the lower layer wiring 39 is connected to the upper layer wiring which becomes the trunk portion through an additional contact. The transistors 20g to 20j are connected to the four electrode films 32g to 32j, respectively, using the same half-circumferential wiring pattern as the current path from the transistors 20c to 20f to the electrode films 32c to 32f. In addition, the transistors 20k to 20n are connected to the four electrode films 32k to 32n, respectively, by using the same half-circumferential wiring pattern. The diffusion region 22o of the transistor 20o is drawn out to approximately directly above by the contact 27o, the lower layer wiring 28o, and the contact 42o. After being drawn out in the Y direction by the upper layer word line 43o, it is drawn out in the X direction, and passes through one contact 41o. It is connected to one electrode film 32o2 (drain side selection gate SGD). The upper word line 43o is L-shaped when viewed from the Z direction. The diffusion region 22p of the transistor 20p is led out to the area just above the diffusion region 22o by the lower layer wiring 28p, is led out directly above the diffusion region 22o by the contact 42p, and is led out of the upper layer word line 43o in an L shape by the upper layer word line 43p , and is connected to one electrode film 32o1 (drain side selection gate SGD) via one contact 41p. The diffusion region 22q of the transistor 20q is connected to the electrode film 32o4, and the diffusion region 22r of the transistor 20r is connected to the electrode film by the same L-shaped wiring pattern as the current path from the transistors 20o and 20p to the electrode films 32o2 and 32o1 32o3. Using the same L-shaped wiring pattern, the diffusion region 22s of the transistor 20s is connected to the electrode film 32o7, and the diffusion region 22t of the transistor 20t is connected to the electrode film 32o8. Further, the diffusion region 22u of the transistor 20u is connected to the electrode film 32o5, and the diffusion region 22v of the transistor 20v is connected to the electrode film 32o6. Next, the effect of this embodiment is demonstrated. In this embodiment, the transistors 20 are arranged not only in the X direction but also in the Y direction, so that the arrangement region of the transistors 20 and the length in the X direction of the end portion 30 a of the laminate 30 can be shortened. The configurations and effects of the present embodiment other than those described above are the same as those of the first embodiment described above. (Sixth Embodiment) Next, a sixth embodiment will be described. FIG. 16 is a plan view showing the laminate of the semiconductor memory device of the present embodiment. FIG. 17 is a plan view showing the semiconductor substrate of the semiconductor memory device of the present embodiment. FIG. 18 is a cross-sectional view showing the semiconductor memory device of the present embodiment. As shown in FIGS. 16 to 18 , in the semiconductor memory device 6 of the present embodiment, the step of the end portion 30 a is formed not only along the X direction but also along the Y direction. The steps along the X direction are formed across all the electrode films 32 arranged along the Z direction, and one step is formed on each of the two electrode films 32 . The step along the Y direction is formed corresponding to only one electrode film 32 , and one step is formed with respect to the one electrode film 32 . That is, when the number of electrode films 32 arranged in the Z direction in the laminate 30 is n, each of the two electrode films 32 has (n/2) steps along the X direction. In the Y direction, only one step corresponding to one electrode film 32 is formed. As a result, a stepped surface can be formed on the entire n-piece electrode film 32 . When viewing the entire end portion 30a, the shape of the region H in which the stepped surface is arranged one step higher than the adjacent stepped surface in the Y direction is comb-like when viewed in the Z direction. In addition, in the semiconductor memory device 6 , a plurality of word lines WL arranged in the Y direction are drawn alternately every two on both sides in the X direction of the laminate 30 . That is, when a plurality of word lines WL arranged in the Y direction are defined as word line WL_A, word line WL_A, word line WL_B, word line WL_B, word line WL_A, word line WL_A, . . . At the end portion 30a shown in FIGS. 16 to 18, the contact 41 is connected only to the word line WL_A. On the other hand, at the end portion 30a (not shown) on the opposite side, the contact 41 is connected to the word line WL_B. In addition, in the semiconductor memory device 6, the transistors 20 are arranged not only in the X direction but also in the Y direction, as in the semiconductor memory device 5 according to the fifth embodiment (see FIGS. 13 to 15 ). In addition, the diffusion region 22 of one transistor 20 is connected to, for example, two electrode films 32 . Moreover, in the end part 30a shown in FIGS. 16-18, the contact 41 is arrange|positioned in the area|region just above the word line WL_A. On the other hand, the contact 42 is arranged at a position where the word line WL_B is penetrated. Therefore, the upper-layer word line 43 extends from the area just above the word line WL_A to the area just above the word line WL_B. Therefore, a portion extending in the Y direction exists in the upper word line 43 . The contacts 42 are aligned along the X direction. The source side selection gates SGS are also drawn alternately every two on both sides of the laminate 30 in the X direction, similarly to the word lines WL. The drain-side selective gates SGD are alternately drawn out every four on both sides of the multilayer body 30 in the X direction. Next, the effect of this embodiment is demonstrated. In this embodiment, in addition to the main step along the X direction, the end portion 30a of the layered body 30 is also formed with a sub step along the Y direction. As a result, the length in the X direction of the end portion 30a can be shortened. In addition, in the present embodiment, the electrode films 32 are drawn out alternately on both sides in the X direction of the laminate 30 . Thereby, compared with the case where the electrode film 32 is drawn out to one side in the X direction, the number of transistors 20 formed in the region immediately below the one side end portion 30a can be reduced to half. As a result, the layout of the upper word lines 43 and the like can be easily prepared. Furthermore, in this embodiment, the contact 41 is arranged in the region just above the word line WL_A, and the contact 42 is arranged in the arrangement region of the word line WL_B. As a result, the wiring can be routed by effectively utilizing the arrangement area of the word line WL_B, which is originally an invalid space. The configuration and effects of the present embodiment other than those described above are the same as those of the above-described first embodiment. (Seventh Embodiment) Next, a seventh embodiment will be described. FIG. 19 is a plan view showing the laminate of the semiconductor memory device of the present embodiment. FIG. 20 is a plan view showing the semiconductor substrate of the semiconductor memory device of the present embodiment. FIG. 21 is a cross-sectional view showing the semiconductor memory device of the present embodiment. As shown in FIGS. 19 to 21 , the semiconductor memory device 7 of this embodiment is compared with the semiconductor memory device 6 of the sixth embodiment (see FIGS. 16 to 18 ) in that the shape of the region H is island-like. different. As mentioned above, the area|region H is arrange|positioned in the area|region in which the step surface higher than the adjacent step surface in the Y direction is 1 stage. Therefore, in this embodiment, compared with the sixth embodiment, the electrode films 32 connected between the adjacent transistors 20 in the Y direction are opposite to each other. Moreover, in the direction from the center part 30b of the laminated body 30 toward the edge part 30a, the edge of the center part 30b side of the area|region H is the step US which rises one step. However, the step US is a shape created for processing reasons, and the electrode film 32 having the step US as an end face is isolated from the electrode film that actually functions and is insulated and does not function electrically. As with the other embodiments, the electrode film that actually functions does not rise in the middle, but descends stepwise in the direction from the intermediate portion 30b to the end portion 30a. The steps arranged in the Y direction may be formed in a plurality of stages similarly to the steps arranged in the X direction. In the present embodiment, the word line WL and the drain side selection gate SGD arranged in the Y direction can be formed in the same step, so that the number of steps can be reduced. The configurations and effects of the present embodiment other than those described above are the same as those of the sixth embodiment described above. (Eighth Embodiment) Next, an eighth embodiment will be described. FIG. 22 is a plan view showing the laminate of the semiconductor memory device of the present embodiment. FIG. 23 is a plan view showing the semiconductor substrate of the semiconductor memory device of the present embodiment. FIG. 24 is a cross-sectional view showing the semiconductor memory device of the present embodiment. As shown in FIGS. 22 to 24 , the semiconductor memory device 8 of this embodiment differs from the semiconductor memory device 6 of the seventh embodiment (see FIGS. 19 to 21 ) in the arrangement of the contacts 41 and 42 . In the semiconductor memory device 8, with respect to each source side select gate SGS and word line WL, two contacts 41 connected to two levels arranged along the Y direction are connected to these via the upper word line 43. The two contacts 42 of the contacts 41 are arranged in a row along the Y direction. That is, in the X direction, the positions of the two contacts 41 and the positions of the two contacts 42 are equal to each other. Regarding the drain side selection gate SGD, the four contacts 41 connected to the two steps arranged in the Y direction are arranged in a row along the Y direction, and the four contacts 42 connected to the four contacts 41 are also line up in the Y direction. That is, the positions of the four contacts 41 in the X direction are equal to each other, and the positions of the four contacts 42 are also equal to each other. However, in the X direction, the position of the contact 41 and the position of the contact 42 are different from each other. The configurations and effects of the present embodiment other than those described above are the same as those of the seventh embodiment described above. (Ninth Embodiment) Next, a ninth embodiment will be described. FIG. 25 is a plan view showing a wafer on which transistors are formed in the semiconductor memory device of the present embodiment. FIG. 26 is a plan view showing a wafer on which a laminated body is formed in the semiconductor memory device of the present embodiment. FIG. 27 is a cross-sectional view showing the semiconductor memory device of the present embodiment. As shown in FIGS. 25 to 27 , in the semiconductor memory device 9 of the present embodiment, two chips 101 and 102 are bonded together via bumps 103 . The laminated body 30 is provided in the wafer 101 . Transistor 20 is formed in wafer 102 . Furthermore, the electrode film 32 provided on the wafer 101 is connected to the transistor 20 formed on the wafer 102 via the bumps 103 . In the semiconductor memory device 9, the chip 102 shown in FIG. 25 and the chip 101 shown in FIG. 26 are bonded together in such a manner that their respective upper surfaces face each other. 27 shows a cross section including the center of the bump 103, but for convenience of description, the lower layer wiring 28 and the contact 42 are also shown. Hereinafter, it demonstrates in more detail. In the wafer 101 , for example, a semiconductor substrate 11 containing silicon is provided, a laminate 30 is provided on the semiconductor substrate 11 , and an interlayer insulating film 40 is provided so as to cover the laminate 30 . However, the transistor 20 is not formed on the semiconductor substrate 11, and the source line 29 is not provided between the semiconductor substrate 11 and the laminate 30 (see FIG. 24). Further, contacts 41 are provided on the stepped surfaces of the electrode films 32 of the laminate 30 , and upper word lines 43 are provided on the contacts 41 , and the upper ends of the contacts 41 are connected to the upper word lines 43 . However, the contacts 42 are not provided (refer to FIG. 24 ). A pad 64 is disposed on the upper layer portion of the interlayer insulating film 40 and is exposed on the upper surface of the interlayer insulating film 40 . The pads 64 are formed of copper, for example. Contacts 63 are connected between upper-layer word lines 43 and pads 64 . In the present embodiment, as in the sixth embodiment described above (see FIGS. 16 to 18 ), the electrode films 32 are drawn out to both sides in the X direction of the laminate 30 . That is, the plurality of source side selection gates SGS and the plurality of word lines WL arranged in the Y direction are alternately drawn out every two on both sides of the multilayer body 30 in the X direction. In addition, a plurality of drain-side selective gates SGD arranged in the Y direction are alternately drawn out every four on both sides of the laminated body 30 in the X direction. Furthermore, the two adjacent source side select gates SGS in the Y direction are connected to the common upper-layer word line 43 via the contact 41 , and are connected to one pad 64 via one contact 63 . In addition, two adjacent word lines WL in the Y direction are connected to the common upper word line 43 via the contact 41 , and are connected to one pad 64 via one contact 63 . However, the word lines WL whose positions in the Z direction are different from each other are connected to the upper layer word lines 43 which are different from each other. Furthermore, the four drain-side selective gates SGD arranged along the Y direction are connected to different pads 64 via the contact 41 , the upper word line 43 , and the contact 63 . In this way, each electrode film 32 is connected to any one of the pads 64 via the contact 41 , the upper word line 43 and the contact 63 . On the other hand, in the wafer 102 , for example, a semiconductor substrate 12 containing silicon is provided, and an interlayer insulating film 66 is provided on the semiconductor substrate 12 . The transistors 20 are formed in the upper layer portion of the semiconductor substrate 12 and in the interlayer insulating film 66, and are arranged in a matrix along the X direction and the Y direction. The structure of the transistor 20 is the same as that of the first embodiment described above. A pad 67 is provided on the upper layer portion of the interlayer insulating film 66 . The pads 67 are formed of copper, for example. The contact 42 is connected between the pad 67 and the lower layer wiring 28 . In this way, the diffusion region 22 of each transistor 20 is connected to any pad 67 via the contact 27 , the lower layer wiring 28 and the contact 42 . The chip 101 and the chip 102 are disposed in such a manner that the bonding pads 64 and the bonding pads 67 face each other, and the bumps 103 are joined between the bonding pads 64 and the bonding pads 67 . The bumps 103 are bumps made of conductive material, for example, solder balls. Using bumps 103 , pads 64 are electrically connected to pads 67 , and die 101 is mechanically coupled to die 102 . Thus, the electrode film 32 of the chip 101 is connected to the diffusion region 22 of the transistor 20 of the chip 102 . In the X direction, when the minimum arrangement period of the pads 64 is set to P1 and the minimum arrangement period of the transistor 20 is set to P2, the length of the step surface T in the X direction is set to be larger from either the period P1 or the period P2 The period P=MAX(P1, P2) is determined. The length L1 of the step surface 33a arranged in the region R1 is shorter than the period P. As shown in FIG. In addition, the length L2 of the step surface 33b arranged in the region R2 is longer than the period P. As shown in FIG. That is, L1<P<L2. Next, the effect of this embodiment is demonstrated. In this embodiment, two wafers 101 and 102 are provided, the laminate 30 is formed on the wafer 101 , and the transistor 20 is formed on the wafer 102 . Thereby, compared with the case where both the transistor 20 and the laminated body 30 are formed on a single wafer, the manufacturing is easy and the manufacturing cost is low. In addition, since there is no need to provide the contacts 42 in the wafer 101, the layout of the upper-layer word lines 43 can be simplified. Accordingly, the layout of the upper-layer word lines 43 can be easily fabricated, and the reduction of the operation speed, the increase of the power consumption, and the reduction of the reliability accompanying the miniaturization of the wiring can be suppressed. The configurations and effects of the present embodiment other than those described above are the same as those of the first embodiment described above. (First modification of the ninth embodiment) Next, a first modification of the ninth embodiment will be described. FIG. 28 is a plan view showing a wafer on which transistors are formed in the semiconductor memory device of the present modification. FIG. 29 is a plan view showing a wafer on which a laminated body is formed in the semiconductor memory device of the present modification. FIG. 30 is a cross-sectional view showing a semiconductor memory device of this modification. As shown in FIGS. 28 to 30 , in the semiconductor memory device 9 a of the present modification, the chip 101 and the chip 102 are bonded by the conductive pillars 104 . The pillar 104 is formed, for example, of copper, and its shape is, for example, cylindrical. The structures of the wafer 101 and the wafer 102 are the same as those of the ninth embodiment described above. The configuration and effects other than the above in this modification example are the same as those of the ninth embodiment described above. (Second modification of the ninth embodiment) Next, a second modification of the ninth embodiment will be described. FIG. 31 is a plan view showing a wafer on which transistors are formed in the semiconductor memory device of the present modification. FIG. 32 is a plan view showing a wafer on which a laminated body is formed in the semiconductor memory device of the present modification. FIG. 33 is a cross-sectional view showing a semiconductor memory device of this modification. As shown in FIGS. 31 to 33 , in the semiconductor memory device 9b of the present modification, the wafer 101 and the wafer 102 are directly bonded to each other. For example, the chip 101 is bonded to the chip 102 by adhesive or mechanical means, and the bonding pads 64 of the chip 101 are in contact with the bonding pads 67 of the chip 102 . The bonding pads 64 and the bonding pads 67 may also be bonded with a conductive adhesive. The structures of the wafer 101 and the wafer 102 are the same as those of the ninth embodiment described above. The configuration and effects other than the above in this modification example are the same as those of the ninth embodiment described above. According to the above-described embodiment and its modifications, a semiconductor memory device with easy wiring layout can be realized. Furthermore, in the first, third, fourth, ninth embodiments, and the first and second modified examples of the ninth embodiment, a step may be formed along the Y direction at the end portion 30a of the layered body 30 . Several embodiments of the present invention and their modifications have been described above, but these embodiments and modifications are presented as examples and are not intended to limit the scope of the invention. These novel embodiments and modified examples can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or changes thereof are included in the scope or spirit of the invention, and are included in the scope of the invention described in the scope of the patent application and its equivalents. In addition, the above-described embodiments and modifications may be implemented in combination with each other. [Related Applications] This application is entitled to U.S. Provisional Patent Application No. 62/374,034 (application date: August 12, 2016) and Japanese Patent Application No. 2017-16330 (application date: January 31, 2017) The priority of the basic application. This application contains the entire contents of the basic application by reference to these basic applications.

1‧‧‧半導體記憶裝置2‧‧‧半導體記憶裝置3‧‧‧半導體記憶裝置4‧‧‧半導體記憶裝置5‧‧‧半導體記憶裝置6‧‧‧半導體記憶裝置7‧‧‧半導體記憶裝置8‧‧‧半導體記憶裝置9‧‧‧半導體記憶裝置9a‧‧‧半導體記憶裝置9b‧‧‧半導體記憶裝置10‧‧‧半導體基板11‧‧‧半導體基板12‧‧‧半導體基板10a‧‧‧上表面20‧‧‧電晶體20a‧‧‧電晶體20c~20v‧‧‧電晶體21‧‧‧阱21a‧‧‧主體區域22‧‧‧擴散區域22c~22v‧‧‧擴散區域23‧‧‧擴散區域24‧‧‧閘極絕緣膜25‧‧‧閘極電極26‧‧‧STI27‧‧‧觸點27c~27v‧‧‧觸點28‧‧‧下層配線28c~28v‧‧‧下層配線29‧‧‧源極線30‧‧‧積層體30a‧‧‧端部30b‧‧‧中央部31‧‧‧絕緣膜32‧‧‧電極膜32c~32n‧‧‧電極膜32o1~32o8‧‧‧電極膜33a‧‧‧階面33b‧‧‧階面39‧‧‧下層配線40‧‧‧層間絕緣膜41‧‧‧觸點41c~41v‧‧‧觸點42‧‧‧觸點42c~42v‧‧‧觸點43‧‧‧上層字元線43c~43v‧‧‧上層字元線44‧‧‧絕緣膜46‧‧‧穿孔觸點47‧‧‧位元線48‧‧‧觸點49‧‧‧上層源極線50‧‧‧矽柱51‧‧‧芯構件52‧‧‧穿隧絕緣膜53‧‧‧電荷累積膜54‧‧‧阻擋絕緣膜54a‧‧‧氧化鋁層54b‧‧‧氧化矽層54c‧‧‧氧化鋁層55‧‧‧記憶膜56‧‧‧浮動閘極電極60‧‧‧狹縫63‧‧‧觸點64‧‧‧焊墊66‧‧‧層間絕緣膜67‧‧‧焊墊101‧‧‧晶片102‧‧‧晶片103‧‧‧凸塊104‧‧‧柱A‧‧‧區域D‧‧‧區域H‧‧‧區域L1‧‧‧長度L2‧‧‧長度MC‧‧‧記憶單元電晶體P‧‧‧最小排列週期R1‧‧‧區域R2‧‧‧區域SGD‧‧‧汲極側選擇閘極SGS‧‧‧源極側選擇閘極US‧‧‧台階WL‧‧‧字元線WL_A‧‧‧字元線WL_B‧‧‧字元線X、Y、Z‧‧‧方向1‧‧‧Semiconductor Memory Device 2‧‧‧Semiconductor Memory Device 3‧‧‧Semiconductor Memory Device 4‧‧‧Semiconductor Memory Device 5‧‧‧Semiconductor Memory Device 6‧‧‧Semiconductor Memory Device 7‧‧‧Semiconductor Memory Device 8 ‧‧‧Semiconductor memory device 9‧‧‧Semiconductor memory device 9a‧‧‧Semiconductor memory device 9b‧‧‧Semiconductor memory device 10‧‧‧Semiconductor substrate 11‧‧‧Semiconductor substrate 12‧‧‧Semiconductor substrate 10a‧‧‧ Surface 20‧‧‧Transistor 20a‧‧‧Transistor 20c~20v‧‧‧Transistor 21‧‧‧Well 21a‧‧‧Main region 22‧‧‧Diffusion region 22c~22v‧‧‧Diffusion region 23‧‧‧ Diffusion region 24‧‧‧Gate insulating film 25‧‧‧Gate electrode 26‧‧‧STI27‧‧‧Contact 27c~27v‧‧‧Contact 28‧‧‧Lower layer wiring 28c~28v‧‧‧Lower layer wiring 29 ‧‧‧Source line 30‧‧‧Laminated body 30a‧‧‧End part 30b‧‧‧Central part 31‧‧‧Insulating film 32‧‧‧Electrode film 32c~32n‧‧‧Electrode film 32o1~32o8‧‧‧ Electrode film 33a‧‧‧Step surface 33b‧‧‧Step surface 39‧‧‧Lower layer wiring 40‧‧‧Interlayer insulating film 41‧‧‧Contacts 41c to 41v ‧‧‧Contacts 43‧‧‧Upper word lines 43c~43v‧‧‧Upper word lines 44‧‧‧Insulating film 46‧‧‧Through-hole contacts 47‧‧‧Bit lines 48‧‧‧Contact 49 ‧‧‧Upper layer source line 50‧‧‧Silicon pillar 51‧‧‧Core member 52‧‧‧Tunnel insulating film 53‧‧‧Charge accumulation film 54‧‧‧Block insulating film 54a‧‧‧Alumina oxide layer 54b‧ ‧‧Silicon oxide layer 54c‧‧‧Aluminum oxide layer 55‧‧‧Memory film 56‧‧‧Floating gate electrode 60‧‧‧Slit 63‧‧‧Contact 64‧‧‧Pad 66‧‧‧Interlayer insulation Film 67‧‧‧Pad 101‧‧‧Chip 102‧‧‧Chip 103‧‧‧Bump 104‧‧‧Pillar A‧‧‧Region D‧‧‧Region H‧‧‧Region L1‧‧‧Length L2‧ ‧‧Length MC‧‧‧Memory Cell Transistor P‧‧‧Minimum Arrangement Period R1‧‧‧Region R2‧‧‧Region SGD‧‧‧Drain Side Select Gate SGS‧‧‧Source Side Select Gate US‧ ‧‧Step WL‧‧‧Word Line WL_A‧‧‧Word Line WL_B‧‧‧Word Line X, Y, Z‧‧‧ Direction

圖1係表示第1實施形態之半導體記憶裝置之剖視圖。 圖2係表示第1實施形態之半導體記憶裝置之配線部之俯視圖。 圖3係表示第1實施形態之半導體記憶裝置之基板面之俯視圖。 圖4係表示圖1之區域A之局部放大剖視圖。 圖5係表示第2實施形態之半導體記憶裝置之俯視圖。 圖6係圖5所示之B-B'線處之剖視圖。 圖7係圖5所示之C-C'線處之剖視圖。 圖8係表示圖6之區域D之局部放大剖視圖。 圖9係表示第3實施形態之半導體記憶裝置之俯視圖。 圖10係圖9所示之E-E'線處之剖視圖。 圖11係圖9所示之F-F'線處之剖視圖。 圖12係表示第4實施形態之半導體記憶裝置之俯視圖。 圖13係表示第5實施形態之半導體記憶裝置之積層體之俯視圖。 圖14係表示第5實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖15係表示第5實施形態之半導體記憶裝置之剖視圖。 圖16係表示第6實施形態之半導體記憶裝置之積層體之俯視圖。 圖17係表示第6實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖18係表示第6實施形態之半導體記憶裝置之剖視圖。 圖19係表示第7實施形態之半導體記憶裝置之積層體之俯視圖。 圖20係表示第7實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖21係表示第7實施形態之半導體記憶裝置之剖視圖。 圖22係表示第8實施形態之半導體記憶裝置之積層體之俯視圖。 圖23係表示第8實施形態之半導體記憶裝置之半導體基板之俯視圖。 圖24係表示第8實施形態之半導體記憶裝置之剖視圖。 圖25係表示第9實施形態之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖26係表示第9實施形態之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖27係表示第9實施形態之半導體記憶裝置之剖視圖。 圖28係表示第9實施形態之第1變化例之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖29係表示第9實施形態之第1變化例之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖30係表示第9實施形態之第1變化例之半導體記憶裝置之剖視圖。 圖31係表示第9實施形態之第2變化例之半導體記憶裝置中之形成有電晶體之晶片之俯視圖。 圖32係表示第9實施形態之第2變化例之半導體記憶裝置中之形成有積層體之晶片之俯視圖。 圖33係表示第9實施形態之第2變化例之半導體記憶裝置之剖視圖。FIG. 1 is a cross-sectional view showing a semiconductor memory device according to the first embodiment. FIG. 2 is a plan view showing a wiring portion of the semiconductor memory device according to the first embodiment. FIG. 3 is a plan view showing the substrate surface of the semiconductor memory device of the first embodiment. FIG. 4 is a partially enlarged cross-sectional view showing a region A of FIG. 1 . FIG. 5 is a plan view showing the semiconductor memory device of the second embodiment. FIG. 6 is a cross-sectional view taken along line BB' shown in FIG. 5 . FIG. 7 is a cross-sectional view taken along the line CC' shown in FIG. 5 . FIG. 8 is a partial enlarged cross-sectional view showing a region D of FIG. 6 . FIG. 9 is a plan view showing the semiconductor memory device of the third embodiment. FIG. 10 is a cross-sectional view taken along the line EE' shown in FIG. 9 . FIG. 11 is a cross-sectional view taken along the line FF' shown in FIG. 9 . FIG. 12 is a plan view showing the semiconductor memory device of the fourth embodiment. FIG. 13 is a plan view showing a laminate of a semiconductor memory device according to a fifth embodiment. FIG. 14 is a plan view showing the semiconductor substrate of the semiconductor memory device of the fifth embodiment. FIG. 15 is a cross-sectional view showing a semiconductor memory device according to a fifth embodiment. FIG. 16 is a plan view showing the laminate of the semiconductor memory device according to the sixth embodiment. FIG. 17 is a plan view showing the semiconductor substrate of the semiconductor memory device of the sixth embodiment. FIG. 18 is a cross-sectional view showing a semiconductor memory device according to a sixth embodiment. FIG. 19 is a plan view showing a laminate of a semiconductor memory device according to a seventh embodiment. FIG. 20 is a plan view showing the semiconductor substrate of the semiconductor memory device of the seventh embodiment. FIG. 21 is a cross-sectional view showing a semiconductor memory device according to a seventh embodiment. FIG. 22 is a plan view showing the laminate of the semiconductor memory device according to the eighth embodiment. FIG. 23 is a plan view showing the semiconductor substrate of the semiconductor memory device of the eighth embodiment. FIG. 24 is a cross-sectional view showing a semiconductor memory device according to the eighth embodiment. FIG. 25 is a plan view showing a wafer on which transistors are formed in the semiconductor memory device of the ninth embodiment. FIG. 26 is a plan view showing a wafer on which a laminated body is formed in the semiconductor memory device of the ninth embodiment. FIG. 27 is a cross-sectional view showing a semiconductor memory device according to the ninth embodiment. FIG. 28 is a plan view showing a wafer on which transistors are formed in a semiconductor memory device according to a first modification of the ninth embodiment. FIG. 29 is a plan view showing a wafer on which a laminated body is formed in a semiconductor memory device according to a first modification of the ninth embodiment. 30 is a cross-sectional view showing a semiconductor memory device according to a first modification of the ninth embodiment. FIG. 31 is a plan view showing a wafer on which transistors are formed in a semiconductor memory device according to a second modification of the ninth embodiment. 32 is a plan view showing a wafer on which a laminate is formed in a semiconductor memory device according to a second modification of the ninth embodiment. 33 is a cross-sectional view of a semiconductor memory device showing a second modification of the ninth embodiment.

1‧‧‧半導體記憶裝置 1‧‧‧Semiconductor memory device

29‧‧‧源極線 29‧‧‧Source line

30a‧‧‧端部 30a‧‧‧End

30b‧‧‧中央部 30b‧‧‧Central

32‧‧‧電極膜 32‧‧‧Electrode film

33a‧‧‧階面 33a‧‧‧Steps

33b‧‧‧階面 33b‧‧‧Steps

41‧‧‧觸點 41‧‧‧Contact

42‧‧‧觸點 42‧‧‧contacts

43‧‧‧上層字元線 43‧‧‧Upper word line

44‧‧‧絕緣膜 44‧‧‧Insulating film

47‧‧‧位元線 47‧‧‧bit line

50‧‧‧矽柱 50‧‧‧Silicon pillar

L1‧‧‧長度 L1‧‧‧Length

L2‧‧‧長度 L2‧‧‧Length

R1‧‧‧區域 R1‧‧‧area

R2‧‧‧區域 R2‧‧‧area

SGD‧‧‧汲極側選擇閘極 SGD‧‧‧Drain Side Selected Gate

SGS‧‧‧源極側選擇閘極 SGS‧‧‧Source Side Select Gate

WL‧‧‧字元線 WL‧‧‧ character line

X、Y、Z‧‧‧方向 X, Y, Z‧‧‧ directions

Claims (16)

一種半導體記憶裝置,其包括:第1晶片;及第2晶片;上述第1晶片包括:第1半導體基板,其具有於第1方向及第2方向延伸之第1主面,上述第2方向與上述第1方向交叉;積層體,其設置於上述第1半導體基板上,具有沿著第3方向相互隔開而積層之複數片電極膜,上述第3方向與上述第1方向及第2方向交叉;半導體構件,其於上述第3方向貫通上述複數片電極膜;電荷累積構件,其設置於上述半導體構件與上述複數片電極膜之一片之間;第1焊墊;及第1觸點,其將上述複數片電極膜之一片連接於上述第1焊墊;上述第2晶片包括:第2半導體基板,其具有於上述第1方向及上述第2方向延伸之第2主面;複數個電晶體,其形成於上述第2主面;第2焊墊;及第2觸點,其將上述電晶體之一者之源極、汲極之一者連接於上述第2焊墊;且 上述第1晶片與上述第2晶片係以上述第1焊墊連接於上述第2焊墊之方式相互對向;上述積層體之上述第1方向之端部之形狀係具有複數個階面之階梯狀,上述複數個階面之各者形成於上述電極膜之各者,且上述複數個階面包括複數個第1階面及第2階面,於上述端部,沿著上述第1方向設定有兩個第1區域及配置於上述兩個第1區域間之第2區域,於各上述第1區域配置有上述複數個第1階面,於上述第2區域配置有上述第2階面,上述第2階面之上述第1方向上之長度,較上述第1焊墊之上述第1方向上之最小週期與上述複數個電晶體之上述第1方向上之最小週期中的較大之週期更長,配置於上述第1區域之上述複數個第1階面之一者之上述第1方向上之長度較上述較大之週期更短。 A semiconductor memory device, comprising: a first chip; and a second chip; the first chip includes: a first semiconductor substrate having a first main surface extending in a first direction and a second direction, the second direction and The first direction intersects; the layered body is provided on the first semiconductor substrate and has a plurality of electrode films that are spaced apart and laminated along a third direction, the third direction intersecting the first and second directions a semiconductor member that penetrates through the plurality of electrode films in the third direction; a charge accumulation member disposed between the semiconductor member and one of the plurality of electrode films; a first pad; and a first contact, which One of the plurality of electrode films is connected to the first pad; the second wafer includes: a second semiconductor substrate having a second main surface extending in the first direction and the second direction; a plurality of transistors , which is formed on the second main surface; the second pad; and the second contact, which connects the source and drain of one of the transistors to the second pad; and The first chip and the second chip are opposed to each other in such a way that the first pad is connected to the second pad, and the shape of the end portion in the first direction of the layered body has a plurality of steps. In a shape, each of the plurality of stepped surfaces is formed on each of the electrode films, and the plurality of stepped surfaces includes a plurality of first stepped surfaces and a plurality of second stepped surfaces, and is set at the end portion along the first direction. There are two first regions and a second region arranged between the two first regions, the plurality of first step surfaces are arranged in each of the first regions, and the second step surfaces are arranged in the second region, The length of the second step surface in the first direction is greater than the period greater than the minimum period in the first direction of the first pad and the minimum period in the first direction of the plurality of transistors Longer, the length in the first direction of one of the plurality of first step surfaces arranged in the first region is shorter than the larger period. 如請求項1之半導體記憶裝置,其進而包括連接於上述第1焊墊與上述第2焊墊之間之凸塊。 The semiconductor memory device of claim 1, further comprising a bump connected between the first pad and the second pad. 如請求項1之半導體記憶裝置,其進而包括連接於上述第1焊墊與上述第2焊墊之間之導電性之柱。 The semiconductor memory device of claim 1, further comprising a conductive post connected between the first pad and the second pad. 如請求項1之半導體記憶裝置,其中上述第1焊墊與上述第2焊墊相接。 The semiconductor memory device of claim 1, wherein the first pad is connected to the second pad. 如請求項1之半導體記憶裝置,其中上述第1晶片進而包括連接於上述半導體構件之上述第3方向之一端且於上述第2方向延伸之位元線。 The semiconductor memory device of claim 1, wherein the first chip further comprises a bit line connected to one end of the semiconductor element in the third direction and extending in the second direction. 如請求項1之半導體記憶裝置,其中上述第1晶片進而包括形成為覆蓋上述第1半導體基板之上述第1主面之第1絕緣膜,上述第1焊墊露出於上述第1絕緣膜;上述第2晶片進而包括形成為覆蓋上述第2半導體基板之上述第2主面之第2絕緣膜,上述第2焊墊露出於上述第2絕緣膜。 The semiconductor memory device of claim 1, wherein the first wafer further includes a first insulating film formed to cover the first principal surface of the first semiconductor substrate, and the first pads are exposed on the first insulating film; the The second wafer further includes a second insulating film formed to cover the second principal surface of the second semiconductor substrate, and the second pad is exposed to the second insulating film. 如請求項1之半導體記憶裝置,其中於上述第1晶片,設置複數上述第1觸點對應於上述電極膜,設置複數上述第1焊墊對應於上述第1觸點;於上述第2晶片,設置複數上述第2觸點對應於上述電晶體,設置複數上述第2焊墊對應於上述第2觸點。 The semiconductor memory device of claim 1, wherein on the first wafer, a plurality of the first contacts are provided corresponding to the electrode films, and a plurality of the first pads are provided corresponding to the first contacts; and on the second wafer, The plurality of second contacts provided corresponds to the transistor, and the plurality of second pads provided corresponds to the second contacts. 如請求項7之半導體記憶裝置,其中於上述第3方向觀之,上述第1焊墊排列為矩陣狀;於上述第3方向觀之,上述第2焊墊排列為矩陣狀。 The semiconductor memory device of claim 7, wherein the first pads are arranged in a matrix when viewed from the third direction, and the second pads are arranged in a matrix when viewed from the third direction. 如請求項1之半導體記憶裝置,其中上述複數片電極膜之一片被分割為沿著上述第2方向排列之複數個帶狀部分, 上述第1觸點連接於上述複數個帶狀部分中之第1帶狀部分。 The semiconductor memory device of claim 1, wherein one of the plurality of electrode films is divided into a plurality of strip-shaped portions arranged along the second direction, The first contact is connected to the first strip portion of the plurality of strip portions. 如請求項1之半導體記憶裝置,其中上述積層體被分割為上述第2方向排列之複數個帶狀部分,於上述帶狀部分間形成有狹縫。 The semiconductor memory device according to claim 1, wherein the layered body is divided into a plurality of strip-shaped parts arranged in the second direction, and slits are formed between the strip-shaped parts. 如請求項1之半導體記憶裝置,其中上述複數個電晶體沿著上述第2方向排列。 The semiconductor memory device of claim 1, wherein the plurality of transistors are arranged along the second direction. 如請求項1之半導體記憶裝置,其中上述複數片電極膜之一片被分割為沿著上述第2方向排列之複數個帶狀部分,上述複數個帶狀部分連接於相同電晶體。 The semiconductor memory device of claim 1, wherein one of the plurality of electrode films is divided into a plurality of strip-shaped parts arranged along the second direction, and the plurality of strip-shaped parts are connected to the same transistor. 如請求項1之半導體記憶裝置,其中上述複數片電極膜之一片被分割為沿著上述第2方向排列之複數個帶狀部分,上述第1觸點連接於一部分之上述帶狀部分。 The semiconductor memory device of claim 1, wherein one of the plurality of electrode films is divided into a plurality of band-shaped portions arranged along the second direction, and the first contact is connected to a part of the band-shaped portions. 如請求項13之半導體記憶裝置,其中上述第1觸點連接於相鄰之複數條上述帶狀部分,不連接於相鄰之其他複數條上述帶狀部分。 The semiconductor memory device of claim 13, wherein the first contact is connected to the adjacent plurality of the above-mentioned strip-shaped portions, and is not connected to the adjacent plurality of the above-mentioned strip-shaped portions. 如請求項1之半導體記憶裝置,其中上述電荷累積構件包含矽及氮。 The semiconductor memory device of claim 1, wherein the charge accumulation member includes silicon and nitrogen. 如請求項1之半導體記憶裝置,其中上述電荷累積構件為導電性。 The semiconductor memory device of claim 1, wherein the charge accumulation member is conductive.
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