CN113097212A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113097212A CN113097212A CN202110342842.5A CN202110342842A CN113097212A CN 113097212 A CN113097212 A CN 113097212A CN 202110342842 A CN202110342842 A CN 202110342842A CN 113097212 A CN113097212 A CN 113097212A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 230
- 238000002955 isolation Methods 0.000 claims abstract description 115
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 239000004020 conductor Substances 0.000 claims abstract description 63
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 59
- 239000001257 hydrogen Substances 0.000 claims abstract description 59
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 57
- 238000003860 storage Methods 0.000 claims abstract description 37
- 238000003475 lamination Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 62
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 16
- 230000000149 penetrating effect Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 239000012212 insulator Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The semiconductor device comprises a substrate, a peripheral circuit and a storage unit, wherein the hydrogen element in the storage unit is higher than the hydrogen element in the peripheral circuit, the peripheral circuit and the storage unit are separated by an isolation layer, and the isolation layer comprises a lamination of a first dielectric layer, a conductor layer and a second dielectric layer.
Description
Technical Field
The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a semiconductor device and a manufacturing method thereof.
Background
In general, a memory device may be divided into a memory region in which a memory cell (cell) array storing data is disposed, and a peripheral region in which peripheral circuits (peri) related to data input/output are disposed.
In the existing 3D NAND, the peripheral region and the storage region have different requirements for hydrogen (H) element, the channel of the storage region needs to repair the defect by using H, while the peripheral region does not have such a requirement, and in the existing 3D NAND device, the peripheral region is easily contacted by H, which affects the performance.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which uses an isolation layer to isolate a peripheral circuit and a memory cell, thereby improving device performance.
An embodiment of the present application provides a semiconductor device, including:
a substrate, and peripheral circuits and memory cells on the substrate; the hydrogen element in the storage unit is higher than the hydrogen element in the peripheral circuit;
the peripheral circuit and the memory unit are separated by an isolation layer, and the isolation layer comprises a lamination layer of a first dielectric layer, a conductor layer and a second dielectric layer.
Optionally, the peripheral circuit is located between the memory cell and the substrate, and a silicon nitride layer is formed on the memory cell to provide a hydrogen source by using the silicon nitride layer; or the like, or, alternatively,
the storage unit is positioned between the peripheral circuit and the substrate, and a silicon nitride layer is also formed between the storage unit and the substrate so as to provide a hydrogen source by utilizing the silicon nitride layer; or the like, or, alternatively,
the substrate area where the peripheral circuit is located outside the substrate area where the storage unit is located, silicon nitride layers are formed on the peripheral circuit and the storage unit so as to provide hydrogen sources for the storage unit through the silicon nitride layers, and the isolation layer is further formed between the silicon nitride layers and the peripheral circuit.
Optionally, when the peripheral circuit is located between the memory cell and the substrate, the memory cell is formed over the peripheral circuit by bonding; when the memory cell is located between the peripheral circuit and the substrate, the peripheral circuit is formed over the memory cell by bonding.
Optionally, a through hole penetrating through the isolation layer is formed in the isolation layer above or below the peripheral circuit, a conductor plug and a third dielectric layer surrounding a sidewall of the conductor plug are formed in the through hole, and the conductor plug is used for connecting the peripheral circuit and the memory cell.
Optionally, the third dielectric layer is made of silicon oxide, and the conductor plug is made of tungsten.
Optionally, the first dielectric layer and the second dielectric layer are made of silicon oxide, and the conductor layer is made of titanium nitride.
The embodiment of the present application further provides a method for manufacturing a semiconductor device, including:
providing a substrate;
forming a peripheral circuit, a memory cell, and an isolation layer between the peripheral circuit and the memory cell on a substrate; the hydrogen element in the memory cell is higher than that in the peripheral circuit, and the isolation layer includes a stack of a first dielectric layer, a conductor layer, and a second dielectric layer.
Optionally, forming a peripheral circuit, a memory cell, and an isolation layer between the peripheral circuit and the memory cell on the substrate includes:
sequentially forming a peripheral circuit, an isolation layer on the peripheral circuit, a storage unit on the isolation layer and a silicon nitride layer on the storage unit on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
sequentially forming a silicon nitride layer, a storage unit on the silicon nitride layer, an isolation layer on the storage unit and a peripheral circuit on the isolation layer on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
forming a peripheral circuit, an isolation layer positioned on the side wall and the top of the peripheral circuit, a memory cell positioned in a substrate area outside the substrate area where the peripheral circuit is positioned, and a silicon nitride layer on the peripheral circuit and the memory cell on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
forming a memory cell, a first isolation part positioned on the side wall of the memory cell, a peripheral circuit positioned in a substrate area outside the substrate area where the memory cell is positioned, a second isolation part positioned on the top of the peripheral circuit, the peripheral circuit and a silicon nitride layer on the memory cell on the substrate; the silicon nitride layer is used for providing a hydrogen source; the first isolation portion and the second isolation portion constitute an isolation layer.
Optionally, when the peripheral circuit is located between the memory cell and the substrate, the memory cell is formed over the peripheral circuit by bonding; when the memory cell is located between the peripheral circuit and the substrate, the peripheral circuit is formed over the memory cell by bonding.
Optionally, the method further includes:
forming a via hole penetrating through the isolation layer in the isolation layer above the peripheral circuit; a third dielectric layer is formed on the side wall of the through hole;
forming a conductor plug in the via hole, the conductor plug for connecting the peripheral circuit and the memory cell.
Optionally, forming a through hole penetrating through the isolation layer in the isolation layer above or below the peripheral circuit includes:
etching the second dielectric layer, the conductor layer and the first dielectric layer above the peripheral circuit to obtain a first opening; the first dielectric layer is remained at the bottom of the first opening;
back-etching the conductor layer on the side wall of the first opening;
forming a third dielectric layer on the side wall and the bottom of the first opening;
and etching the third dielectric layer and the first dielectric layer at the bottom of the first opening to obtain a through hole penetrating through the isolation layer.
Optionally, forming a via penetrating through the isolation layer in the isolation layer above the peripheral circuit includes:
etching a second dielectric layer above the conductor layer in the isolation layer above the peripheral circuit to obtain a second opening;
etching the conductor layers at the bottom and on the side wall of the second opening to obtain a third opening;
forming a third dielectric layer on the side wall of the third opening;
and etching the third dielectric layer and the first dielectric layer at the bottom of the third opening to obtain a through hole penetrating through the isolation layer.
Optionally, the third dielectric layer is made of silicon oxide, and the conductor plug is made of tungsten.
Optionally, the first dielectric layer and the second dielectric layer are made of silicon oxide, and the conductor layer is made of titanium nitride.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof, the semiconductor device can comprise a substrate, and a peripheral circuit and a storage unit which are arranged on the substrate, wherein the hydrogen element in the storage unit is higher than the hydrogen element in the peripheral circuit, the peripheral circuit and the storage unit are separated by an isolation layer, and the isolation layer comprises a lamination of a first dielectric layer, a conductor layer and a second dielectric layer, so that the isolation layer can prevent the hydrogen element in the storage unit from diffusing into the peripheral circuit, the performance of the peripheral circuit is protected from being influenced by the hydrogen element, and the device performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 4 is a flow chart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present application;
fig. 5-16 show schematic structural diagrams in the manufacturing process of the semiconductor device provided by the embodiment of the application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, in general, a memory device may be divided into a memory region in which memory cells for storing data are disposed and a peripheral region in which peripheral circuits are disposed, and in the conventional 3D NAND, the peripheral region and the memory region have different requirements for hydrogen elements, and the hydrogen element in the memory region is generally higher than that in the peripheral region, whereas the peripheral region and the memory region are generally disposed adjacently, and the hydrogen element in the memory region is easily diffused to the peripheral region, affecting the performance of the peripheral circuits.
Based on the above technical problem, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same, where the semiconductor device may include a substrate, and a peripheral circuit and a memory cell on the substrate, where hydrogen in the memory cell is higher than that in the peripheral circuit, the peripheral circuit and the memory cell are separated by an isolation layer, and the isolation layer includes a stack of a first dielectric layer, a conductor layer, and a second dielectric layer 133, so that the isolation layer may prevent the hydrogen in the memory cell from diffusing into the peripheral circuit, protect the performance of the peripheral circuit from being affected by the hydrogen, and improve the performance of the device.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 2 and fig. 3, a schematic structural diagram of a semiconductor device provided in an embodiment of the present application may include a substrate 100, and a memory cell 120 and a peripheral circuit 110 on the substrate 100, wherein an isolation layer 130 is formed between the memory cell 120 and the peripheral circuit 110.
The substrate 100 may be a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) substrate, or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In the present embodiment, the substrate 100 is a bulk silicon substrate.
A memory cell 120 and a peripheral circuit 110 may be formed on the substrate 100, the peripheral circuit 110 being used to implement data input/output, and the memory cell 120 being used to store data. The relative position between the peripheral circuit 110 and the memory unit 120 can have various forms, which constitute two devices, the first is that the peripheral circuit 110 is located at the outer side (POC) of the memory unit 120, and both are located at the same height, the memory unit 120 is formed in the memory region, and the peripheral circuit 110 is formed in the peripheral region, as shown in fig. 1; another is that the peripheral circuit 110 and the memory unit 120 are stacked vertically, for example, the peripheral circuit 110 is located below the memory unit 120 (PUC) and located in different layers, as shown in fig. 2, in this case, the memory unit 120 may be formed above the peripheral circuit 110 by bonding, or may be formed above the peripheral circuit 110 by growing layer by layer, or the peripheral circuit 110 is located above the memory unit 120 and located in different layers, as shown in fig. 3, where the peripheral circuit 110 may be formed above the memory unit 120 by bonding, or may be formed above the memory unit 120 by growing layer by layer.
The hydrogen element in the memory unit 120 is higher than the hydrogen element in the peripheral circuit 110, and the peripheral circuit 110 and the memory unit 120 are separated by the isolation layer 130, so that the hydrogen element in the memory unit 120 can be prevented from diffusing into the peripheral circuit 110, the performance of the peripheral circuit 110 is protected from the hydrogen element, and the device performance is improved. Specifically, when the peripheral circuit 110 is located below the memory cell 120, the isolation layer 130 may be located below the memory cell 120 and above the peripheral circuit 110; when the peripheral circuit 110 is located above the memory cell 120, the isolation layer 130 may be located above the memory cell 120 and below the peripheral circuit 110; when the substrate region where the peripheral circuit 110 is located outside the substrate region where the memory cell 120 is located, the isolation layer 130 may be located on a sidewall of the peripheral circuit 110 and a sidewall of the memory cell 120, where "outside" indicates that the peripheral circuit 110 and the memory cell 120 are located in different regions, different from the relative positions of "up and down", and in fact, the peripheral circuit 110 may surround the memory cell 120, and the memory cell 120 may also surround the peripheral circuit 110.
The isolation layer 130 may include a stack of a first dielectric layer 131, a conductor layer 132, and a second dielectric layer 133 for isolating the peripheral circuit 110 and the memory cell 120, one of the first dielectric layer 131 and the second dielectric layer 133 being in contact with the peripheral circuit 110 and the other being in contact with the memory cell 120, and the conductor layer 132 may prevent hydrogen elements in the memory cell 120 from diffusing into the peripheral circuit 110. Specifically, the material of the first dielectric layer 131 and the second dielectric layer 133 may be silicon oxide, and the material of the conductor layer 132 is titanium nitride.
Generally, when the memory cell 120 and the peripheral circuit 110 are stacked vertically, the silicon nitride layer 140 is disposed on a side of the memory cell 120 away from the peripheral circuit 110. When the peripheral circuit 110 is located below the memory cell 120, i.e. the peripheral circuit 110 is located between the memory cell 120 and the substrate, the silicon nitride layer 140 and the peripheral circuit 110 are respectively located on the upper and lower sides of the memory cell 120, and do not have contact interfaces; when the memory cell 120 is located under the peripheral circuit 110, i.e., the memory cell 120 is located between the peripheral circuit 110 and the substrate, the silicon nitride layer 140 is located between the memory cell 120 and the substrate, so that the silicon nitride layer 140 and the peripheral circuit 110 are respectively located on the upper and lower sides of the memory cell 120 without contact interfaces.
When the peripheral circuit 110 is located outside the memory cell 120, the silicon nitride layer 140 is located above the memory cell 120 and the peripheral circuit 110, and is used to provide a hydrogen source for the memory cell 120 and protect the memory cell 120 and the peripheral circuit 110. At this time, the isolation layer 130 is also formed between the silicon nitride layer 140 and the peripheral circuit 110, i.e., above the peripheral circuit 110 and below the silicon nitride layer 140.
A via hole penetrating the isolation layer 130 is further formed in the isolation layer 130 above or below the peripheral circuit 110, a conductor plug 135 and a third dielectric layer 134 surrounding a sidewall of the conductor plug 135 are formed in the via hole, the conductor plug 135 is used for connecting the peripheral circuit 110 and the memory cell 120, and the third dielectric layer 134 around the conductor plug 135 is used for isolating the conductor plug 135 from the conductor layer 132 in the isolation layer 130. Specifically, the isolation layer 130 above the peripheral circuit 110 may include the isolation layer 130 below the memory cell 120 above the peripheral circuit 110, and may also include the isolation layer 130 below the silicon nitride layer 140 above the peripheral circuit 110. The material of the conductor plug 135 is tungsten, and the material of the third dielectric layer 134 is silicon oxide.
Of course, the memory cell 120 may have a lead-out structure connected to the conductor plug 135, and the lead-out structure may extend downward to be connected to the conductor plug 135 when the memory cell 120 is located above the peripheral circuit 110, and may extend upward to be connected by an interconnect layer above the memory cell 120 and the peripheral structure when the peripheral circuit 110 is located outside the memory cell 120.
The embodiment of the application provides a semiconductor device, which comprises a substrate, and a peripheral circuit and a storage unit which are arranged on the substrate, wherein hydrogen elements in the storage unit are higher than hydrogen elements in the peripheral circuit, the peripheral circuit and the storage unit are separated by using an isolation layer, and the isolation layer comprises a lamination of a first dielectric layer, a conductor layer and a second dielectric layer, so that the isolation layer can prevent the hydrogen elements in the storage unit from diffusing into the peripheral circuit, the performance of the peripheral circuit is protected from being influenced by the hydrogen elements, and the performance of the device is improved.
Based on the semiconductor device provided in the embodiments of the present application, embodiments of the present application also provide a method for manufacturing a semiconductor device, and referring to fig. 4, the method for manufacturing a semiconductor provided in the embodiments of the present application is a flowchart, and the method may include:
s01, a substrate 100 is provided, as shown with reference to fig. 5.
The substrate 100 may be a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or GOI (Germanium On Insulator) substrate, or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In the present embodiment, the substrate 100 is a bulk silicon substrate.
S02, a peripheral circuit 110, a memory cell 120, and an isolation layer 130 between the peripheral circuit 110 and the memory cell 120 are formed on the substrate, as shown with reference to fig. 5 to 16.
In this embodiment, the peripheral circuit 110, the isolation layer 130 on the peripheral circuit 110, the memory cell 120 on the isolation layer 130, and the silicon nitride layer on the memory cell 120 may be sequentially formed on the substrate, as shown in fig. 5, fig. 7, and fig. 2; a silicon nitride layer 140, a memory cell 120 on the silicon nitride layer 140, an isolation layer 130 on the memory cell 120, and a peripheral circuit on the isolation layer 130 may also be sequentially formed on the substrate, as shown in fig. 3; peripheral circuitry 110, an isolation layer 130 located on the sidewalls and top of peripheral circuitry 110, memory cells 120 located in a substrate region outside the substrate region where peripheral circuitry 110 is located, peripheral circuitry 110, and a silicon nitride layer 140 on memory cells 120 may also be formed on the substrate, as shown with reference to fig. 6, 8, and 1; it is also possible to form on the substrate the memory cell 120, a first isolation portion at the sidewall of the memory cell 120, the peripheral circuit 110 at a substrate region other than the substrate region where the memory cell is located, a second isolation portion on top of the peripheral circuit 110, and the silicon nitride layer 140 on the memory cell 120, the first isolation portion and the second isolation portion constituting the isolation layer 130.
The peripheral circuit 110 is used to realize data input/output. The formation position of the peripheral circuit 110 on the substrate may be determined according to the type of semiconductor device to be formed. When the peripheral circuit 110 is located outside the memory cell 120, the peripheral circuit 110 may be formed in a peripheral region, leaving the memory region free for the formation of the subsequent memory cell 120, and when the peripheral circuit 110 is located below the memory cell 120, the peripheral circuit 110 may cover the entire substrate or may be located at a specific position of the substrate.
The memory unit 120 is used for storing data, the memory unit 120 may be located in a memory region on a substrate, or located above the peripheral circuit 110, the memory unit 120 may be formed above the peripheral circuit 110 by bonding, or formed above the peripheral circuit 110 by layer-by-layer growth, the memory unit 120 may also be located below the peripheral circuit 110, and the peripheral circuit 110 may be formed above the memory unit 120 by bonding, or formed above the memory unit 120 by layer-by-layer growth.
The hydrogen element in the memory unit 120 is higher than the hydrogen element in the peripheral circuit 110, and the peripheral circuit 110 and the memory unit 120 are separated by the isolation layer 130, so that the hydrogen element in the memory unit 120 can be prevented from diffusing into the peripheral circuit 110, the performance of the peripheral circuit 110 is protected from the hydrogen element, and the device performance is improved. Specifically, when the peripheral circuit 110 is located below the memory cell 120, the isolation layer 130 may be located below the memory cell 120 and above the peripheral circuit 110; when the peripheral circuit 110 is located above the memory cell 120, the isolation layer 130 may be located above the memory cell 120 and below the peripheral circuit 110; when the substrate region of the peripheral circuit 110 is located outside the substrate region of the memory cell 120, the isolation layer 130 may be located on the sidewall of the peripheral circuit 110 and the sidewall of the memory cell 120.
The isolation layer 130 may include a stack of a first dielectric layer 131, a conductor layer 132, and a second dielectric layer 133 for isolating the peripheral circuit 110 and the memory cell 120, one of the first dielectric layer 131 and the second dielectric layer 133 being in contact with the peripheral circuit 110 and the other being in contact with the memory cell 120, and the conductor layer 132 may prevent hydrogen elements in the memory cell 120 from diffusing into the peripheral circuit 110. Specifically, the material of the first dielectric layer 131 and the second dielectric layer 133 may be silicon oxide, and the material of the conductor layer 132 is titanium nitride.
The isolation layer 130 may be formed by sequentially forming a first dielectric layer 131, a conductor layer 132, and a second dielectric layer 133 in a layer-by-layer growth manner, and a memory layer formed on the isolation layer 130 may be formed by bonding or may be formed in a layer-by-layer growth manner.
When the peripheral circuit 110 is located outside the memory cell 120, the peripheral circuit 110 may be formed on the substrate, as shown in fig. 6, after the peripheral circuit 110 is formed, a first dielectric layer 131, a conductor layer 132, and a second dielectric layer 133 are sequentially deposited to cover the upper surface and the sidewall of the peripheral circuit 110, and the exposed surface of the substrate, then the isolation layer 130 on the exposed surface of the substrate may be removed, as shown in fig. 8, and then the memory cell 120 and the silicon nitride layer 140 on the memory cell 120 and the peripheral circuit 110 may be formed on the uncovered surface of the substrate, as shown in fig. 1.
When the peripheral circuit 110 is located below the memory cell 120, i.e. the peripheral circuit 110 is located between the memory cell 120 and the substrate, the silicon nitride layer 140 and the peripheral circuit 110 are respectively located on the upper and lower sides of the memory cell 120, and do not have contact interfaces; when the memory cell 120 is located under the peripheral circuit 110, i.e., the memory cell 120 is located between the peripheral circuit 110 and the substrate, the silicon nitride layer 140 is located between the memory cell 120 and the substrate, so that the silicon nitride layer 140 and the peripheral circuit 110 are respectively located on the upper and lower sides of the memory cell 120 without contact interfaces.
When the peripheral circuit 110 is located outside the memory cell 120, the silicon nitride layer 140 is located above the memory cell 120 and the peripheral circuit 110, and is used to provide a hydrogen source for the memory cell 120 and protect the memory cell 120 and the peripheral circuit 110. At this time, the isolation layer 130 is also formed between the silicon nitride layer 140 and the peripheral circuit 110, i.e., above the peripheral circuit 110 and below the silicon nitride layer 140.
In addition, a via penetrating through the isolation layer 130 may be formed in the isolation layer 130 above or below the peripheral circuit 110, and a third dielectric layer 134 may be formed on a sidewall of the via, so that a conductor plug 135 may be formed in the via, the conductor plug 135 being used to connect the peripheral circuit 110 and the memory cell 120, and the third dielectric layer 134 around the conductor plug 135 being used to isolate the conductor plug 135 from the conductor layer 132 in the isolation layer 130.
Specifically, the isolation layer 130 above the peripheral circuit 110 may include the isolation layer 130 below the memory cell 120 above the peripheral circuit 110, and the step of forming the via and the conductor plug 135 is performed before forming the memory cell 120; the isolation layer 130 over the peripheral circuits 110 may also include the isolation layer 130 under the silicon nitride layer 140 over the peripheral circuits 110, and the step of forming the vias and the conductor plugs 135 is performed before forming the silicon nitride layer 140; the isolation layer 130 under the peripheral circuit 110 may include an isolation layer over the memory cell 120 under the peripheral circuit 110, and then the step of forming the via hole and the conductor plug 135 is performed before the peripheral circuit 110 is formed. The material of the conductor plug 135 is tungsten, and the material of the third dielectric layer 134 is silicon oxide.
The formation of the vias is described below with reference to fig. 9-16, taking the device shown in fig. 7 and 8 as an example.
As a possible implementation manner of forming the through hole, the second dielectric layer 133, the conductive layer 132, and the first dielectric layer 131 above the peripheral circuit 110 may be etched to obtain a through hole penetrating through the isolation layer 130, form a third dielectric layer 134 on the sidewall and the bottom of the through hole, and etch the third dielectric layer 134 on the bottom of the through hole to form a third dielectric layer 134 on the sidewall of the through hole.
As another possible implementation manner of forming the through hole, the second dielectric layer 133, the conductive layer 132, and the first dielectric layer 131 above the peripheral circuit 110 may be etched to obtain a first opening 151, and a portion of the first dielectric layer 131 may be left at the bottom of the first opening 151 to protect the upper surface of the peripheral circuit 110, as shown in fig. 9; etching back the conductive layer 132 on the sidewall of the first opening 151 to increase the inner diameter of the conductive layer 132, as shown in fig. 10; then, a third dielectric layer 134 may be formed on the sidewall and the bottom of the first opening 151, and the third dielectric layer 134 covers the inner wall of the conductor layer 132, the inner wall of the first dielectric layer 131, and the inner wall of the second dielectric layer 133; the third dielectric layer 134 and the first dielectric layer 131 at the bottom of the first opening 151 are etched to obtain a via 155 penetrating through the isolation layer 130, as shown in fig. 11.
As another embodiment of forming a via, the second dielectric layer 133 on the conductive layer 132 in the isolation layer 130 above the peripheral circuit 110 may be etched to obtain a second opening 152, the bottom of the second opening 153 is the conductive layer 132, and the second opening 152 obtained by etching may use the conductive layer 132 as an etching stop layer, as shown in fig. 13; etching the conductor layer 132 at the bottom and the sidewall of the second opening 152 to obtain a third opening 153, so as to increase the inner diameter of the conductor layer 132, as shown in fig. 14; forming a third dielectric layer 134 on the sidewall of the third opening 153, wherein the third dielectric layer 134 covers the inner wall of the conductor layer 132, the inner wall of the first dielectric layer 131, and the inner wall of the second dielectric layer 133; the third dielectric layer 134 and the first dielectric layer 131 at the bottom of the third opening are etched to obtain a via 156 penetrating through the isolation layer 130, as shown in fig. 15.
Thereafter, conductor plugs 135 may be formed in the vias 155/156, as shown with reference to fig. 12 and 16.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the steps of forming a peripheral circuit on a substrate, forming a storage unit on the substrate, and forming an isolation layer between the peripheral circuit and the storage unit, wherein the hydrogen element in the storage unit is higher than the hydrogen element in the peripheral circuit, and the isolation layer comprises a lamination of a first dielectric layer 131, a conductor layer 132 and a second dielectric layer, so that the isolation layer can prevent the hydrogen element in the storage unit from diffusing into the peripheral circuit, the performance of the peripheral circuit is protected from being influenced by the hydrogen element, and the device performance is improved.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (12)
1. A semiconductor device, comprising:
a substrate, and peripheral circuits and memory cells on the substrate; the hydrogen element in the storage unit is higher than the hydrogen element in the peripheral circuit;
the peripheral circuit and the memory unit are separated by an isolation layer, and the isolation layer comprises a lamination layer of a first dielectric layer, a conductor layer and a second dielectric layer.
2. The semiconductor device according to claim 1, wherein the peripheral circuit is located between the memory cell and the substrate, and a silicon nitride layer is formed over the memory cell to provide a hydrogen source using the silicon nitride layer; or the like, or, alternatively,
the storage unit is positioned between the peripheral circuit and the substrate, and a silicon nitride layer is also formed between the storage unit and the substrate so as to provide a hydrogen source by utilizing the silicon nitride layer; or the like, or, alternatively,
the substrate area where the peripheral circuit is located outside the substrate area where the storage unit is located, silicon nitride layers are formed on the peripheral circuit and the storage unit so as to provide hydrogen sources for the storage unit through the silicon nitride layers, and the isolation layer is further formed between the silicon nitride layers and the peripheral circuit.
3. The semiconductor device according to claim 1, wherein when the peripheral circuit is located between the memory cell and the substrate, the memory cell is formed over the peripheral circuit by bonding; when the memory cell is located between the peripheral circuit and the substrate, the peripheral circuit is formed over the memory cell by bonding.
4. The semiconductor device according to any one of claims 1 to 3, wherein a via hole penetrating the isolation layer is formed in the isolation layer above or below the peripheral circuit, and a conductor plug for connecting the peripheral circuit and the memory cell and a third dielectric layer surrounding a sidewall of the conductor plug are formed in the via hole.
5. The semiconductor device according to claim 4, wherein a material of the third dielectric layer is silicon oxide, and a material of the conductor plug is tungsten.
6. The semiconductor device according to any one of claims 1 to 3, wherein the material of the first dielectric layer and the second dielectric layer is silicon oxide, and the material of the conductor layer is titanium nitride.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a peripheral circuit, a memory cell, and an isolation layer between the peripheral circuit and the memory cell on the substrate; the hydrogen element in the memory cell is higher than that in the peripheral circuit, and the isolation layer includes a stack of a first dielectric layer, a conductor layer, and a second dielectric layer.
8. The method of claim 7, wherein forming peripheral circuitry, memory cells, and isolation layers between the peripheral circuitry and the memory cells on the substrate comprises:
sequentially forming a peripheral circuit, an isolation layer on the peripheral circuit, a storage unit on the isolation layer and a silicon nitride layer on the storage unit on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
sequentially forming a silicon nitride layer, a storage unit on the silicon nitride layer, an isolation layer on the storage unit and a peripheral circuit on the isolation layer on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
forming a peripheral circuit, an isolation layer positioned on the side wall and the top of the peripheral circuit, a memory cell positioned in a substrate area outside the substrate area where the peripheral circuit is positioned, and a silicon nitride layer on the peripheral circuit and the memory cell on the substrate; the silicon nitride layer is used for providing a hydrogen source; or the like, or, alternatively,
forming a memory cell, a first isolation part positioned on the side wall of the memory cell, a peripheral circuit positioned in a substrate area outside the substrate area where the memory cell is positioned, a second isolation part positioned on the top of the peripheral circuit, the peripheral circuit and a silicon nitride layer on the memory cell on the substrate; the silicon nitride layer is used for providing a hydrogen source; the first isolation portion and the second isolation portion constitute an isolation layer.
9. The method of claim 7, wherein the memory cell is formed over the peripheral circuitry by bonding while the peripheral circuitry is between the memory cell and the substrate; when the memory cell is located between the peripheral circuit and the substrate, the peripheral circuit is formed over the memory cell by bonding.
10. The method according to any one of claims 7-9, further comprising:
forming a via hole penetrating through the isolation layer in the isolation layer above or below the peripheral circuit; a third dielectric layer is formed on the side wall of the through hole;
forming a conductor plug in the via hole, the conductor plug for connecting the peripheral circuit and the memory cell.
11. The method of claim 10, wherein forming a via through an isolation layer above the peripheral circuitry in the isolation layer comprises:
etching the second dielectric layer, the conductor layer and the first dielectric layer above the peripheral circuit to obtain a first opening; the first dielectric layer is remained at the bottom of the first opening;
back-etching the conductor layer on the side wall of the first opening;
forming a third dielectric layer on the side wall and the bottom of the first opening;
and etching the third dielectric layer and the first dielectric layer at the bottom of the first opening to obtain a through hole penetrating through the isolation layer.
12. The method of claim 10, wherein forming a via through an isolation layer above the peripheral circuitry in the isolation layer comprises:
etching a second dielectric layer above the conductor layer in the isolation layer above the peripheral circuit to obtain a second opening;
etching the conductor layers at the bottom and on the side wall of the second opening to obtain a third opening;
forming a third dielectric layer on the side wall of the third opening;
and etching the third dielectric layer and the first dielectric layer at the bottom of the third opening to obtain a through hole penetrating through the isolation layer.
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Application publication date: 20210709 |