CN103824812A - 用于平面衬底的双外延cmos集成 - Google Patents

用于平面衬底的双外延cmos集成 Download PDF

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CN103824812A
CN103824812A CN201310444504.8A CN201310444504A CN103824812A CN 103824812 A CN103824812 A CN 103824812A CN 201310444504 A CN201310444504 A CN 201310444504A CN 103824812 A CN103824812 A CN 103824812A
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CN103824812B (zh
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N·劳贝特
B·普拉纳撒蒂哈兰
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STMicroelectronics lnc USA
International Business Machines Corp
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Abstract

本发明涉及一种用于平面衬底的双外延CMOS集成。本发明公开一种集成电路结构及相关方法。形成与在集成电路中的n型和p型区域二者之上的栅极电极相邻的硅锗区域。通过光刻而图案化的硬掩模然后保护在p型区域之上的结构而甚至在栅极电极上的侧壁间隔物上的硬掩模的剩余物之下从n型区域之上选择性地去除硅锗。外延生长与栅极电极相邻的硅锗碳取代去除的硅锗，并且在去除在p型区域结构之上的剩余硬掩模之前执行源极／漏极延伸注入。

Description

用于平面衬底的双外延CMOS集成
技术领域
本公开内容总体涉及制作互补金属氧化物半导体集成电路，并且更具体地，涉及互补金属氧化物半导体集成电路中的硅锗碳(silicon germanium carbon)层的外延沉积。
背景技术
前沿技术需要在低功率操作的高性能。硅锗碳(经常由“Si(Ge)(C)”、“SiGe(C)”或者“SiGe：C”中的任一项表示)层的外延生长可以是用于提高器件性能的有吸引力的解决方案。然而在互补MOS(CMOS)设计内的n沟道金属氧化物半导体(NMOS)和p沟道MOS(PMOS)晶体管需要不同外延，从而产生在对一个晶体管类型执行外延时在保护另一晶体管类型中的挑战。常规方法需要图案化和在NMOS或者PMOS器件上使用附加间隔物，这降低器件性能、使集成很难并且导致所得电路上的不良缺陷率。
也就是说，因此在本领域中需要一种用于在制作CMOS集成电路期间外延沉积硅锗碳层的改进工艺。
发明内容
形成与在集成电路中的n型和p型区域二者之上的栅极电极相邻的硅锗区域。通过光刻而图案化的硬掩模然后保护在p型区域之上的结构而甚至在栅极电极上的侧壁间隔物上的硬掩模的剩余物之下从n型区域之上选择性地去除硅锗。外延生长与栅极电极相邻的硅锗碳取代去除的硅锗，并且在去除在p型区域结构之上的剩余硬掩模之前执行源极／漏极延伸注入。
在描述以下具体实施方式之前，阐明贯穿本专利文献使用的某些字眼和短语的定义可以是有利的：术语“包括”及其派生词意味着包括而不限于；术语“或者”为包含意义，这意味着和／或；短语“与......关联”和“与之关联”及其派生词可以意味着包括、被包括在......内、与......互连、包含、被包含于......内、连接到或者与......连接、耦合到或者与......耦合、可与......连通、与......配合、交织、并置、与......邻近、限于或者用......限定、具有、具有......的性质等；并且术语“控制器”意味着控制至少一个操作的任何设备、系统或者其部分，可以在硬件、固件或者软件中实施这样的设备或者它们中的至少两项的某一组合。应当注意，可以无论本地还是远程地集中或者分布与任何特定控制器关联的功能。贯穿本专利文献提供用于某些字眼和短语的定义，本领域技术人员应当理解，在如果不是多数而为许多实例中，这样的定义适用于这样定义的字眼和短语的先前以及将来使用。
附图说明
为了更完整理解本公开内容及其优点，现在参照结合附图进行的以下描述，在附图中，相同标号代表相同部分：
图1A至图1J是根据本公开内容的一个实施例的在用于平面衬底的双外延CMOS集成工艺期间的半导体集成电路结构的一部分的截面图；并且
图2是图示根据本公开内容的一个实施例的用于平面衬底的双外延CMOS集成工艺的概略流程图。
具体实施方式
以下讨论的图1A至图2和用来在本专利文献中描述本公开内容的原理的各种实施例仅通过示例而不应以任何方式解释为限制公开内容的范围。本领域技术人员将理解可以在任何适当布置的系统中实施本公开内容的原理。
用PMOS优先方案的集成意味着首先在每处生长硅锗(SiGe)并且使用保护硬掩模(HM)，继而为光刻步骤。然后用干蚀刻执行简单HM反应离子蚀刻(RIE)以从NMOS结构上的外延SiGe之上去除硬掩模，但是留下PMOS结构上的保护层。使用氯化氢(HCl)的蚀刻性质来选择性地去除NMOS结构上的SiGe外延以选择性地去除SiGe，这有别于仅硅(Si的)结构。可选地，首先用注入物非晶化并且然后选择性地去除NMOS结构上的外延HM层，因为HCl气体也可以比对非晶SiGe：C层的对应单晶相选择性地去除非晶SiGe：C层。
图1A至图1J是根据本公开内容的一个实施例的在用于平面衬底的双外延CMOS集成工艺期间的半导体集成电路结构的一部分的截面图。图2是图示根据本公开内容的一个实施例的用于平面衬底的双外延CMOS集成工艺的概略流程图，并且以下结合图1A至图1J来讨论。尽管图示仅单个NMOS和PMOS晶体管对，但是本领域技术人员将理解，对于集成电路裸片上的和晶片内的许多不同裸片上的许多不同CMOS晶体管对使用相同工艺来并行形成相同结构。
本领域技术人员将认识到，图1A至图1J的结构尽管一般被绘制用于图示近似相对尺寸或者尺度、但是未按比例绘制。本领域技术人员将进一步认识到，在附图中未图示或者这里未描述用于形成集成电路和关联结构的全工艺。取而代之，为了简化和清楚，仅描绘和描述用于形成集成电路和关联结构的工艺的如本公开内容特有的或者为了理解本公开内容而必需的部分。此外，虽然在附图中图示和这里描述各种步骤，但是未暗示关于这样的步骤的顺序或者存在或者不存在居间步骤的限制。除非另有指明，完成如描绘或者描述为依次的步骤仅为了说明而未排除如果不是完全则至少部分以并行或者重叠方式实际执行相应步骤的可能性。
首先参照图1A，作为用于根据本公开内容的双外延CMOS集成的起点，集成电路结构100包括可选衬底101，在该衬底上形成各自用不同类型的杂质掺杂的半导体材料(例如硅)区域102-103以产生n型区域102和p型区域103。n型区域102和p型区域103被隔离区域104a相互电隔离并且被各自可以由(例如)二氧化硅形成的隔离区域104b和104c从衬底101上的相邻集成电路结构电隔离。分别可以是二氧化硅和硅的层105a和105b以及层106a和106b形成于n型区域102和p型区域103之上。层106a和106b可以是掺杂或者未掺杂和／或掺杂区域可以形成于层106b中(或者层106a和106b中)。用于晶体管的栅极电极形成于Si(Ge)(C)层106a和106b上，并且在示例实施例中各自包括氮氧化铪硅(HfSiON)栅极绝缘体107a和107b、氮化钛(TiN)阻挡层108a和108b以及多晶硅栅极电极109a和109b。
根据本公开内容的双外延CMOS集成工艺200始于在所有暴露的结构(即栅极电极和Si(Ge)(C)的相邻暴露部分二者，以及隔离区域104a至104b)之上用低压化学气相沉积(LPCVD)形成保形氮化硅(SiN)层110(步骤201)至近似9纳米(nm)的厚度。如图1B中所示，执行零损耗蚀刻(步骤202)以蚀刻和图案化氮化硅层110，从而形成SiN间隔物111。在示例实施例中，通过以下步骤来执行SiN层110的蚀刻和图案化：首先使用利用乙二醇稀释的氢氟酸(HFEG)溶液，然后使用反应离子蚀刻以定向地去除SiN层110的部分而在栅极电极的侧壁上留下显著厚度的SiN，并且最终用氢氟(HF)酸蚀刻以去除层106a和106b之上的任何剩余SiN，从而留下与栅极电极的两侧相邻的SiN间隔物111。
如图1C中所示，然后执行外延(步骤203)以在SiN间隔物111与隔离区域104a、104b和104c之间在层106a和106b的暴露表面上生长SiGe区域112a、112b、112c和112d。可以用适合于在p型区域103之上形成器件的杂质类型和浓度形成SiGe区域112a、112b、112c和112d。如图1D中所示，然后在整个结构100之上形成硬掩模(HM)113(步骤204。可以利用任何硬掩模材料，诸如氮化硅。如图1E中所示，在硬掩模113之上形成和图案化光刻胶114以允许除了与栅极电极相邻的部分或者剩余物115之外在n型区域102之上通过RIE选择性地去除硬掩模113(步骤205)。由于SiN RIE工艺的选择性而有可能用相对于SiGe层112a和112b的SiN RIE过蚀刻。在n型区域之上的硬掩模剩余物115由于SiN RIE的定向性质而保留，但是对于工艺流程不是必需的并且在其它工艺中并不用作附加侧壁间隔物的功能。取而代之，选择性蚀刻允许甚至在硬掩模剩余物115之下去除与n型区域102之上的栅极电极相邻的SiGe区域112a和112b。外延生长然后允许形成Si(Ge)(C)区域取代SiGe区域112a和112b。与栅极电极相邻的附加间隔物对于去除SiGe区域112a和112b以及外延生长Si(Ge)(C)取代SiGe区域112a和112b不是必需的。
参照图1F，然后剥离抗蚀剂114，执行预清理，并且通过HCl蚀刻来去除n型区域102之上的SiGe(步骤206)。如图1G中所示，然后执行外延(步骤207)以在层106a的暴露表面上生长Si(Ge)(C)区域116。形成Si(Ge)(C)区域116取代先前去除的、包括在硬掩模剩余物115之下的SiGe区域112a和112b。如图1H中所示，在p型区域103之上形成和图案化抗蚀剂117以允许在层106a内注入磷酸硼盐(BP)延伸(步骤208)。如图1I中所示，剥离了抗蚀剂，并且去除了p型区域103之上的硬掩模和硬掩模在n型区域102之上的剩余部分(步骤209)。如图1J中所示，然后执行最终间隔物形成、源极／漏极(S／D)注入和硅化(步骤210)。
本公开内容避免需要为NMOS或者PMOS晶体管形成和图案化与栅极电极相邻的单独间隔物以便形成Si(Ge)(C)区域。基于用于SiGe的蚀刻剂比对(SiN)硬掩模的选择性，可以从与栅极相邻的硬掩模剩余物之下去除SiGe区域。然后可以在那些硬掩模剩余物之下外延生长Si(Ge)(C)区域。因此简化集成电路制作工艺流程中的Si(Ge)(C)形成的集成，而对器件性能和缺陷率的有害影响更少。
虽然已经用示例实施例描述本公开内容，但是本领域技术人员可以想到各种改变和修改。旨在于本公开内容涵盖如落入所附权利要求的范围内的这样的改变和修改。

Claims (20)

1.一种方法，包括：
形成与在n型区域和p型区域二者之上的栅极电极相邻的硅锗(SiGe)区域；
在所述p型区域中的结构之上形成和图案化硬掩模；
相对于所述硬掩模的材料选择性地去除与在所述n型区域之上的所述栅极电极相邻的所述硅锗区域；并且
外延生长与在所述n型区域之上的所述栅极电极相邻的硅锗碳(Si(Ge)C)区域以取代所去除的硅锗区域。
2.根据权利要求1所述的方法，其中所述硬掩模包括氮化硅(SiN)，并且其中所述硬掩模的剩余物在所述硬掩模被图案化时保留于与在所述n型区域之上的所述栅极电极相邻并且在所述硅锗区域之上的间隔物上。
3.根据权利要求2所述的方法，还包括去除所述硅锗区域的与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的部分。
4.根据权利要求3所述的方法，还包括外延生长与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的硅锗碳。
5.根据权利要求4所述的方法，还包括：
在外延生长与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的所述硅锗碳区域之后，去除所述硬掩模剩余物。
6.根据权利要求5所述的方法，还包括：
在外延生长与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的所述硅锗碳区域之后，并且在去除所述硬掩模剩余物之前，在所述硅锗碳区域以下的层中注入源极／漏极延伸。
7.根据权利要求1所述的方法，其中在选择性地去除与在所述n型区域之上的所述栅极电极相邻的所述硅锗区域和外延生长与在所述n型区域之上的所述栅极电极相邻的硅锗碳区域以取代所去除的硅锗区域期间，所述硬掩模保留于所述p型区域中的结构之上。
8.根据权利要求1所述的方法，其中所述硅锗区域邻接在所述n型区域之上的所述栅极电极上的侧壁间隔物。
9.根据权利要求1所述的方法，其中所述硬掩模由氮化硅形成。
10.根据权利要求9所述的方法，还包括使用盐酸(HCl)以去除与在所述n型区域之上的所述栅极电极相邻的所述硅锗区域而不去除所述硬掩模的剩余物。
11.一种集成电路结构，包括：
在衬底上的n型区域和p型区域二者之上的栅极电极；以及
在通过去除硅锗区域而留下的至少定义空间中与在所述n型区域之上的所述栅极电极相邻的硅锗碳(Si(Ge)(C))区域。
12.根据权利要求11所述的集成电路结构，其中所述硅锗碳区域邻接在所述n型区域之上的所述栅极电极上的侧壁间隔物。
13.根据权利要求12所述的集成电路结构，还包括：
在所述侧壁间隔物上并且在所述硅锗碳区域之上的图案化硬掩模的剩余物。
14.根据权利要求13所述的集成电路结构，其中所述硬掩模剩余物由氮化硅形成。
15.根据权利要求14所述的集成电路结构，其中外延地生长所述硅锗碳区域。
16.一种集成电路结构，包括：
在衬底上的n型区域和p型区域二者之上的栅极电极；
与在所述p型区域之上的所述栅极电极相邻的硅锗(SiGe)区域；
在所述p型区域上的结构之上的图案化硬掩模；
用于在所述n型区域之上的所述栅极电极上的侧壁间隔物上的所述硬掩模的材料的剩余物；以及
与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的包含至少硅和锗的区域。
17.根据权利要求16所述的集成电路结构，其中与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的包含至少硅和锗的所述区域是与在所述p型区域之上的所述栅极电极相邻的所述硅锗区域并行形成的硅锗区域。
18.根据权利要求16所述的集成电路结构，其中与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的包含至少硅和锗的所述区域是在所述硬掩模剩余物之下外延生长的硅锗碳(Si(Ge)(C))区域。
19.根据权利要求18所述的集成电路结构，其中所述硬掩模由氮化硅形成。
20.根据权利要求19所述的集成电路结构，其中与在所述n型区域之上的所述栅极电极相邻并且在所述硬掩模剩余物之下的包含至少硅和锗的所述区域是在所述侧壁间隔物与从相接区域分离所述n型区域的隔离区域之间的区域。
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