CN103796448B - The minimum method of printed circuit board (PCB) BVH depth - Google Patents
The minimum method of printed circuit board (PCB) BVH depth Download PDFInfo
- Publication number
- CN103796448B CN103796448B CN201310498762.4A CN201310498762A CN103796448B CN 103796448 B CN103796448 B CN 103796448B CN 201310498762 A CN201310498762 A CN 201310498762A CN 103796448 B CN103796448 B CN 103796448B
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- Prior art keywords
- coverlay
- bvh
- copper
- raw material
- depth
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/005—Punching of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Laser Beam Processing (AREA)
Abstract
The present invention relates to the minimum method of printed circuit board (PCB) BVH depth, it comprises：The raw material of volume (roll) state forms the raw material preparation process S10 of circuit with certain size after cutting；The coverlay that the single or double of the raw material preparing in described raw material preparation process S10 is laminated carries out dozen coverlay pulling out and beats the rapid S20 that takes a step；Described coverlay is beaten in the rapid S20 that takes a step and beat step S30 that the coverlay vacation pulled out connects and is laminated to raw material single or double；Step S40 connecing and being laminated sticker (Prepreg) and copper (Copper) between laminate layers above the coverlay of lamination in step S30 of coverlay in described vacation；In order to form BVH, by copper (Copper) the layer casing milling steps S50 that open a window of copper (Copper) of lamination；It is pointed to step S60 that the interlayer sticker (Prepreg) of the windowing bottom surface of copper (Copper) layer is opened a window in described copper (Copper) layer casing milling steps S50；To de-smear step S70 carrying out removing glue Slag treatment through the BVH exposing that opens a window；And implement gold-plated gold-plated step S80 after completing removing glue Slag treatment in described de-smear step S70.
Description
Technical field
The present invention relates to the minimum method of printed circuit board (PCB) BVH depth, it is more particularly related to processing BVH
When, depth (DEPTH) is minimized to guarantee the reliability of BVH, and then guarantees the printed circuit board (PCB) BVH of gold-plated job stabilization
The minimum method of depth.
Background technology
The multifunction of current needs FPCB product, forms multiple stratification and blind hole (BVH) with it.
Described blind hole (BVH) is due to using the thin film (prepreg) determining BVH depth and thin coverlay
(coverlay) although the depth shallower of BVH, but the gross thickness of customer demand can not be met, occur BVH depth to deepen on the contrary
Problem.
However, the deeper reliability being more difficult to guarantee BVH of the depth of BVH, for this most enterprise as shown in figure 1, carrying out
Plasma or de-smear technique are to guarantee reliability.But, existing method is due to increasing the pre-treatment of plasma or de-smear
Technique, has the productive problem of reduction,
Pre-treating technology such as plasma or de-smear technique can not be met, or in the required condition of BVH, such as scheme
Shown in 2, pollution and resin (resin) are not completely eliminated in bottom surface and produce glue residue (smear), if during overtreating, such as Fig. 3
Broken (void) is bad in shown generation hole, and when making gold-plated, gold plating liquid can not successfully be impregnated with and produce bad.
As mentioned above in addition to plasma and removing glue Slag treatment, the expansion due to surface BVH WINDOW size can be true
Protect aspect ratio (aspect ratio), but as shown in figure 4, off normal can be produced in pattern operation and hole is quick-fried during BVH dimension enlargement
Split, therefore there is the problem reducing productivity and increasing fraction defective.
In addition, guarantee the reliability of BVH using the attempt of other methods, but continue to produce other bad phenomenon, therefore
Suffer difficulty in terms of the reliability guaranteeing BVH.
Look-ahead technique document Prior Art
Patent documentation
(patent documentation 1) Koran Office registered patent publication the 10-0632557th
Content of the invention
The technical problem to be addressed by invention
The invention solves the problems that existing issue as above, the purpose of the present invention is to pull out in beating of coverlay (Coverlay)
Consider the size of BVH in operation and off normal carries out beating and pulls out, therefore glue between coverlay (Coverlay) the top laminate layers pulling out beating
When agent (Prepreg) and copper (Copper), there is not coverlay (Coverlay) in the part forming BVH, that is, only BVH's
Region is not covered with film (Coverlay), and there is coverlay (Coverlay) in other regions, thus provides and meets gross thickness,
The minimum method of the printed circuit board (PCB) BVH depth of the depth minimization of BVH can be made simultaneously.
Solve the technical scheme of problem
The present invention, in order to complete purpose as above, to be realized with having the embodiment being constituted as follows.
The invention is characterized in that comprising：The raw material of volume (roll) state forms the former of circuit after cutting with certain size
Material preparation process S10；Coverlay to the single or double lamination of the raw material preparing in described raw material preparation process S10
Carry out dozen coverlay pulling out and beat the rapid S20 that takes a step；Described coverlay is beaten in the rapid S20 that takes a step and play the coverlay vacation pulled out and connect and be laminated to
Step S30 of raw material single or double；Connect in described vacation and be laminated the coverlay upper layer of lamination in step S30 of coverlay
Step S40 of sticker (Prepreg) and copper (Copper) between laminate layer；In order to form BVH, by copper (Copper) windowing of lamination
Copper (Copper) layer casing milling steps S50；It is pointed to copper (Copper) layer in described copper (Copper) layer casing milling steps S50
Step S60 that the interlayer sticker (Prepreg) of windowing bottom surface is opened a window；Carry out at de-smear to through the BVH exposing that opens a window
De-smear step S70 of reason；And implement gold-plated gold-plated step after completing removing glue Slag treatment in described de-smear step S70
S80.
The described coverlay of the present invention beats the rapid S20 that takes a step it is characterised in that considering gold-plated part and forming BVH part
BVH size and off normal and carry out beat pull out.
The described coverlay of the present invention is beaten and is taken a step rapid S20 it is characterised in that beating, using Laser operating type, mould, the side of pulling out
Between formula, BVH, interval operating type carries out to coverlay beating and pulls out.
Beneficial effect
As described above is at coverlay (Coverlay) according to the minimum method of the printed circuit board (PCB) BVH depth of the present invention
Beat to pull out and consider BVH size and off normal in operation and carry out beating and pull out, therefore beating coverlay (Coverlay) the top laminate layers pulling out
Between sticker (Prepreg) and during copper (Copper), there is not coverlay (Coverlay) in the part forming BVH, only exist
The region of BVH is not covered with film (Coverlay), and there is coverlay (Coverlay) in other regions, thus can plan symbol
Close gross thickness, the effect of the depth minimization of BVH can be made simultaneously.
In addition, the present invention be in BVH Depth exclusion Coverlay, with respect to existing thickness averagely reduce 20um with
On, and Aspect Ratio value also about reduce 20% expression average with respect to existing Aspect Ratio value 75～85% to 55～
Between 65%, so that gold plating liquid is successfully impregnated with, stably can carry out operation, and BVH Depth reduces, tool
There is the effect that may insure reliability.
In addition, the present invention is the reliability that is lowered to ensure that according to BVH Depth, excludes plasma treatment, depend merely on removing glue
Slag treatment can plan the effect that can ensure that reliability.
In addition, the present invention is to be not changed in simply reducing Depth itself according to surface BVH WINDOW SIZE, prevent hole
Off normal and hole explosion, have improve productivity and reduce fraction defective effect.
Brief description
Fig. 1 is the schematic flow sheet that existing BVH reliability guarantees technique.
Fig. 2 is the photo of the problem occurring when the condition that existing BVH reliability guarantees pretreatment process in technique is not enough.
Fig. 3 is the photo of the problem occurring when existing BVH reliability guarantees that the condition of pretreatment process in technique is excessive.
Fig. 4 is the photo of problem occurring during the expanded in size guaranteeing BVH surface in technique in existing BVH reliability.
Fig. 5 is the schematic flow sheet of the minimum method of printed circuit board (PCB) BVH depth according to an embodiment of the invention.
Fig. 6 is the schematic diagram that vacation according to an embodiment of the invention connect and be laminated coverlay step.
Fig. 6 to Fig. 8 is that the printed circuit board (PCB) of the minimum method being suitable for BVH depth according to an embodiment of the invention shines
Piece.
Specific embodiment
Below in conjunction with accompanying drawing, the minimum method of the printed circuit board (PCB) BVH depth according to the present invention is carried out specifically
Bright.Identical constituent element to be represented with identical symbol as far as possible in the accompanying drawings.In addition idea of the invention may be produced
The unnecessary known function obscured and composition, omit detail explanation.
Fig. 5 is the schematic flow sheet of the minimum method of printed circuit board (PCB) BVH depth according to an embodiment of the invention, figure
6 is the schematic diagram that vacation according to an embodiment of the invention connect and be laminated coverlay step, and Fig. 6 to Fig. 8 is to be suitable for according to the present invention
The printed circuit board (PCB) photo of the minimum method of the BVH depth of one embodiment.
As shown in figure 5, the present invention comprises：The raw material of volume (roll) state forms circuit after cutting with certain size
Raw material preparation process S10；Covering to the single or double lamination of the raw material preparing in described raw material preparation process S10
Film carries out dozen coverlay pulling out and beats the rapid S20 that takes a step；Described coverlay is beaten in the rapid S20 that takes a step and play the coverlay vacation pulled out and connect and be laminated
Lamination step S30 in raw material single or double；Connect in described vacation and be laminated the coverlay of lamination in step S30 of coverlay
Above between laminate layers sticker (Prepreg) and copper (Copper) step S40；In order to form BVH, in the copper of lamination
(Copper) process copper (Copper) layer hole machined step S50 in hole；Described copper (Copper) layer hole machined step S50 is revealed
Step S60 that hole is processed on interlayer sticker (Prepreg) layer going out；The BVH exposing is carried out with the de-smear of removing glue Slag treatment
Step S70；And implement gold-plated gold-plated step S80 after completing removing glue Slag treatment in described de-smear step S70.
Described raw material preparation process S10 be by volume (roll) state raw material cut with certain size after, covering
The step of circuit needed for being formed on the Copper Foil of lid raw material.Described circuit is the resist corrosion using acid medicine and drug-resistant
(etching) Copper Foil and formed.
It is to subsequently gold-plated part and formation BVH on coverlay (Coverlay) that described coverlay beats the rapid S20 that takes a step
Part windowing carry out beating the step pulled out, with Laser operating type, that interval operating type between the mode of pulling out, BVH beaten by mould is complete
Become.
Described Laser operating type can be to implement to beat the more close tolerance of the mode of pulling out than mould, in expense when processing a small amount of
Aspect ratio is advantageous, produces the tolerance of 50um～70um during the lateral deviation calculating BVH Size and Laser, and calculating both sides then needs
Will about 100um～140um.
The mode of pulling out beaten by described mould needs bigger tolerance than Laser operating type, but during process volume in terms of expense
Ratio is advantageous, produces the tolerance of 100～200um during the lateral deviation calculating BVH Size and Laser, and calculating both sides then needs greatly
About 200um～400um.
Between described BVH, interval operating type is to beat in mould to occur without tolerance of interval (500um) in the mode of pulling out between BVH
When, each BVH will be integrated and open a window (OPEN).
Step S30 that described vacation connect and be laminated coverlay is to carry out hot pressing in the substrate surface of described raw material, is used for
The circuit vacation step that connects and be laminated insulating barrier coverlay being formed on protection Copper Foil, when described vacation connects technique and refers to be laminated coverlay
For the technique preventing tegillum pressure pressure from pushing or distorting and paste temporarily.
Step S40 of described lamination interlayer sticker (Prepreg) and copper (Copper) is to connect and be laminated in described vacation to cover
Above the coverlay of lamination in step S30 of epiphragma between laminate layers sticker (Prepreg) and copper (Copper) step.
Described copper (Copper) layer hole machined step S50 is to irradiate or be exposed etching to form hole using UV LASER,
Make the step that the table facing external of the interlayer adhering agent layer positioned at bottom surface is exposed.
Step S60 processing hole on described interlayer sticker (Prepreg) layer is to be pointed to described copper (Copper) layer hole
Interlayer sticker (Prepreg) the layer irradiating laser of removed layers of copper bottom surface in procedure of processing S50, in interlayer sticker
(Prepreg) step that hole is processed on layer.
Described de-smear step S70 is when processing hole, and the resin melting inwall flowing out and being attached to hole of internal layer hinders
Pasting of internal layer and the step that chemically eliminates.
Described gold-plated step S80 is the technique that the BVH inwall exposing is covered using electrochemical method with copper, thus processes
BVH makes the inside/outside layer of insertion become the step being electrically connected with (conducting).
Existing BVH Depth is worthwhile copper (Copper) layer, interlayer sticker (Prepreg) layer and coverlay
(Coverlay) total thickness value, but the BVH Depth of the present invention is to beat in coverlay (Coverlay) to pull out consideration BVH in operation
Size and off normal and carry out beating and pull out, therefore playing sticker (Prepreg) between coverlay (Coverlay) the top laminate layers pulling out
And during copper (Copper), there is not coverlay (Coverlay) in the part forming BVH.Therefore, only do not cover in the region of BVH
Epiphragma (Coverlay), and there is coverlay (Coverlay) in other regions, thus have and meet gross thickness, can make simultaneously
The effect of the depth minimization of BVH.
More than, the various embodiments of the present invention are illustrated, but described embodiment is to implement the technology of the present invention to think
The embodiment thought, every any modification realizing the technology of the present invention thought or fixed case should belong to the model of the present invention
Enclose.
<The explanation of main graphical labelling>
S10：Raw material preparation process
S20：Coverlay is beaten and is taken a step suddenly
S30：The step that vacation connects and is laminated coverlay
S40：Lamination interlayer sticker (Prepreg) and the step of copper (Copper)
S50：Copper (Copper) layer hole machined step
S60：The step that hole is processed on interlayer sticker (Prepreg) layer
S70：De-smear step
S80：Gold-plated step
Claims (1)
1. a kind of minimum method of printed circuit board (PCB) BVH depth, is characterized in that comprising：The raw material of volume state is with certain big
Little cut after formed circuit raw material preparation process S10；List to the raw material preparing in described raw material preparation process S10
The coverlay of face or dual sided lamination carries out dozen coverlay pulling out and beats the rapid S20 that takes a step；Described coverlay is beaten beat in the rapid S20 that takes a step and pull out
Coverlay vacation step S30 that connects and be laminated to raw material single or double；Step S30 connecing and being laminated coverlay in described vacation
Above the coverlay of middle lamination between laminate layers sticker and copper step S40；In order to form BVH, on the top of the layers of copper of lamination
Irradiate or be exposed etching using UV laser and form hole, so that the table facing external of the interlayer adhering agent layer positioned at bottom surface is exposed
Layers of copper hole machined step S50；The top profit of the interlayer adhering agent layer being exposed by the hole being formed in described layers of copper hole machined step S50
Irradiate or be exposed etching with UV laser and form hole, make the interlayer sticker that the materials statement facing external positioned at bottom surface is exposed
Step S60 that hole is processed on layer；De-smear step S70 of removing glue Slag treatment is carried out to the BVH of processing；And in described de-smear
Implement gold-plated gold-plated step S80 after completing removing glue Slag treatment in step S70,
Wherein, described coverlay beats the rapid S20 that takes a step is to play interval operation between the mode of pulling out, BVH using laser work mode, mould
Any one in mode carries out coverlay beats and pulls out, and considers the both sides that the laser work mode of BVH size and a lateral deviation needs
Tolerance is 100～140um, and the both sides tolerance that mould is beaten the mode of pulling out and needed is 200～400um, and between BVH, interval operating type is
When mould is beaten and occurred without tolerance of interval between BVH in the mode of pulling out, each BVH will be integrated and open a window.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2012-0119522 | 2012-10-26 | ||
| KR1020120119522A KR101299258B1 (en) | 2012-10-26 | 2012-10-26 | The printed circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103796448A CN103796448A (en) | 2014-05-14 |
| CN103796448B true CN103796448B (en) | 2017-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310498762.4A Active CN103796448B (en) | 2012-10-26 | 2013-10-22 | The minimum method of printed circuit board (PCB) BVH depth |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR101299258B1 (en) |
| CN (1) | CN103796448B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114018373B (en) * | 2021-10-28 | 2024-07-02 | 广州兴森快捷电路科技有限公司 | Method and system for measuring glue removal amount |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1226802A (en) * | 1998-01-14 | 1999-08-25 | 三井金属鈜业株式会社 | Method for producing multi-layer printed wiring boards having blind vias |
| CN101098591A (en) * | 2006-06-26 | 2008-01-02 | 景硕科技股份有限公司 | Patterned method for tape coiling type thin object in automated process |
| CN101106872A (en) * | 1997-07-08 | 2008-01-16 | 伊比登株式会社 | Printed wiring board and method of producing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040058418A (en) * | 2002-12-26 | 2004-07-05 | 삼성전기주식회사 | Manufacturing method of rigid flexible printed circuit board for mobile phone |
| KR100722620B1 (en) | 2005-10-31 | 2007-05-28 | 삼성전기주식회사 | Rigid-flexible Print circuit board and method for manufacturing thereof |
| KR100751471B1 (en) | 2006-02-02 | 2007-08-23 | 영풍전자 주식회사 | Method for making window-open part of flexible printed circuit board |
| KR100894701B1 (en) | 2007-10-04 | 2009-04-24 | 삼성전기주식회사 | Rigid-flexible Print circuit board and method for manufacturing thereof |
-
2012
- 2012-10-26 KR KR1020120119522A patent/KR101299258B1/en active IP Right Grant
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2013
- 2013-10-22 CN CN201310498762.4A patent/CN103796448B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101106872A (en) * | 1997-07-08 | 2008-01-16 | 伊比登株式会社 | Printed wiring board and method of producing the same |
| CN1226802A (en) * | 1998-01-14 | 1999-08-25 | 三井金属鈜业株式会社 | Method for producing multi-layer printed wiring boards having blind vias |
| CN101098591A (en) * | 2006-06-26 | 2008-01-02 | 景硕科技股份有限公司 | Patterned method for tape coiling type thin object in automated process |
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| Publication number | Publication date |
|---|---|
| KR101299258B1 (en) | 2013-08-22 |
| CN103796448A (en) | 2014-05-14 |
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