CN103796448A - Method of minimizing depth of blind via hole (BVH) of printed circuit board - Google Patents
Method of minimizing depth of blind via hole (BVH) of printed circuit board Download PDFInfo
- Publication number
- CN103796448A CN103796448A CN201310498762.4A CN201310498762A CN103796448A CN 103796448 A CN103796448 A CN 103796448A CN 201310498762 A CN201310498762 A CN 201310498762A CN 103796448 A CN103796448 A CN 103796448A
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- Prior art keywords
- bvh
- coverlay
- copper
- layer
- hole
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/005—Punching of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Laser Beam Processing (AREA)
Abstract
A method of minimizing the depth of a BVH of a printed circuit board includes a raw material preparing step (S10) forming a circuit after cutting raw materials with a roll state into a constant size; a coverlay punching step (S20) punching a coverlay to be laminated on one surface or both surfaces of the raw materials prepared in the raw material preparing step (S10); a step (S30) of attaching and laminating the punched coverlay on one surface or both surfaces of the raw materials; a step (S40) of laminating a prepreg layer and a copper layer on the upper part of the laminated coverlay obtained in the step (S30); a copper layer hole processing step (S50) forming a hole on the laminated copper layer for forming the BVH; a prepreg layer hole processing step (S60) forming a hole on the upper part of the prepreg layer exposed by the hole formed in the copper layer hole processing step (S50); a de-smear processing step (S70) de-smearing the processed BVH; and a plating step (S80) performing plating after the de-smear processing step (S70).
Description
Technical field
The present invention relates to the Method for minimization of the printed circuit board (PCB) BVH degree of depth, more particularly, while the present invention relates to process BVH, the degree of depth (DEPTH) is minimized to guarantee the reliability of BVH, and then guarantee the Method for minimization of the printed circuit board (PCB) BVH degree of depth of gold-plated job stabilization.
Background technology
The multifunction of current needs FPCB product, forms multiple stratification and blind hole (BVH) with it.
Described blind hole (BVH) is owing to using the thin film (prepreg) and the thin coverlay (coverlay) that determine the BVH degree of depth, although the degree of depth of BVH shoals, but can not meet the gross thickness of customer demand, the problem that the BVH degree of depth deepens occurs on the contrary.
But, the more dark more difficult reliability of guaranteeing BVH of the degree of depth of BVH, most enterprise as shown in Figure 1, carries out plasma or de-smear technique to guarantee reliability for this reason., existing method, owing to increasing the pre-treating technology of plasma or de-smear, has the productive problem of reduction,
Can not meet pre-treating technology as plasma or de-smear technique, or in the time of the required condition of BVH, as shown in Figure 2, there is no complete pollution abatement and resin (resin) in bottom surface and produce glue slag (smear), if when overtreating, produce as shown in Figure 3 hole broken (void) bad, make gold plating liquid when gold-plated can not successfully soak into and produce bad.
As mentioned above except plasma and de-smear processing, because the expansion of surperficial BVH WINDOW size can be guaranteed aspect ratio (aspect ratio), but BVH size expand time as shown in Figure 4, in pattern operation, can produce off normal and hole explosion, therefore there is the problem that reduces productivity and increase fraction defective.
In addition, utilize other method attempt to guarantee the reliability of BVH, but continue to produce other bad phenomenon, therefore guaranteeing to suffer difficulty aspect the reliability of BVH.
Look-ahead technique document
Patent documentation
No. 10-0632557th, (patent documentation 1) Koran Office registered patent communique
Summary of the invention
The technical problem to be addressed by invention
The present invention will solve existing issue as above, the object of the invention is to consider that the size of BVH and off normal are beaten pulls out in beating of coverlay (Coverlay) pulled out operation, therefore in the time beating coverlay (Coverlay) the top lamination interlayer sticker (Prepreg) that pulls out and copper (Copper), there is not coverlay (Coverlay) in the part that forms BVH, only there is no coverlay (Coverlay) in the region of BVH, and there is coverlay (Coverlay) in other region, provide thus and meet gross thickness, can make the Method for minimization of the printed circuit board (PCB) BVH degree of depth of the depth minimization of BVH simultaneously.
Solve the technical scheme of problem
The present invention, in order to complete object as above, realizes with the embodiment with following formation.
Feature of the present invention is to comprise: the raw material of volume (roll) state cut the raw material preparation process S10 of rear formation circuit with certain size; The coverlay of the raw-material single or double lamination of preparing at described raw material preparation process S10 is beaten to the coverlay pulling out and beat the rapid S20 that takes a step; Described coverlay is beaten to the step S30 that plays the coverlay vacation of pulling out in the rapid S20 that takes a step and connect and be laminated to raw material single or double; Described vacation connect and the step S30 of lamination coverlay in the step S40 of lamination interlayer sticker (Prepreg) and copper (Copper) above the coverlay of lamination; In order to form BVH, copper (Copper) that the copper of lamination (Copper) the is windowed layer step S50 that windows; The step S60 windowing to being positioned at the interlayer sticker (Prepreg) of the bottom surface of windowing of copper (Copper) layer in described copper (Copper) layer is windowed step S50; The BVH exposing through windowing is carried out to the de-smear step S70 of de-smear processing; And implement gold-plated gold-plated step S80 complete de-smear processing in described de-smear step S70 after.
Described coverlay of the present invention is beaten the rapid S20 that takes a step, and it is characterized in that, considers gold-plated part and beats and pull out with forming the BVH size of BVH part and off normal.
Described coverlay of the present invention is beaten the rapid S20 that takes a step, and it is characterized in that, utilizes Laser operating type, mould to beat interval operating type between the mode of pulling out, BVH coverlay is beaten and pulled out.
Beneficial effect
As mentioned above to beat and consider that BVH size and off normal are beaten in pulling out operation and pull out at coverlay (Coverlay) according to the Method for minimization of the printed circuit board (PCB) BVH degree of depth of the present invention, therefore in the time beating coverlay (Coverlay) the top lamination interlayer sticker (Prepreg) that pulls out and copper (Copper), there is not coverlay (Coverlay) in the part that forms BVH, only there is no coverlay (Coverlay) in the region of BVH, and there is coverlay (Coverlay) in other region, can plan and meet gross thickness thus, can make the effect of the depth minimization of BVH simultaneously.
In addition, the present invention gets rid of Coverlay in BVH Depth, more than on average reducing 20um with respect to existing thickness, and Aspect Ratio value also approximately reduces 20% and is on average illustrated between 75～85% to 55～65% with respect to existing Aspect Ratio value, when gold-plated operation, make gold plating liquid successfully soak into, can stably carry out operation, and BVH Depth reduction, the effect that can guarantee reliability there is.
In addition, the present invention be according to the reduction of BVH Depth to guarantee reliability, get rid of plasma treatment, depend merely on de-smear processing and can plan the effect that can guarantee reliability.
In addition, the present invention does not change and just reduces Depth itself according to surperficial BVH WINDOW SIZE, prevents the off normal in hole and the explosion in hole, has the effect that improves productivity and reduce fraction defective.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet that existing BVH reliability is guaranteed technique.
Fig. 2 is the photo of the condition of pretreatment process in existing BVH reliability is guaranteed technique problem occurring when not enough.
Fig. 3 is the photo of the condition of pretreatment process in existing BVH reliability is guaranteed technique problem occurring when excessive.
Fig. 4 is the photo of problem occurring during by the expanded in size on BVH surface in existing BVH reliability is guaranteed technique.
Fig. 5 is the schematic flow sheet of the Method for minimization of the printed circuit board (PCB) BVH degree of depth according to an embodiment of the invention.
Fig. 6 is false according to an embodiment of the invention connecing and the schematic diagram of lamination coverlay step.
Fig. 6 to Fig. 8 is suitable for the printed circuit board (PCB) photo of the Method for minimization of the BVH degree of depth according to an embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing, the Method for minimization of the printed circuit board (PCB) BVH degree of depth according to the present invention is described in detail.Identical constituent element represents with identical symbol as far as possible in the accompanying drawings.May produce the unnecessary known function of obscuring and formation to main idea of the present invention in addition, omit its detailed explanation.
Fig. 5 is the schematic flow sheet of the Method for minimization of the printed circuit board (PCB) BVH degree of depth according to an embodiment of the invention, Fig. 6 is false according to an embodiment of the invention connecing and the schematic diagram of lamination coverlay step, and Fig. 6 to Fig. 8 is suitable for the printed circuit board (PCB) photo of the Method for minimization of the BVH degree of depth according to an embodiment of the invention.
As shown in Figure 5, the present invention comprises: the raw material of volume (roll) state cut the raw material preparation process S10 of rear formation circuit with certain size; The coverlay of the raw-material single or double lamination of preparing at described raw material preparation process S10 is beaten to the coverlay pulling out and beat the rapid S20 that takes a step; Described coverlay is beaten to the lamination step S30 that plays the coverlay vacation of pulling out in the rapid S20 that takes a step and connect and be laminated to raw material single or double; Described vacation connect and the step S30 of lamination coverlay in the step S40 of lamination interlayer sticker (Prepreg) and copper (Copper) above the coverlay of lamination; In order to form BVH, at copper (Copper) the layer hole procedure of processing S50 of copper (Copper) machining hole of lamination; The step S60 of machining hole on interlayer sticker (Prepreg) layer exposing in described copper (Copper) layer hole procedure of processing S50; The BVH exposing is carried out to the de-smear step S70 of de-smear processing; And implement gold-plated gold-plated step S80 complete de-smear processing in described de-smear step S70 after.
Described raw material preparation process S10, after the raw material of volume (roll) state are cut with certain size, is covering the step that forms required circuit on raw-material Copper Foil.Described circuit utilizes resist corrosion (etching) Copper Foil of acid medicine and drug-resistant to form.
Described coverlay is beaten the rapid S20 that takes a step and is windowed and beat the step of pulling out in the upper part to gold-plated subsequently part and formation BVH of coverlay (Coverlay), beats interval operating type between the mode of pulling out, BVH complete with Laser operating type, mould.
Described Laser operating type can be implemented to beat the mode of pulling out tolerance more closely than mould, process when a small amount of more favourable aspect expense, the tolerance that produces 50um～70um while calculating a lateral deviation of BVH Size and Laser, calculating both sides needs about 100um～140um.
Described mould is beaten the mode of pulling out needs larger tolerance than Laser operating type, but more favourable aspect expense while processing volume, the tolerance that produces 100～200um while calculating a lateral deviation of BVH Size and Laser, calculating both sides needs about 200um～400um.
Between described BVH, interval operating type is to beat while there is not tolerance of interval (500um) between BVH in the mode of pulling out at mould, by each integration BVH and window (OPEN).
Described vacation connects and the step S30 of lamination coverlay carries out hot pressing at described raw-material substrate surface; connect and the step of lamination insulating barrier coverlay for the protection of the circuit vacation forming on Copper Foil, when described vacation connects technique and refers to lamination coverlay, for preventing from being laminated, pressure is pushed or distortion and the technique temporarily pasted.
The step S40 of sticker between described laminate layers (Prepreg) and copper (Copper) be described vacation connect and the step S30 of lamination coverlay in the step of lamination interlayer sticker (Prepreg) and copper (Copper) above the coverlay of lamination.
Described copper (Copper) layer hole procedure of processing S50 utilizes UV LASER to irradiate or the etching formation hole of exposing, the step that the surface of the interlayer adhering agent layer that is positioned at bottom surface is exposed to outside.
On described interlayer sticker (Prepreg) layer, the step S60 of machining hole is interlayer sticker (Prepreg) the layer irradiating laser to being arranged in described copper (Copper) the layer removed copper layer of hole procedure of processing S50 bottom surface, the step of machining hole on interlayer sticker (Prepreg) layer.
Described de-smear step S70 is in the time of machining hole, and the fusing of the resin of internal layer is flowed out and the inwall that is attached to hole hinders pasting of internal layer and by the step of chemical method elimination.
Described gold-plated step S80 is that the BVH inwall to exposing utilizes electrochemical method to cover the technique of copper, and the BVH of processing makes the inside/outside layer connecting become to be electrically connected the step of (conducting) thus.
Existing BVH Depth is the total thickness value of worthwhile copper (Copper) layer, interlayer sticker (Prepreg) layer and coverlay (Coverlay), but BVH Depth of the present invention beats and considers BVH size and off normal in pulling out operation and beat and pull out at coverlay (Coverlay), therefore in the time beating coverlay (Coverlay) the top lamination interlayer sticker (Prepreg) that pulls out and copper (Copper), there is not coverlay (Coverlay) in the part that forms BVH.Therefore, only there is no coverlay (Coverlay) in the region of BVH, and have coverlay (Coverlay) in other region, there is thus the gross thickness of meeting, can make the effect of the depth minimization of BVH simultaneously.
Above, various embodiments of the present invention is illustrated, but described embodiment just implements an embodiment of the technology of the present invention thought, every any modification or fixed case that realizes the technology of the present invention thought should belong to scope of the present invention.
The explanation > of the main pictorial symbolization of <
S10: raw material preparation process
S20: coverlay is beaten and taken a step suddenly
S30: vacation connects and the step of lamination coverlay
S40: the step of sticker between laminate layers (Prepreg) and copper (Copper)
S50: copper (Copper) layer hole procedure of processing
S60: the step of machining hole on interlayer sticker (Prepreg) layer
S70: de-smear step
S80: gold-plated step
Claims (1)
1. a Method for minimization for the printed circuit board (PCB) BVH degree of depth, is characterized in that comprising: the raw material of volume (roll) state cut the raw material preparation process S10 of rear formation circuit with certain size; The coverlay of the raw-material single or double lamination of preparing at described raw material preparation process S10 is beaten to the coverlay pulling out and beat the rapid S20 that takes a step; Described coverlay is beaten to the step S30 that plays the coverlay vacation of pulling out in the rapid S20 that takes a step and connect and be laminated to raw material single or double; Described vacation connect and the step S30 of lamination coverlay in the step S40 of lamination interlayer sticker (Prepreg) and copper (Copper) above the coverlay of lamination; In order to form BVH, utilize UV Ear Mucosa Treated by He Ne Laser Irradiation or the etching that exposes to form hole on the top of copper (Copper) layer of lamination, copper (Copper) the layer hole procedure of processing S50 that the surface of the interlayer adhering agent layer that is positioned at bottom surface is exposed to outside; The top of interlayer sticker (Prepreg) layer being exposed by the hole forming in described copper (Copper) layer hole procedure of processing S50 utilizes UV Ear Mucosa Treated by He Ne Laser Irradiation or the etching that exposes to form hole, makes the step S60 of machining hole on interlayer sticker (Prepreg) layer that the materials statement that is positioned at bottom surface exposes towards outside; The de-smear step S70 that the BVH of processing is carried out to de-smear processing; And implement gold-plated gold-plated step S80 complete de-smear processing in described de-smear step S70 after,
Wherein, described coverlay is beaten the rapid S20 that takes a step and is utilized Laser operating type, mould to beat between the mode of pulling out, BVH any one in the operating type of interval to carry out coverlay and beat and pull out, the both sides tolerance of considering the laser work mode needs of BVH Size and a lateral deviation is 100～140um, the both sides tolerance that mould is beaten the mode of pulling out to be needed is 200～400um, between BVH, interval operating type is to beat while there is not tolerance of interval (500um) between BVH in the mode of pulling out at mould, and each integration BVH is windowed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2012-0119522 | 2012-10-26 | ||
| KR1020120119522A KR101299258B1 (en) | 2012-10-26 | 2012-10-26 | The printed circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103796448A true CN103796448A (en) | 2014-05-14 |
| CN103796448B CN103796448B (en) | 2017-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310498762.4A Active CN103796448B (en) | 2012-10-26 | 2013-10-22 | The minimum method of printed circuit board (PCB) BVH depth |
Country Status (2)
| Country | Link |
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| KR (1) | KR101299258B1 (en) |
| CN (1) | CN103796448B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114018373B (en) * | 2021-10-28 | 2024-07-02 | 广州兴森快捷电路科技有限公司 | Method and system for measuring glue removal amount |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1226802A (en) * | 1998-01-14 | 1999-08-25 | 三井金属鈜业株式会社 | Method for producing multi-layer printed wiring boards having blind vias |
| KR20040058418A (en) * | 2002-12-26 | 2004-07-05 | 삼성전기주식회사 | Manufacturing method of rigid flexible printed circuit board for mobile phone |
| CN101098591A (en) * | 2006-06-26 | 2008-01-02 | 景硕科技股份有限公司 | Patterned method for tape coiling type thin object in automated process |
| CN101106872A (en) * | 1997-07-08 | 2008-01-16 | 伊比登株式会社 | Printed wiring board and method of producing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100722620B1 (en) | 2005-10-31 | 2007-05-28 | 삼성전기주식회사 | Rigid-flexible Print circuit board and method for manufacturing thereof |
| KR100751471B1 (en) | 2006-02-02 | 2007-08-23 | 영풍전자 주식회사 | Method for making window-open part of flexible printed circuit board |
| KR100894701B1 (en) | 2007-10-04 | 2009-04-24 | 삼성전기주식회사 | Rigid-flexible Print circuit board and method for manufacturing thereof |
-
2012
- 2012-10-26 KR KR1020120119522A patent/KR101299258B1/en active IP Right Grant
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2013
- 2013-10-22 CN CN201310498762.4A patent/CN103796448B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101106872A (en) * | 1997-07-08 | 2008-01-16 | 伊比登株式会社 | Printed wiring board and method of producing the same |
| CN1226802A (en) * | 1998-01-14 | 1999-08-25 | 三井金属鈜业株式会社 | Method for producing multi-layer printed wiring boards having blind vias |
| KR20040058418A (en) * | 2002-12-26 | 2004-07-05 | 삼성전기주식회사 | Manufacturing method of rigid flexible printed circuit board for mobile phone |
| CN101098591A (en) * | 2006-06-26 | 2008-01-02 | 景硕科技股份有限公司 | Patterned method for tape coiling type thin object in automated process |
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| Publication number | Publication date |
|---|---|
| CN103796448B (en) | 2017-03-01 |
| KR101299258B1 (en) | 2013-08-22 |
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