CN103762156A - Manufacturing method of semiconductor substrate, semiconductor substrate and high-voltage transistor - Google Patents
Manufacturing method of semiconductor substrate, semiconductor substrate and high-voltage transistor Download PDFInfo
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- CN103762156A CN103762156A CN201310745388.3A CN201310745388A CN103762156A CN 103762156 A CN103762156 A CN 103762156A CN 201310745388 A CN201310745388 A CN 201310745388A CN 103762156 A CN103762156 A CN 103762156A
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- 239000000758 substrate Substances 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 21
- 230000001351 cycling effect Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 11
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a manufacturing method of a semiconductor substrate, the semiconductor substrate and a high-voltage transistor. The high-voltage transistor is manufactured on the surface of the semiconductor substrate with an insulating layer, the semiconductor substrate comprises a supporting substrate body, an insulating buried layer on the surface of the supporting substrate body and a device layer on the surface of the insulating buried layer, the high-voltage transistor is formed on the surface of the device layer, and the supporting substrate body comprises an auxiliary depletion layer which is formed by piling a P-type semiconductor layer and an N-type semiconductor layer alternately. The manufacturing method has the advantages that the auxiliary depletion layer which is formed by piling the P-type semiconductor layer and the N-type semiconductor layer alternately is arranged in the supporting substrate body, the auxiliary depletion effect of the substrate body can be effectively restrained, and voltage endurance capability of devices is improved.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to a kind of manufacture method, Semiconductor substrate and high voltage transistor of Semiconductor substrate.
Background technology
Power integrated circuit also claims high voltage integrated circuit sometimes, it is the important branch that hyundai electronics is learned, can be various power conversions and energy processing unit provides the new-type circuit of high speed, high integration, low-power consumption and anti-irradiation, is widely used in many key areas such as the current consumption fields such as electric control system, automotive electronics, display device driving, communication and illumination and national defence, space flight.The rapid expansion of its range of application, also has higher requirement to the high tension apparatus of its core.
For power transistor, guaranteeing that under the prerequisite of puncture voltage, the conducting resistance that must reduce as much as possible device improves device performance.But between puncture voltage and conducting resistance, exist so-called " silicon limit ".In order to solve this contradiction, forefathers proposed drift region based on three-dimensional RESURF technology by P, the alternate super-junction structure forming of N post for optimizing the drift region Electric Field Distribution of high tension apparatus.The theoretical foundation of this technology is charge compensation theory, and when drift region applies voltage and reaches certain value, drift region reaches completely and exhausts, and Electric Field Distribution is more even, has improved the breakdown characteristics of device.Guaranteeing, under the constant prerequisite of puncture voltage, can significantly to improve the doping content of drift region, reduce conducting resistance.Conventional power MOSFET device " the silicon limit " has been broken in the proposition of super-junction structure.
Super-junction structure is applied to VDMOS device at first, expands to afterwards LDMOS device.Transversary is more conducive to the integrated application of high-density power of new generation, is the focus of contemporary power device research.When but super-junction structure is used for the transversal device of SOI substrate, due to the existence of " support substrates-oxygen buried layer-top layer silicon " capacitance structure, make substrate participate in exhausting of Chao Jiezhu district, cause occurring so-called " substrate-assisted depletion effect ", and the width of depletion layer is not at the drain terminal of device to the diverse location of source direction etc., the problem that this has just brought drift region Electric Field Distribution inequality, has had a strong impact on device withstand voltage, has reduced process allowance.
Forming at present the horizontal super-junction structure of n ditch, is mainly repeatedly that Implantation forms column p district in N-shaped drift region.Extenuate substrate-assisted depletion effect and also propose several different methods, as extra increase N-shaped layer, adopt Sapphire Substrate or etched substrate etc.
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of with the high voltage transistor on insulating buried layer substrate, can effectively suppress substrate-assisted depletion effect.
In order to address the above problem, the invention provides a kind of manufacture method of Semiconductor substrate, comprise the steps: to provide support substrate, described support substrates consists of the semi-conducting material with the first conduction type; On support substrates surface, form groove; Fill the semi-conducting material with the second conduction type in described groove, form and along the direction that is parallel to support substrates surface, replace the stacking assisted depletion layer forming by the first conductive type semiconductor layer and second conductive type semiconductor layer; On the surface of assisted depletion layer, continue to form insulating barrier; At described surface of insulating layer, form device layer.
Optionally, before forming insulating barrier, further comprise the step that planarization is carried out in the fluted surface of described support substrates tool.
The present invention also provides a kind of manufacture method of Semiconductor substrate, comprises the steps: to provide support substrate, and described support substrates consists of the semi-conducting material with the first conduction type; At support substrates surface cycling deposition, there is the semiconductor layer of the second conduction type and the first conduction type, cycle-index is at least once, to form by the first conductive type semiconductor layer and second conductive type semiconductor layer along replace the stacking assisted depletion layer forming perpendicular to the direction on support substrates surface; On the surface of assisted depletion layer, continue to form insulating barrier; At described surface of insulating layer, form device layer.
The present invention further provides a kind of Semiconductor substrate, comprise the insulating buried layer on support substrates, support substrates surface and the device layer on insulating buried layer surface, described support substrates comprises an assisted depletion layer, and described assisted depletion layer is replaced and stackingly formed by p type semiconductor layer and n type semiconductor layer.
Optionally, described p type semiconductor layer and n type semiconductor layer are stacking along the direction that is parallel to substrate surface.
Optionally, described p type semiconductor layer and n type semiconductor layer are stacking along the direction perpendicular to substrate surface.
Optionally, in described assisted depletion layer, at least comprise the two-layer p type semiconductor layer and the two-layer n type semiconductor layer that replace each other stacking setting.
The present invention further provides a kind of high voltage transistor, be formed at the semiconductor substrate surface with insulating buried layer, described Semiconductor substrate comprises the insulating buried layer on support substrates, support substrates surface and the device layer on insulating buried layer surface, described high voltage transistor is formed on the surface of device layer, it is characterized in that, described support substrates comprises an assisted depletion layer, and described assisted depletion layer is replaced and stackingly formed by p type semiconductor layer and n type semiconductor layer.
Optionally, described p type semiconductor layer and n type semiconductor layer are stacking along the direction that is parallel to substrate surface, and described assisted depletion layer is arranged in the support substrates corresponding with the drift region of described high voltage transistor.
The invention has the advantages that, by arranging and replace the stacking assisted depletion layer forming by p type semiconductor layer and n type semiconductor layer, can effectively suppress substrate-assisted depletion effect in support substrates, improve device withstand voltage ability.
Accompanying drawing explanation
It shown in accompanying drawing 1, is the implementation step schematic diagram of method described in the present invention's the first embodiment.
Accompanying drawing 2A is to shown in accompanying drawing 2E being the process schematic representation of the present invention's the first embodiment.
Shown in accompanying drawing 3, be to adopt the Semiconductor substrate that the first embodiment obtains to make the structural representation after device.
It shown in accompanying drawing 4, is the implementation step schematic diagram of method described in the present invention's the second embodiment.
Accompanying drawing 5A is to shown in accompanying drawing 5D being the process schematic representation of the present invention's the second embodiment.
Shown in accompanying drawing 6, be to adopt the Semiconductor substrate that the second embodiment obtains to make the structural representation after device.
Embodiment
Below in conjunction with accompanying drawing, the embodiment with the high voltage transistor on insulating buried layer substrate provided by the invention is elaborated.
First by reference to the accompanying drawings provide first embodiment of the method for the invention.
Shown in accompanying drawing 1, be the implementation step schematic diagram of method described in this embodiment, comprise: step S10, provide support substrate, described support substrates consists of the semi-conducting material with the first conduction type; Step S11, forms groove on support substrates surface; Step S12 fills the semi-conducting material with the second conduction type in described groove, forms and along the direction that is parallel to support substrates surface, replaces the stacking assisted depletion layer forming by the first conductive type semiconductor layer and second conductive type semiconductor layer; Step S13 continues to form insulating barrier on the surface of assisted depletion layer; Step S14, forms device layer at described surface of insulating layer.
Accompanying drawing 2A is to shown in accompanying drawing 2E being the process schematic representation of this embodiment.
Shown in accompanying drawing 2A, refer step S10, provides support substrate 230, and described support substrates consists of the semi-conducting material with the first conduction type.The material of described support substrates 230 can be for example monocrystalline silicon, and described the first conduction type can be N-type or P type.
Shown in accompanying drawing 2B, refer step S11, forms groove 240 on support substrates 230 surfaces.The method that forms groove 240 can be for example by the method for photoetching and etching.
Shown in accompanying drawing 2C, refer step S12, in the interior filling of described groove 240, there is the semi-conducting material of the second conduction type, form and along the direction that is parallel to support substrates 230 surfaces, replace the stacking assisted depletion layer 231 forming by the first conductive type semiconductor layer 2311 and second conductive type semiconductor layer 2312.The semi-conducting material of described the second conduction type can be the materials such as monocrystalline silicon, can be identical from the material of support substrates 230 or different, and be preferably identical.Filling can select epitaxy technique to realize.
Shown in accompanying drawing 2D, refer step S13 continues to form insulating barrier 220 on the surface of assisted depletion layer 231.Preferably silica of the material of described insulating barrier 220, and adopt thermal oxidation method to be formed in monocrystalline substrate.Before forming insulating barrier 220, can also further to the surface of assisted depletion layer 231, implement planarization, be beneficial to subsequent technique.
Shown in accompanying drawing 2E, refer step S14, forms device layer 210 on described insulating barrier 220 surfaces.Described device layer 210 is for making semiconductor device.Due to the effect of assisted depletion layer 231, therefore on described device layer 210 surfaces, make high tension apparatus and can obtain better electrology characteristic.The technique that forms device layer 210 can be for example bonding attenuate.
Semiconductor substrate after above-mentioned embodiment is implemented is as shown in accompanying drawing 2E.Comprise the insulating buried layer 220 on support substrates 230, support substrates 230 surfaces and the device layer 210 on insulating buried layer 220 surfaces.Described support substrates 230 comprises an assisted depletion layer 231, and described assisted depletion layer the first conductive type semiconductor layer 2311 and second conductive type semiconductor layer 2312 replace stacking formation along the direction that is parallel to support substrates 230 surfaces.
Shown in accompanying drawing 3, be to adopt the Semiconductor substrate that above-mentioned embodiment obtains to make the structural representation after device.Described Semiconductor substrate comprises the insulating barrier 220 on support substrates 230, support substrates 230 surfaces and the device layer 210 on insulating barrier 220 surfaces.Described high voltage transistor is formed on the surface of device layer 210, comprise the P trap 314 for limits source 311 in grid 313 between 312 of source electrode 311, drain electrode 312, source electrode 311 and drain electrode, device layer, and the drift region 315 between grid 313 and drain electrode 313.Described drift region 315 can comprise along the assorted post of the P type being arranged alternately perpendicular to page and N-type doped column (not shown), form super-junction structure.
In this embodiment, support substrates 230 comprises an assisted depletion layer 231, and described assisted depletion layer 231 is stacking along the direction that is parallel to substrate surface by p type semiconductor layer and n type semiconductor layer.Continuation is with reference to accompanying drawing 3, and for example the first conductive type semiconductor layer 2311 can be p type semiconductor layer, and second conductive type semiconductor layer 2312 can be n type semiconductor layer, or contrary.P type semiconductor layer in assisted depletion layer 231 and n type semiconductor layer can exhaust mutually, thereby reduce " substrate-assisted depletion effect " in the device course of work, suppressing " support substrates 230-insulating barrier 220-device layer 210 " parasitic capacitance structure forming affects the charge balance of top device drift region 315.In described assisted depletion layer 231, at least comprise the two-layer p type semiconductor layer and the two-layer n type semiconductor layer that replace each other stacking setting, to improve assisted depletion effect.
Secondly provide by reference to the accompanying drawings second embodiment of the method for the invention.
Shown in accompanying drawing 4, be the implementation step schematic diagram of method described in this embodiment, comprise: step S40, provide support substrate, described support substrates consists of the semi-conducting material with the first conduction type; Step S41, at support substrates surface cycling deposition, there is the semiconductor layer of the second conduction type and the first conduction type, cycle-index is at least once, to form by the first conductive type semiconductor layer and second conductive type semiconductor layer along replace the stacking assisted depletion layer forming perpendicular to the direction on support substrates surface; Step S42 continues to form insulating barrier on the surface of assisted depletion layer; Step S43, forms device layer at described surface of insulating layer.
Accompanying drawing 5A is to shown in accompanying drawing 5D being the process schematic representation of this embodiment.
Shown in accompanying drawing 5A, refer step S40, provides support substrate 530, and described support substrates consists of the semi-conducting material with the first conduction type.The material of described support substrates 530 can be for example monocrystalline silicon, and described the first conduction type can be N-type or P type.
Shown in accompanying drawing 5B, refer step S41, at the surperficial cycling deposition of support substrates 530, there is the semiconductor layer of the second conduction type and the first conduction type, cycle-index is at least once, to form by the first conductive type semiconductor layer 5311 and second conductive type semiconductor layer 5312 along replace the stacking assisted depletion layer 531 forming perpendicular to the direction on support substrates 530 surfaces.Grow the first conductive type semiconductor layer 5311 and second conductive type semiconductor layer 5312 can adopt the method for extension.
Shown in accompanying drawing 5C, refer step S42 continues to form insulating barrier 520 on the surface of assisted depletion layer 531.Preferably silica of the material of described insulating barrier 520, and adopt thermal oxidation method to be formed in monocrystalline substrate.
Shown in accompanying drawing 5D, refer step S43, forms device layer 510 on described insulating barrier 520 surfaces.Described device layer 510 is for making semiconductor device.Due to the effect of assisted depletion layer 531, therefore on described device layer 510 surfaces, make high tension apparatus and can obtain better electrology characteristic.The technique that forms device layer 510 can be for example bonding attenuate.
Semiconductor substrate after above-mentioned embodiment is implemented is as shown in accompanying drawing 5D.Comprise the insulating buried layer 520 on support substrates 530, support substrates 530 surfaces and the device layer 510 on insulating buried layer 520 surfaces.Described support substrates 530 comprises an assisted depletion layer 531, and described assisted depletion layer the first conductive type semiconductor layer 5311 and second conductive type semiconductor layer 5312 are along replacing stacking formation perpendicular to the direction on support substrates 530 surfaces.
Shown in accompanying drawing 6, be to adopt the Semiconductor substrate that above-mentioned embodiment obtains to make the structural representation after device.Described Semiconductor substrate comprises the insulating barrier 520 on support substrates 530, support substrates 530 surfaces and the device layer 510 on insulating barrier 520 surfaces.Described high voltage transistor is formed on the surface of device layer 510, comprise the P trap 614 for limits source 611 in grid 613 between 612 of source electrode 611, drain electrode 612, source electrode 611 and drain electrode, device layer, and the drift region 615 between grid 613 and drain electrode 612.Described drift region 615 can comprise along the assorted post of the P type being arranged alternately perpendicular to page and N-type doped column (not shown), form super-junction structure.
In this embodiment, support substrates 530 comprises an assisted depletion layer 531, and described assisted depletion layer 531 is stacking along the direction that is parallel to substrate surface by p type semiconductor layer and n type semiconductor layer.Continuation is with reference to accompanying drawing 6, and for example 5311 can be n type semiconductor layer, and 5312 can be p type semiconductor layer, or contrary.P type semiconductor layer in assisted depletion layer 531 and n type semiconductor layer can exhaust mutually, thereby reduce " substrate-assisted depletion effect " in the device course of work, suppressing " support substrates 530-insulating barrier 520-device layer 510 " parasitic capacitance structure forming affects the charge balance of top device drift region 615.In described assisted depletion layer 531, at least comprise the two-layer p type semiconductor layer and the two-layer n type semiconductor layer that replace each other stacking setting, to improve assisted depletion effect.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a manufacture method for Semiconductor substrate, is characterized in that, comprises the steps:
Provide support substrate, described support substrates consists of the semi-conducting material with the first conduction type;
On support substrates surface, form groove;
In described groove, fill the semi-conducting material with the second conduction type, form and along the direction that is parallel to support substrates surface, replace the stacking assisted depletion layer forming by the first conductive type semiconductor layer and second conductive type semiconductor layer;
On the surface of assisted depletion layer, continue to form insulating barrier;
At described surface of insulating layer, form device layer.
2. the manufacture method of Semiconductor substrate according to claim 1, is characterized in that, before forming insulating barrier, further comprises the step that planarization is carried out in the fluted surface of described support substrates tool.
3. a manufacture method for Semiconductor substrate, is characterized in that, comprises the steps:
Provide support substrate, described support substrates consists of the semi-conducting material with the first conduction type;
At support substrates surface cycling deposition, there is the semiconductor layer of the second conduction type and the first conduction type, cycle-index is at least once, to form by the first conductive type semiconductor layer and second conductive type semiconductor layer along replace the stacking assisted depletion layer forming perpendicular to the direction on support substrates surface;
On the surface of assisted depletion layer, continue to form insulating barrier;
At described surface of insulating layer, form device layer.
4. a Semiconductor substrate, comprise the insulating buried layer on support substrates, support substrates surface and the device layer on insulating buried layer surface, it is characterized in that, described support substrates comprises an assisted depletion layer, and described assisted depletion layer is replaced and stackingly formed by p type semiconductor layer and n type semiconductor layer.
5. Semiconductor substrate according to claim 4, is characterized in that, described p type semiconductor layer and n type semiconductor layer are stacking along the direction that is parallel to substrate surface.
6. Semiconductor substrate according to claim 4, is characterized in that, described p type semiconductor layer and n type semiconductor layer are stacking along the direction perpendicular to substrate surface.
7. Semiconductor substrate according to claim 4, is characterized in that, at least comprises the two-layer p type semiconductor layer and the two-layer n type semiconductor layer that replace each other stacking setting in described assisted depletion layer.
8. a high voltage transistor, be formed at the semiconductor substrate surface with insulating buried layer, described Semiconductor substrate comprises the insulating buried layer on support substrates, support substrates surface and the device layer on insulating buried layer surface, described high voltage transistor is formed on the surface of device layer, it is characterized in that, described support substrates comprises an assisted depletion layer, and described assisted depletion layer is replaced and stackingly formed by p type semiconductor layer and n type semiconductor layer.
9. high voltage transistor according to claim 8, it is characterized in that, described p type semiconductor layer and n type semiconductor layer are stacking along the direction that is parallel to substrate surface, and described assisted depletion layer is arranged in the support substrates corresponding with the drift region of described high voltage transistor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114122114A (en) * | 2022-01-28 | 2022-03-01 | 微龛(广州)半导体有限公司 | Semiconductor structure, device and preparation method thereof |
| CN115831941A (en) * | 2023-02-10 | 2023-03-21 | 微龛(广州)半导体有限公司 | Thin film resistor structure |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020060330A1 (en) * | 2000-07-12 | 2002-05-23 | Yasuhiko Onishi | Bidirectional semiconductor device and method of manufacturing the same |
| US6504176B2 (en) * | 2000-04-06 | 2003-01-07 | Matshushita Electric Industrial Co., Ltd. | Field effect transistor and method of manufacturing the same |
| CN1845332A (en) * | 2006-03-21 | 2006-10-11 | 电子科技大学 | SOI structure with low k dielectric buried layer and its power device |
| CN1864269A (en) * | 2002-05-21 | 2006-11-15 | 皇家飞利浦电子股份有限公司 | SOI-LDMOS device |
| CN1901226A (en) * | 2002-03-27 | 2007-01-24 | 株式会社东芝 | Field effect transistor and application device thereof |
| CN101095235A (en) * | 2004-12-28 | 2007-12-26 | 皇家飞利浦电子股份有限公司 | SOI device |
| CN101488525A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | P type SOI lateral double-diffused metal-oxide semiconductor transistor |
| CN101515586A (en) * | 2008-02-21 | 2009-08-26 | 中国科学院微电子研究所 | Radio frequency SOI LDMOS device with close body contact |
| CN102306659A (en) * | 2011-09-08 | 2012-01-04 | 浙江大学 | LDMOS (laterally double-diffused metal-oxide-semiconductor field effect transistor) device based on internal electric field modulation |
| CN103022087A (en) * | 2011-09-26 | 2013-04-03 | 朱江 | Semiconductor chip and production method thereof |
| CN103400797A (en) * | 2013-08-15 | 2013-11-20 | 上海新傲科技股份有限公司 | Preparation method of semiconductor substrate with cavity |
-
2013
- 2013-12-31 CN CN201310745388.3A patent/CN103762156A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6504176B2 (en) * | 2000-04-06 | 2003-01-07 | Matshushita Electric Industrial Co., Ltd. | Field effect transistor and method of manufacturing the same |
| US20020060330A1 (en) * | 2000-07-12 | 2002-05-23 | Yasuhiko Onishi | Bidirectional semiconductor device and method of manufacturing the same |
| CN1901226A (en) * | 2002-03-27 | 2007-01-24 | 株式会社东芝 | Field effect transistor and application device thereof |
| CN1864269A (en) * | 2002-05-21 | 2006-11-15 | 皇家飞利浦电子股份有限公司 | SOI-LDMOS device |
| CN101095235A (en) * | 2004-12-28 | 2007-12-26 | 皇家飞利浦电子股份有限公司 | SOI device |
| CN1845332A (en) * | 2006-03-21 | 2006-10-11 | 电子科技大学 | SOI structure with low k dielectric buried layer and its power device |
| CN101515586A (en) * | 2008-02-21 | 2009-08-26 | 中国科学院微电子研究所 | Radio frequency SOI LDMOS device with close body contact |
| CN101488525A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | P type SOI lateral double-diffused metal-oxide semiconductor transistor |
| CN102306659A (en) * | 2011-09-08 | 2012-01-04 | 浙江大学 | LDMOS (laterally double-diffused metal-oxide-semiconductor field effect transistor) device based on internal electric field modulation |
| CN103022087A (en) * | 2011-09-26 | 2013-04-03 | 朱江 | Semiconductor chip and production method thereof |
| CN103400797A (en) * | 2013-08-15 | 2013-11-20 | 上海新傲科技股份有限公司 | Preparation method of semiconductor substrate with cavity |
Non-Patent Citations (1)
| Title |
|---|
| 成建兵: "SJ-LDMOST中的衬底辅助耗尽效应", 《电子产品世界》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114122114A (en) * | 2022-01-28 | 2022-03-01 | 微龛(广州)半导体有限公司 | Semiconductor structure, device and preparation method thereof |
| CN115831941A (en) * | 2023-02-10 | 2023-03-21 | 微龛(广州)半导体有限公司 | Thin film resistor structure |
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