CN103745987A - 一种场限环-负斜角复合终端结构 - Google Patents

一种场限环-负斜角复合终端结构 Download PDF

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CN103745987A
CN103745987A CN201310695943.6A CN201310695943A CN103745987A CN 103745987 A CN103745987 A CN 103745987A CN 201310695943 A CN201310695943 A CN 201310695943A CN 103745987 A CN103745987 A CN 103745987A
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王彩琳
王一宇
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Xian University of Technology
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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Abstract

本发明公开了一种场限环-负斜角复合终端结构，将芯片的中央区域作为有源区，将有源区外围区域作为终端区，有源区和终端区共同的n-衬底下方设置有n型FS层，在n型FS层下方设置有p+阳极区及阳极；有源区中，n-基区中设置有多个并联的单元，每个单元内与n-基区相邻的是波状p基区，p基区上面为p+基区，p+基区中央设置有一个阴极n+发射区，每个n+发射区上方设有阴极；p+基区上方设有门极，并且整个门极环绕在所包围的阴极n+发射区的周围；在终端区的n-衬底内，在主结外侧设了至少一个p型场限环，并在场限环上面有一个负斜角，斜面上覆有钝化层。本发明的场限环-负斜角复合终端结构具有更好的高温稳定性。

Description

一种场限环-负斜角复合终端结构
技术领域
本发明属于电力半导体器件技术领域，涉及一种场限环-负斜角复合终端结构。
背景技术
在电力半导体器件的开发过程中，终端结构的设置会直接影响电力半导体器件的耐压及其稳定性。门极换流晶闸管（GCT）是基于门极可关断晶闸管（GTO）而开发的一种新型大功率半导体器件，为了提高GCT终端击穿电压，通常采用类似于普通晶闸管的台面终端结构或横向变掺杂（VLD）结构。台面终端结构采用机械磨角及腐蚀工艺形成，制作工艺比较成熟，但它能实现的终端击穿电压只有其体内击穿电压的80%，并且其高温漏电流及终端所占的芯片面积很大。横向变掺杂结构是采用渐变的扩散窗口进行铝注入形成，能使器件的终端击穿电压达到其体内击穿电压的90%，但终端所占的芯片面积也很大，并且形成渐变掺杂所需的光刻窗口较难控制。
可见，现有的终端技术都不能有效地提高器件的终端击穿电压和芯片的利用率，从而限制了高压大功率器件的开发。
发明内容
本发明的目的是提供一种场限环-负斜角复合终端结构，解决了现有的高压深结器件结终端电压低、高温稳定性差及终端占用芯片面积大的问题。
本发明所采用的技术方案是，一种场限环-负斜角复合终端结构，将芯片的中央区域作为有源区，将有源区外围区域作为终端区，有源区和终端区共同的n-衬底下方设置有n型FS层，在n型FS层下方设置有p+阳极区及其阳极；在有源区中，n-基区中设置有多个并联的单元，每个单元内与n-基区相邻的是波状p基区，p基区上面为p+基区，p+基区中央设置有一个阴极n+发射区，每个n+发射区上方设置有阴极；p+基区上方设置有门极，并且整个门极环绕在所包围的阴极n+发射区的周围；在终端区的n-衬底内，在主结外侧设置了至少一个p型场限环，并且在场限环上面有一个负斜角，使得终端区上表面为斜面，斜面上覆有钝化层。
本发明的场限环-负斜角复合终端结构，其特征还在于：
终端区有一级或两级场限环，主结与第一级场限环的间距s1为260～350μm，第一级场限环与第二级场限环的间距s2为130～145μm。
终端区的场限环上方有一负斜角，所述负斜角的角度为2.5°～3.5°。
所述的钝化层为聚酰亚胺或硅胶。
本发明的有益效果是，采用此复合终端结构可获得95.7%的体击穿电压，与具有相同角度和终端尺寸的传统负斜角终端相比，此复合终端的击穿电压可提高22%，并且高温稳定性好。
附图说明
图1是本发明的复合终端结构的截面示意图；
图2是本发明的复合终端结构击穿时的纵向电场分布曲线图；
图3是本发明的复合终端结构空间电荷区的展宽剖面图；
图4是终端击穿电压随负斜角角度θ的变化曲线；
图5是终端击穿电压随主结与第1环结间距s1的变化曲线；
图6是终端击穿电压随第1环与第2环之间的环间距s2的变化曲线；
图7是采用本发明的复合终端结构的波状基区GCT器件击穿特性模拟曲线。
具体实施方式
下面结合附图和具体实施方式对本发明进行详细说明。
参照图1，本发明的场限环-负斜角复合终端结构，用于波状基区GCT器件制备，其具体结构设置是：
将芯片的中央区域作为有源区，将有源区外围区域作为终端区，有源区和终端区共同的n-衬底下方设置有n型FS层，在n型FS层下方设置有p+阳极区及其阳极（即底部位置）；
在有源区中，n-基区中设置有多个并联的单元，每个单元内与n-基区相邻的是波状p基区，p基区上面为p+基区，p+基区中央设置有一个阴极n+发射区，每个n+发射区上方设置有阴极；p+基区上方设置有门极，并且整个门极环绕在所包围的阴极n+发射区的周围；
在终端区的n-衬底内，在主结外侧设置了至少一个p型场限环，并且在场限环上面有一个负斜角，使得终端区上表面为斜面，斜面上覆有钝化层，该表面的钝化层选用聚酰亚胺或硅胶。
场限环与有源区内的波状基区同时形成；终端区有一级或两级场限环，主结与第一级场限环的间距s1为260～350μm，第一级场限环与第二级场限环的间距s2为130～145μm；终端区的场限环上方有一负斜角，所述负斜角的角度为2.5°～3.5°。
本发明的复合终端结构，其耐压机理是：
通过在主结末端设置至少一个p型场限环，增加了主结末端处耗尽层的曲率半径，缓解表面电场集中，并且场限环的数目、环间距及斜角的变化均会影响空间电荷区的电荷量，使空间电荷区展宽发生变化，从而改善表面电场分布，提高终端耐压。
图2是本发明的复合终端结构击穿时的纵向电场分布曲线图，由图2可见，在主结末端处（x=100μm）、第一个场限环末端处（x=495μm）及第二个场限环末端处（x=810μm）分别形成了三个电场强度相近的峰值电场，其中第一场限环处的电场稍低，第二个场限环与主结处的电场非常接近，击穿将会在这两处同时发生。图3是本发明的复合终端结构空间电荷区的展宽剖面图。由图可见，当负斜角的角度θ为3.5°、s1为274μm、s2为138μm时，此时空间电荷区从100μm处展宽到1420μm，对应的终端尺寸为1320μm，击穿电压最高可达5041V。
通过选择合理的结构参数，能够将表面的最高电场转移到体内，使击穿稳定地发生在体内；同时使器件击穿时所需的空间电荷区展宽尽可能小，以减小终端尺寸。为了优选本发明复合终端的最佳结构参数，以5kV的GCT器件为例，分析了各项结构参数对器件击穿电压的影响。图4-图6是采用本发明的复合终端结构波状基区GCT器件终端击穿电压与空间电荷区展宽随各个关键参数的变化曲线。由图4可见，随负斜角角度的增大，终端击穿电压先增大后快速减小，空间电荷区展宽呈线性减小；由图5可见，随主结与第1环结间距s1的增大，终端击穿电压先快速增大后基本不变，空间电荷区展宽则呈线性增大；由图6可见，随第1环与第2环间距s2的增大，终端击穿电压先增加而后就减小，空间电荷区展宽逐渐增大。
本发明的适用于波状基区GCT器件的复合终端结构，在常温（300K）和高温（420K）下击穿特性的模拟曲线如图7所示，由图7可见，GCT器件体内平行平面结的击穿电压约为5290V，采用场限环-负斜角复合终端结构至少可获得约5041～5064V的终端击穿电压，约为其体内平行平面结击穿电压的95%以上，对应的终端尺寸在1.32～1.62mm范围内。与具有相同负斜角和终端尺寸的传统负斜角终端结构相比，常温下的终端击穿电压可提高约22%，并且高温下的终端击穿电压更高、漏电流密度更低。所以，本发明的场限环-负斜角复合终端结构具有更好的高温稳定性。该终端结构还可以推广到逆导型GCT器件中。

Claims (4)

1.一种场限环-负斜角复合终端结构，其特征在于：
将芯片的中央区域作为有源区，将有源区外围区域作为终端区，有源区和终端区共同的n-衬底下方设置有n型FS层，在n型FS层下方设置有p+阳极区及其阳极；
在有源区中，n-基区中设置有多个并联的单元，每个单元内与n-基区相邻的是波状p基区，p基区上面为p+基区，p+基区中央设置有一个阴极n+发射区，每个n+发射区上方设置有阴极；p+基区上方设置有门极，并且整个门极环绕在所包围的阴极n+发射区的周围；
在终端区的n-衬底内，在主结外侧设置了至少一个p型场限环，并且在场限环上面有一个负斜角，使得终端区上表面为斜面，斜面上覆有钝化层。
2.根据权利要求1所述的场限环-负斜角复合终端结构，其特征在于：终端区有一级或两级场限环，主结与第一级场限环的间距s1为260～350μm，第一级场限环与第二级场限环的间距s2为130～145μm。
3.根据权利要求1所述的场限环-负斜角复合终端结构，其特征在于：终端区的场限环上方有一负斜角，所述负斜角的角度为2.5°～3.5°。
4.根据权利要求1所述的场限环-负斜角复合终端结构，其特征在于：所述的钝化层为聚酰亚胺或硅胶。
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CN107910360A (zh) * 2017-12-06 2018-04-13 中国工程物理研究院电子工程研究所 一种新型碳化硅小角度倾斜台面终端结构及其制备方法
CN115084231A (zh) * 2022-07-19 2022-09-20 浙江大学 一种二极管及其制造方法
CN117790537A (zh) * 2023-12-28 2024-03-29 深圳平湖实验室 一种半导体器件、其制作方法及电子器件

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