CN103718285B - 应用导电颗粒的低应力tsv设计 - Google Patents

应用导电颗粒的低应力tsv设计 Download PDF

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Publication number
CN103718285B
CN103718285B CN201280037494.XA CN201280037494A CN103718285B CN 103718285 B CN103718285 B CN 103718285B CN 201280037494 A CN201280037494 A CN 201280037494A CN 103718285 B CN103718285 B CN 103718285B
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metal
conductive
particles
microelectronic component
substrate
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Chinese (zh)
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CN103718285A (zh
Inventor
C·G·沃伊奇克
K·德赛
伊利亚斯·默罕默德
T·卡斯基
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0094Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • B23K1/0008Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016Brazing of electronic components
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/36Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
CN201280037494.XA 2011-06-09 2012-06-07 应用导电颗粒的低应力tsv设计 Active CN103718285B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/156,609 2011-06-09
US13/156,609 US8723049B2 (en) 2011-06-09 2011-06-09 Low-stress TSV design using conductive particles
PCT/US2012/041247 WO2012170625A1 (en) 2011-06-09 2012-06-07 Low-stress tsv design using conductive particles

Publications (2)

Publication Number Publication Date
CN103718285A CN103718285A (zh) 2014-04-09
CN103718285B true CN103718285B (zh) 2017-02-15

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US (2) US8723049B2 (enExample)
EP (1) EP2718968A1 (enExample)
JP (1) JP5941983B2 (enExample)
KR (1) KR20140053946A (enExample)
CN (1) CN103718285B (enExample)
TW (1) TWI493670B (enExample)
WO (1) WO2012170625A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816505B2 (en) 2011-07-29 2014-08-26 Tessera, Inc. Low stress vias
JP5099272B1 (ja) * 2011-12-26 2012-12-19 パナソニック株式会社 多層配線基板とその製造方法
TW201340807A (zh) * 2011-12-28 2013-10-01 松下電器產業股份有限公司 撓性配線基板與其製造方法、使用其之裝載製品、及撓性多層配線基板
CN103314652A (zh) * 2012-01-17 2013-09-18 松下电器产业株式会社 配线基板及其制造方法
EP2883430B1 (en) * 2012-08-10 2022-10-05 Telefonaktiebolaget LM Ericsson (publ) A printed circuit board arrangement and a method for forming electrical connection at a printed circuit board
US8809181B2 (en) * 2012-11-07 2014-08-19 Intel Corporation Multi-solder techniques and configurations for integrated circuit package assembly
US8933564B2 (en) * 2012-12-21 2015-01-13 Intel Corporation Landing structure for through-silicon via
CN203707402U (zh) * 2013-12-05 2014-07-09 番禺得意精密电子工业有限公司 电连接器
KR20160046621A (ko) * 2014-10-21 2016-04-29 삼성전자주식회사 반도체 칩 패키지 테스트용 테스트 소켓 및 이의 제조 방법
US9731384B2 (en) 2014-11-18 2017-08-15 Baker Hughes Incorporated Methods and compositions for brazing
US9397048B1 (en) * 2015-03-23 2016-07-19 Inotera Memories, Inc. Semiconductor structure and manufacturing method thereof
US10070533B2 (en) * 2015-09-30 2018-09-04 3D Glass Solutions, Inc. Photo-definable glass with integrated electronics and ground plane
TW202529282A (zh) * 2016-11-18 2025-07-16 美商山姆科技公司 用於填充之無鉛材料及導電組件
US9941210B1 (en) * 2016-12-27 2018-04-10 Nxp Usa, Inc. Semiconductor devices with protruding conductive vias and methods of making such devices
US10224301B2 (en) * 2017-07-05 2019-03-05 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
WO2019032846A1 (en) * 2017-08-10 2019-02-14 Molex, Llc METHOD AND APPARATUS FOR FORMING AN ELECTRICAL CIRCUIT COMPRISING ALUMINUM AND ONE OR MORE DISSOLVABLE METALS
WO2019191621A1 (en) 2018-03-30 2019-10-03 Samtec, Inc. Electrically conductive vias and methods for producing same
KR102511200B1 (ko) 2018-06-27 2023-03-17 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN109470699A (zh) * 2018-10-15 2019-03-15 北京工业大学 一种tsv电镀铜填充效果的测试方法
US12100647B2 (en) * 2019-09-30 2024-09-24 Samtec, Inc. Electrically conductive vias and methods for producing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684256A (zh) * 2003-12-05 2005-10-19 国际商业机器公司 具有导电穿透通道的硅芯片载体及其制造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624741A (en) * 1990-05-31 1997-04-29 E. I. Du Pont De Nemours And Company Interconnect structure having electrical conduction paths formable therein
US5540379A (en) * 1994-05-02 1996-07-30 Motorola, Inc. Soldering process
JP3311899B2 (ja) * 1995-01-20 2002-08-05 松下電器産業株式会社 回路基板及びその製造方法
US5573859A (en) * 1995-09-05 1996-11-12 Motorola, Inc. Auto-regulating solder composition
US6143116A (en) * 1996-09-26 2000-11-07 Kyocera Corporation Process for producing a multi-layer wiring board
US6286206B1 (en) * 1997-02-25 2001-09-11 Chou H. Li Heat-resistant electronic systems and circuit boards
JP2000223836A (ja) * 1999-01-28 2000-08-11 Kyocera Corp 多層配線基板およびその製造方法
US6555762B2 (en) * 1999-07-01 2003-04-29 International Business Machines Corporation Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition
TW498707B (en) * 1999-11-26 2002-08-11 Matsushita Electric Industrial Co Ltd Wiring substrate and production method thereof
WO2001098222A1 (en) * 2000-06-20 2001-12-27 Kabushiki Kaisha Toshiba Transparent film-coated substrate, coating liquid for transparent film formation, and display device
TW533758B (en) * 2000-07-31 2003-05-21 Ngk Spark Plug Co Printed wiring substrate and method for manufacturing the same
US6930395B2 (en) * 2000-12-05 2005-08-16 Matsushita Electric Industrial Co., Ltd. Circuit substrate having improved connection reliability and a method for manufacturing the same
JP3473601B2 (ja) * 2000-12-26 2003-12-08 株式会社デンソー プリント基板およびその製造方法
US7202154B2 (en) 2004-01-05 2007-04-10 International Business Machines Corporation Suspension for filling via holes in silicon and method for making the same
JP4377764B2 (ja) * 2004-07-12 2009-12-02 株式会社日立ハイテクノロジーズ 電気泳動装置及び分析方法
JP4747707B2 (ja) * 2004-11-09 2011-08-17 ソニー株式会社 多層配線基板及び基板製造方法
US7425507B2 (en) * 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
DE102005036824A1 (de) * 2005-08-04 2007-03-29 Siemens Ag Chipmodul zum Einbau in Sensorchipkarten für fluidische Anwendungen sowie Verfahren zur Herstellung eines derartigen Chipmoduls
US7517798B2 (en) * 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
EP1949432B1 (en) * 2005-11-08 2017-10-18 Invensas Corporation Producing a covered through substrate via using a temporary cap layer
JP5114858B2 (ja) * 2006-03-28 2013-01-09 富士通株式会社 多層配線基板およびその作製方法
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
JP5311609B2 (ja) 2007-10-30 2013-10-09 新光電気工業株式会社 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置
US7968975B2 (en) * 2008-08-08 2011-06-28 International Business Machines Corporation Metal wiring structure for integration with through substrate vias
JP5624364B2 (ja) 2010-05-24 2014-11-12 株式会社メムス・コア 配線構造物及びその製造方法
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8697569B2 (en) 2010-07-23 2014-04-15 Tessera, Inc. Non-lithographic formation of three-dimensional conductive elements

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684256A (zh) * 2003-12-05 2005-10-19 国际商业机器公司 具有导电穿透通道的硅芯片载体及其制造方法

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EP2718968A1 (en) 2014-04-16
TWI493670B (zh) 2015-07-21
TW201304100A (zh) 2013-01-16
KR20140053946A (ko) 2014-05-08
US20120314384A1 (en) 2012-12-13
JP5941983B2 (ja) 2016-06-29
US20140201994A1 (en) 2014-07-24
WO2012170625A1 (en) 2012-12-13
US8723049B2 (en) 2014-05-13
CN103718285A (zh) 2014-04-09
US9433100B2 (en) 2016-08-30
JP2014517537A (ja) 2014-07-17

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