CN103715991A - 微cmos功率放大器 - Google Patents
微cmos功率放大器 Download PDFInfo
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- CN103715991A CN103715991A CN201210407077.1A CN201210407077A CN103715991A CN 103715991 A CN103715991 A CN 103715991A CN 201210407077 A CN201210407077 A CN 201210407077A CN 103715991 A CN103715991 A CN 103715991A
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Abstract
本发明涉及一种输出变压器由多层结构的基板构成并与放大电路模块层叠而构成的微CMOS功率放大器,提供如下构成的功率放大器,包括:放大电路模块芯片,其构成为将放大功率的电路模块化成一体;以及输出变压器,其将所述放大电路模块芯片的输出经由变压器电路输出到外部,所述输出变压器通过多层结构的基板实现,所述放大电路模块芯片和所述输出变压器由对层进行层叠而形成。根据如上述的微CMOS功率放大器,在功率放大器中将以往的占较大空间的输出变压器由多层结构的基板来构成,由此能够将芯片尺寸减小到50%以内而不降低功率放大器的输出。
Description
技术领域
本发明涉及一种输出变压器由多层结构的基板构成并与放大电路模块层叠而构成的微CMOS功率放大器。
背景技术
一般来说,无线终端所要求的事项包括低功率、低价格、小型化、高数据速率、SDR(软件定义无线电,支持多重标准功能)等。从功率放大器的设计方面来看,为了达到小型化和低价格,利用CMOS工艺而不是GaAs来减少外部SMT(表面安装)零件,并尽可能开发成内置于主流RF芯片中的方式。目前在功率放大器(PA)研究领域中,最成为争论点的是CMOS功率放大器。
CMOS功率放大器可通过RFIC(射频集成电路)的单一芯片来实现,而且还具有价格上的竞争力,因此可期待成为未来无线终端机用放大器。但是,为了设计成高传输率的发送端,要求功率放大器具有高线性,不幸的是CMOS功率放大器的线性比GaAs功率放大器差,因此需要用于对比进行补偿的发送端结构。
随着通信系统从GSM、CDMA、WCDMA等2G、3G发展成3GPP LTE、移动WiMAX等方式的3.5G、4G,需要传输的信号(主要是OFDM)逐渐变得更复杂。为此,无线终端的通信中,具有信号的频带变宽的特征,而且需要具有更高的峰均功率比(PAPR)。从而,要求终端机用的新一代功率发射器具有更高的线性和高效率。
被设计成线性CMOS功率放大器的芯片已被开发并在上市中,但还停留在低功率和中等功率范围内。作为低功率范围的放大器,代表性的是在蓝牙和超宽带通信(UWB)等中所使用的放大器。此外,作为中等功率范围的放大器,有用于代替在现有的WLAN中所使用的GaAs功率放大器的线性CMOS功率放大器(PA)等。
然而,迄今为止高输出范围的线性CMOS功率放大器没有常用化。其原因在于CMOS基板相比GaAs具有缺点而受到很多限制。
CMOS晶体管具有低击穿电压的特性,因此很难将CMOS功率放大器开发成高输出功率。因此,终端机用的功率放大器的最重要的因素中的一个即效率低,存在电池使用时间变短的缺点。这种缺点成为利用CMOS工艺的功率放大器常用化的绊脚石。
为了解决如上述的问题,作为克服CMOS晶体管的低击穿电压特性的技术,曾提出了应用共源共栅(cascode)方式及输出变压器的电压结合方式的方法。
特别是,利用变压器的差动结构,理想的是能够解决因接合线产生的晶体管的源极退化,因此能够获得更高的增益。
但是,为了作为手机用3G、4G功率放大器来使用,需要以1dB功率增益为基准输出30dBm以上。CMOS功率放大器即使将晶体管构成为两级的共源共栅,单端结构的功率放大器也只能输出以P1dB基准27dBm程度的最高输出。并且,由于没有背面通孔,所以源极没有接地,而造成性能降低严重。
此时如果使用双向(2-way)变压器,则能够形成源极的虚地(AC情况下的接地)。这种情况下,电流保持不变,但电压摆动增大2倍,输出功率提高到2倍(3dB),能够输出30dBm的功率。从而,为了提高CMOS功率放大器的输出,如上述的变压器的构成是必须具备的。
另一方面,上述变压器可以构成于CMOS芯片的内部或外部。构成于CMOS芯片外部的变压器称作片外变压器,构成于CMOS芯片内部的变压器称作片上变压器。
图1a为3G CMOS功率放大器的芯片照片。如图1a所示,将变压器构成于CMOS芯片内部而制成片上变压器方式的功率放大器。但是,变压器占芯片整个大小的50%。若减小变压器的大小,则效率和最大输出功率降低,因此不能减小。
而且,由于变压器构成于芯片内部,所以由硅介质使功率损失变大。一般来说,使用集总参数元件进行匹配时,因介质产生较大损失,但如果利用损失较小的板式电感器(slab inductor)方式的变压器,则能够减少很多该损失。
如图1b所示,片外变压器方式中,CMOS功率放大器和变压器分开构成。不能将CMOS芯片构成在变压器中央处的结构。构成于CMOS芯片外部的输出变压器方式能够克服功率损失较大的硅介质的缺点。
但是,如前所述,为了在CMOS功率放大器中提高输出,变压器的构成是必须具备的,但是变压器根据结构和材质而发生功率损失,并占功率放大器的整个芯片尺寸的接近50%的大小,因此成为常用化的绊脚石。
发明内容
本发明的目的在于解决如上述的问题,并提供一种输出变压器由多层结构的基板构成并与放大电路模块层叠而构成的微CMOS功率放大器。
为达到上述目的,本发明涉及一种微CMOS功率放大器,其特征在于,包括:放大电路模块芯片,其构成为将放大功率的电路模块化成一体;以及输出变压器,其将所述放大电路模块芯片的输出经由变压器电路输出到外部,所述输出变压器通过多层结构的基板实现,所述放大电路模块芯片和所述输出变压器由对层进行层叠而构成。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,所述输出变压器的一级线圈和二级线圈形成于相互不同的层上,并且所述层以所述一级线圈和二级线圈相互对置地层叠的方式层压。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,所述放大电路模块芯片通过CMOS芯片来实现。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,所述输出变压器包括:第二层,其形成一级线圈图案;第一层,其形成第一输入端子图案和一级线圈连接图案,所述一级线圈连接图案经由通孔与所述一级线圈图案垂直地连接;第三层,其形成二级线圈的图案;以及第四层,其形成第二输入端子图案和输出端子图案,所述第二输入端子图案经由通孔与所述第一输入端子图案垂直地连接,所述输出端子图案经由通孔与所述二级线圈图案垂直地连接,所述第一层、第二层、第三层和第四层按顺序垂直地配置成一列。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,所述放大电路模块芯片在所述第一层上层叠配置,所述放大电路模块芯片的外部端子经由引线与所述一级线圈图案或第一输入端子图案连接。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,所述一级线圈图案的两个端部和所述二级线圈图案的两个端部位于相互相反的方向。
此外,本发明的特征在于,在上述的微CMOS功率放大器中,在所述第三层上将所述二级线圈图案的第一端部延长而形成延长部,在所述第二层上形成与所述延长部相对置的电容器图案,所述电容器图案和所述二级线圈图案的第二端部经由通孔连接。
如上所述,根据本发明的微CMOS功率放大器,功率放大器将以往的占较大空间的输出变压器由多层结构的基板来构成,由此能够获得在不降低功率放大器的输出的情况下将芯片尺寸减小到50%以内的效果。
附图说明
图1表示以往的片上或片外变压器方式的CMOS功率放大器的一个实例。
图2为根据本发明的第一实施例的微CMOS功率放大器的电路图。
图3为根据本发明的第一实施例的微CMOS功率放大器的概略构成图。
图4为根据本发明的第一实施例的功率放大模块的电路图。
图5为根据本发明的第一实施例的输出变压器的电路图。
图6为根据本发明的第一实施例的输出变压器的各层的构成图。
图7为根据本发明的第一实施例的将输出变压器的第一层和功率放大模块结合的例示。
图8为根据本发明的第一实施例的输出端的电容器构成的侧视图。
图9为表示根据本发明的第一实施例的变压器的输入及输出中所测量到的电压及电流的曲线图。
图10表示根据本发明的第一实施例的变压器的频率特性。
图11表示根据本发明的第一实施例的输出变压器的输入阻抗。
具体实施方式
以下,参照附图说明用于实施本发明的具体内容。
此外,在本发明的说明中,对相同部分标注相同符号,并省略其反复说明。
首先,参照图2说明根据本发明的第一实施例的微CMOS功率放大器的电路构成。
如图2所示,微CMOS功率放大器的电路1由输入电路10、匹配电路20、共源共栅电路30及输出变压器电路40构成。而且,在各部分电路的电容器部分中,还包括用于消除电容器的振动、发热等的谐波调谐电路60来构成。
输入电路10是用于输入信号的电路,并由输入平衡不平衡变压器(input baluntransformer)构成。输入平衡不平衡变压器是将平衡信号转换为不平衡信号的电路,其将单一输入信号变成差动信号。
匹配电路20由多个电容器C1、C2、C3、C4和电感器L2构成,其是通常的为了使功率损失最少地进行传输而用于匹配输入端的阻抗的匹配电路。
共源共栅电路30为了在不提高击穿电压的情况下增大输出电压,而由差分共源共栅电路构成。这是为了解决如果以CMOS电路进行工艺则击穿电压变低而最大输出受限制的问题的电路。差分共源共栅结构,在差动情况下比单端情况更能够增加电压摆动和击穿电压。并且,在CMOS工艺中,由于通孔接地不可能实现,所以通常情况下使用引线接合来进行接地。但是,差动结构中,由于晶体管的源极端上存在虚AC地,所以能够减少由引线接合带来的电感器效果。此外,由于是对称结构,所以没有偶次谐波,因此相比于单端情况,能够进一步减少谐波。
输出变压器电路40是用于与输出50电分离并稳定地放大输出的电路,并由共源共栅电路30端的一级线圈41和输出50端的二级线圈42构成。
而且,偏置电路70是供给共源共栅电路30中所使用的晶体管电路的偏置电压的电路,并从外部接受偏置电压的施加。
另一方面,谐波调谐电路60等的电感器WL1、WL2、…、WL9在构成功率放大器1时,通过引线接合来实现。以下,更具体地进行说明。
其次,参照图3说明根据本发明的第一实施例的微CMOS功率放大器的构成。
如图3所示,根据本发明的第一实施例的微CMOS功率放大器1由放大电路模块芯片100和输出变压器200构成。
放大电路模块芯片100将放大功率的电路(以下为放大电路)模块化成一体而构成为基板或芯片。优选为,放大电路芯片模块100由CMOS电路构成而制成为芯片。
如图4所示,放大电路模块芯片100包括输入电路10、匹配电路20、共源共栅电路30、偏置电路70而由用于放大功率的主要电路构成。
并且,放大电路模块芯片100的外部端子由输入端子110、连接端子120、偏置电压端子130、电感器接地端子140构成。输入端子110是从输入电路10输入输入信号的端子,连接端子120是输出被放大的信号的端子,而且是与输出变压器电路40的一级线圈41连接的端子。
偏置电压端子130是施加偏置电路70的偏置电压的端子,电感器接地端子140是用于构成通过引线接合而接地的电感器的端子。如图4所示,电感器接地端子140由用于WL3、WL4、WL5、WL6、WL7的端子构成。
输出变压器200中,输出变压器电路40通过如LTCC(低温共烧陶瓷)等的多层结构的基板实现,各层之间经由通孔进行电连接。
在说明输出变压器200的构成之前,参照图5具体地说明构成输出变压器200的电路。图5是构成输出变压器200的电路,是放大了图2的输出变压器电路40的电路。
如图5所示,输出变压器200由一级线圈部260和二级线圈部270构成。一级线圈部260的电路由第一线圈261、与第一线圈261的两个端部连接的两个信号端子262、以及与第一线圈261中间连接的电源端子263构成。二级线圈部270的电路由第二线圈271、与第二线圈271的两个端部连接的端子即输出部端子272和接地部端子273构成。另一方面,输出部端子272和接地部端子273之间具备电容器C10。
以下,更具体地说明输出变压器200的多层结构。
接着,参照图6说明根据本发明的第一实施例的微CMOS功率放大器1的输出变压器200的多层基板结构。图6a、图6b、图6c及图6d分别是输出变压器200的第一层210、第二层220、第三层230及第四层240的平面图。
如图6所示,输出变压器200由第一层210、第二层220、第三层230及第四层240的四个层构成,并以该顺序垂直地配置成一列而构成。即,以第一层210为塔顶层,在其下面按第二层220、第三层230及第四层240的顺序进行层叠而构成。
各层210、220、230、240分别是在电介质层219、229、239、249上层压铜箔层并对铜箔层的局部进行刻蚀而形成各图案。以下,分为第一层及第二层210、220、和第三层及第四层230、240,来说明各层上所形成的图案。
首先,对第一层及第二层210、220进行说明。
第一层及第二层210、220是形成图5所示的输出变压器200的一级线圈部260的电路的层。
第二层220上形成用于形成一级线圈部260的第一线圈图案221。第一线圈图案221形成为环形导线以基板的中央为中心串联连接的导电图案,环形导线没有形成为闭合线,而是局部断开地形成。环形导线的断开的部分即为第一线圈图案221的两个末端部分(或两个端部)222。
第一线圈图案221的两个端部222上形成通孔222a,在第一线圈图案221的中间部223上也形成通孔223a。上述两个端部通孔222a作为一级线圈部的信号端子262发挥作用,中间部通孔223a作为电源端子263发挥作用。
并且,在第一线圈图案的中间部223附近形成电容器图案225,并在电容器图案225内形成通孔225a。电容器图案225是用于实现与二级线圈部270连接的电容器C10的图案。关于电容器图案225的作用,在第三层的说明时进一步具体说明。
另一方面,在第一层210上形成用于分别与一级线圈部260的端子连接的图案、和用于分别与放大器的外部端子连接的图案。此外,除此之外的区域上形成地线图案218。
与一级线圈部260的端子连接的图案由信号连接图案212及电源连接图案213构成。信号连接图案212及电源连接图案213中分别形成通孔212a、213a。
信号连接图案212形成于第二层220的第一线圈图案的两个端部222位置,电源连接图案213形成于第一线圈图案的中间部223位置。从而,信号连接图案的通孔212a与第一线圈图案的两个端部通孔222a垂直地连接,且电源连接图案的通孔213a与第一线圈图案的中间部通孔223a垂直地连接而通电。
从而,信号连接图案212作为一级线圈部260的信号端子262发挥作用,电源连接图案213作为电源端子263发挥作用。
接着,与放大器的外部端子连接的图案由第一输入端子图案215、第一偏置端子图案216、第一电源端子图案217构成。
第一输入端子图案215是接收外部信号的输入的导电图案,第一偏置端子图案216是用于连接向偏置电路施加的电源的导电图案,第一电源端子图案217是接收主电源的施加的导电图案。优选为,第一输入端子图案215、第一偏置端子图案216、第一电源端子图案217形成于第一层210的一侧。
另一方面,在第一层210中,各图案之外的剩余的整个区域上形成地线图案218,在地线图案218内形成至少一个通孔218a。地线图案的通孔218a是为了与第四层240的地线图案248电连接而作为接地来发挥作用的通孔。
并且,优选为第一层210的中央附近形成散热图案214。特别是,在第一层210之上层叠放置放大电路模块芯片100的位置形成散热图案214。放大电路模块芯片100是集成电路且有可能发热较多,因此形成为其进行散热的图案。
另一方面,在第二层220中,为了使地线图案的通孔218a与第四层240的地线图案通孔248a贯通连接,在与通孔218a、248a相同的位置形成通孔贯通的贯通孔228a。
参照图7,说明在第一层210之上层叠放置放大电路模块芯片100的实施例。
如图7所示,形成于放大电路模块芯片100的外部端子经由引线与第一层210的图案电连接。
具体地说,放大电路模块芯片100的输入端子110WL1经由引线与第一输入端子图案215连接,偏置电压端子130WL11与第一偏置端子图案216连接。并且,放大电路模块芯片100的连接端子120WL9/WL10与信号连接图案212连接,结果通过通孔212a、222a与第一线圈图案221连接。
放大电路模块芯片100的电感器接地端子140WL3、WL4、WL5、WL6、WL7经由引线接合到地线图案218。即,通过引线接合实现电感器接地功能。
另一方面,电源连接图案213经由引线与主电源图案217捆结。结果,主电源图案217经由通孔213a、223a与第一线圈图案221的中间部223连接。
其次,对第三及第四层230、240进行说明。
第三及第四层230、240是形成图5所示的输出变压器200的二级线圈部270的电路的层。
第三层230上形成用于形成二级线圈部270的第二线圈图案231。第二线圈图案231形成为环形导线以基板的中央为中心串联连接的导电图案,环形导线没有形成为闭合线,而是局部断开地形成。环形导线的断开的部分即为第二线圈图案231的两个末端部分(或两个端部)232、233。
此时,环形导线优选形成为与第一线圈图案221相互对置。但是,第二线圈图案231的两个端部232、233优选位于与第一线圈图案的两个端部222的位置相反方向的位置。在第二线圈图案231的两个端部232、233上形成通孔232a、233a。
此时,两个端部中的一个为二级线圈部270的输出部端子272,另一个为接地部端子273。为方便起见,将前者称作输出端部232,将后者称作接地端部233。
并且,将输出端部232或接地端部233中的一个导线图案进行延长。为方便起见,将输出端部232延长,并将延长的部分称作延长部232b。
如图8所示,第二层220的电容器图案225的通孔225a形成为与接地端部233(即,未延长部的末端)的通孔233a垂直地连接。即,电容器图案225经由通孔225a、233a与接地端部233连接。
并且,电容器图案225与延长部232b平行地重叠形成。从而,与输出端部232连接的延长部232b、和与接地端部233连接的电容器图案225相互对置地面对,从而作为电容器C10发挥作用。
另一方面,第四层210上形成用于与功率放大器1的外部连接的图案,其余区域上形成地线图案248。
作为功率放大器1的与外部连接的图案,形成输出端子图案242、第二输入端子图案245、第二偏置端子图案246、第二电源端子图案247。
输出端子图案242形成于与第三层230的输出端部232相同的位置,并形成有通孔242a而与输出端部232垂直地连接。并且,第二输入端子图案245、第二偏置端子图案246、第二电源端子图案247分别位于与第一层210的第一输入端子图案215、第一偏置端子图案216、第一电源端子图案217相同的位置,并经由通孔垂直地连接。
另一方面,在第四层240上,除了各个图案外的剩余的整个区域上形成地线图案248,在地线图案248内形成至少一个通孔248a,而与第一层210的地线图案218电连接。
下面,参照图9至图11进一步具体说明根据本发明的第一实施例的效果。
如图9所示,在一级线圈的输入中施加相位差为180度的电流和电压,在输出中,输入时180度差的电压在输出时有一个输入电压反转180度而使输出电压成为2倍。电流的输入和输出相同,理想地使2倍(3dB)的输出引入到二级线圈。
如图9所示,分别被施加于输入变压器的两个电压在输出中合并为2倍的电压,最终输出端上可以实现2倍的输出功率。从而,单个CMOS功率放大器(PA)只需输出27dBm的输出功率,另一单个CMOS PA利用相位差为180度的电压输出功率27dBm。这种结构称作差动结构,若利用变压器对电压进行组合,则有可能实现30dBm的输出。
根据本发明的第一实施例的变压器实际上产生0.3dB的损失,但相比于基于以往技术的片上方式的1dB以上的损失值而显示出非常卓越的性能。图11示出了输入阻抗为50欧姆的一半即25欧姆。
以上,根据实施例具体说明了由本发明人实现的发明,但本发明不限定于实施例,在不脱离其要旨的范围内,当然能够进行各种变更。
附图标记说明
1:功率放大器
10:输入电路 20:匹配电路
30:共源共栅电路 40:输出变压器电路
41:一级线圈 42:二级线圈
50:输出 60:谐波调谐电路
70:偏置电路 71:偏置电压
100:放大电路模块芯片 110:输入端子
120:连接端子 130:偏置电压端子
140:电感器接地端子
200:输出变压器 210:第一层
219、229、239、249:电介质层 212:信号连接图案
213:电源连接图案 214:散热图案
215:第一输入端子图案 216:第一偏置端子图案
217:第一电源端子图案 218、248:地线图案
221:一级线圈图案 222:两个端部
223:中间部 231:二级线圈图案
232:输出端部 233:接地端部
242:输出端子图案 245:第二输入端子图案
246:第二偏置端子图案 247:第二电源端子图案
218、228:地线图案。
Claims (7)
1.一种微CMOS功率放大器,其特征在于,包括:
放大电路模块芯片,其构成为将放大功率的电路模块化成一体;以及
输出变压器,其将所述放大电路模块芯片的输出经由变压器电路输出到外部,
所述输出变压器通过多层结构的基板实现,所述放大电路模块芯片和所述输出变压器层压而构成。
2.根据权利要求1所述的微CMOS功率放大器,其特征在于,
在所述输出变压器中,一级线圈和二级线圈形成于相互不同的层上,并且所述层以所述一级线圈和所述二级线圈相互对置地层叠的方式层压。
3.根据权利要求1所述的微CMOS功率放大器,其特征在于,
所述放大电路模块芯片通过CMOS芯片来实现。
4.根据权利要求1所述的微CMOS功率放大器,其特征在于,所述输出变压器包括:
第二层,其形成一级线圈图案;
第一层,其形成第一输入端子图案和一级线圈连接图案,所述一级线圈连接图案经由通孔与所述一级线圈图案垂直地连接;
第三层,其形成二级线圈图案;以及
第四层,其形成第二输入端子图案和输出端子图案,所述第二输入端子图案经由通孔与所述第一输入端子图案垂直地连接,所述输出端子图案经由通孔与所述二级线圈图案垂直地连接,
所述第一层、所述第二层、所述第三层和所述第四层按顺序垂直地配置成一列。
5.根据权利要求4所述的微CMOS功率放大器,其特征在于,
所述放大电路模块芯片在所述第一层上层叠配置,所述放大电路模块芯片的外部端子经由引线与所述一级线圈图案或所述第一输入端子图案连接。
6.根据权利要求4所述的微CMOS功率放大器,其特征在于,
所述一级线圈图案的两个端部和所述二级线圈图案的两个端部位于相互相反的方向。
7.根据权利要求4所述的微CMOS功率放大器,其特征在于,
在所述第三层上将所述二级线圈图案的第一端部延长而形成延长部,在所述第二层上形成与所述延长部相对置的电容器图案,所述电容器图案和所述二级线圈图案的第二端部经由通孔连接。
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WO2015112091A1 (en) * | 2014-01-23 | 2015-07-30 | Massachusetts Institute Of Technology (Mit) | An integrated circuit adapted for mobile communication and related mobile computing device |
JP2020027975A (ja) * | 2018-08-09 | 2020-02-20 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
JP2020028108A (ja) * | 2018-08-10 | 2020-02-20 | 株式会社村田製作所 | 電力増幅モジュール |
US11196394B2 (en) * | 2018-08-10 | 2021-12-07 | Murata Manufacturing Co., Ltd. | Power amplifier module |
JP2021061577A (ja) * | 2019-10-09 | 2021-04-15 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
JP2022090557A (ja) * | 2020-12-07 | 2022-06-17 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
CN116192067B (zh) * | 2023-04-28 | 2023-08-15 | 广东工业大学 | 一种晶体管堆叠电压摆幅增强的功率放大器 |
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US6424227B1 (en) * | 2001-05-23 | 2002-07-23 | National Scientific Corporation | Monolithic balanced RF power amplifier |
KR100568312B1 (ko) * | 2004-09-23 | 2006-04-05 | 삼성전기주식회사 | 적층형 발룬 트랜스포머 |
US7315212B2 (en) * | 2005-04-13 | 2008-01-01 | International Business Machines Corporation | Circuits and methods for implementing transformer-coupled amplifiers at millimeter wave frequencies |
US7477108B2 (en) * | 2006-07-14 | 2009-01-13 | Micro Mobio, Inc. | Thermally distributed integrated power amplifier module |
US7675365B2 (en) * | 2007-01-10 | 2010-03-09 | Samsung Electro-Mechanics | Systems and methods for power amplifiers with voltage boosting multi-primary transformers |
US7746174B2 (en) * | 2008-06-12 | 2010-06-29 | Samsung Electro-Mechanics Company, Ltd. | Systems and methods for power amplifier with integrated passive device |
JP2011182107A (ja) * | 2010-02-26 | 2011-09-15 | Renesas Electronics Corp | 電力増幅装置 |
US8115555B2 (en) | 2010-03-12 | 2012-02-14 | Samsung Electro-Mechanics | Balun function with reference enhancement in single-ended port |
KR20120072424A (ko) * | 2010-12-24 | 2012-07-04 | 삼성전기주식회사 | 트랜스포머 |
US8729963B2 (en) * | 2011-02-09 | 2014-05-20 | Rf Micro Devices, Inc. | Asymmetrical transformer output demultiplexing (atodem) circuit |
US9379678B2 (en) * | 2012-04-23 | 2016-06-28 | Qualcomm Incorporated | Integrated directional coupler within an RF matching network |
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