CN103715097A - 利用外延工艺制备垂直沟道的围栅型mosfet的方法 - Google Patents

利用外延工艺制备垂直沟道的围栅型mosfet的方法 Download PDF

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CN103715097A
CN103715097A CN201310742875.4A CN201310742875A CN103715097A CN 103715097 A CN103715097 A CN 103715097A CN 201310742875 A CN201310742875 A CN 201310742875A CN 103715097 A CN103715097 A CN 103715097A
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epitaxial loayer
vertical
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type mosfet
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CN103715097B (zh
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郭奥
任铮
胡少坚
周伟
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Shanghai IC R&D Center Co Ltd
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Shanghai Integrated Circuit Research and Development Center Co Ltd
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Abstract

本发明提供一种利用外延工艺制备垂直沟道的围栅型MOSFET的方法，包括：选取一个从上到下依次包含有顶层膜、中间介质层和底层膜的半导体衬底；采用外延工艺在半导体衬底上制备第一外延层；在顶层膜中形成源/漏电极图形；在第一外延层中形成垂直沟道结构；在垂直沟道结构表面形成栅介质层；在半导体衬底上形成底层侧墙层—栅电极层—顶层侧墙层的三明治结构；在栅电极层中形成栅电极图形；在栅电极图形上沉积一层介质层，在介质层中形成顶层侧墙结构；采用外延工艺在顶层侧墙结构上形成第二外延层；在第二外延层中形成漏/源电极图形。本发明的方法可以与传统CMOS工艺良好兼容，降低了工艺难度并节约了成本。

Description

利用外延工艺制备垂直沟道的围栅型MOSFET的方法
技术领域
本发明涉及半导体技术领域，特别涉及一种利用外延工艺制备垂直沟道的围栅型MOSFET的方法。
背景技术
随着半导体工艺技术节点的不断缩小，传统的平面MOSFET遇到了越来越多的技术挑战，如器件漏电显著增大，短沟道效应日趋严重，亚阈值特性日益恶化等，而随着MOS器件特征尺寸的不断减小，器件制备也越来越依赖于高精度的光刻工艺，这也极大地限制了平面MOS器件的发展，因此近年来越来越多的研究工作对三维结构的MOS器件进行了探索，尤其是以FinFET和围栅型纳米线MOSFET为代表的多栅器件成为研究热点，FinFET目前已成为业界所公认的可以延续平面MOSFET Scaling-down趋势的新型器件结构，并将在20纳米以下工艺节点获得量产，而围栅型的纳米线MOSFET也非常希望成为继FinFET之后的下一代主流器件结构。
然而，在目前所研究的围栅型MOSFET的器件结构中，绝大部分器件的导电沟道仍然与衬底表面平行，即在衬底表面形成悬空的导电沟道，然后制备围栅型的栅极，这种器件结构对器件的制备工艺提出了非常苛刻的要求，尤其是对于如何形成悬空的导电沟道，目前仍没有成熟的制备工艺可以实现。该结构的另一个缺点是栅极的特征尺寸仍需依赖传统的光刻工艺进行定义，这也极大地限制了器件尺寸的进一步缩小。
为此，有人提出了垂直沟道的围栅MOSFET结构，如图1所示(Mark Bohr,IEDM,2011)，图1为现有的围栅型MOSFET器件的结构示意图，其中，3表示源/漏电极，该器件的导电沟道2垂直于衬底表面，栅电极1环绕导电沟道2形成围栅器件结构，该结构的突出优点非常便于制备理想的围栅结构，从而实现较为理想的亚阈值特性，另一个显著优势是栅电极的特征尺寸通过淀积工艺即可实现，无需借助光刻工艺，从而使得器件尺寸更易于进一步缩小。但是目前仍然缺乏与传统CMOS工艺兼容的用于制备垂直沟道的围栅型MOSFET器件的制备工艺，如果能够与传统CMOS工艺相兼容，能够在原有设备规模的基础上进行制备，不仅避免了成本的扩大，还克服了器件尺寸进一步缩小的工艺难度。因此，探索研究与传统CMOS工艺兼容的用于制备垂直沟道的围栅型MOSFET器件的制备工艺具有十分重要的意义。
发明内容
为了克服上述问题，本发明旨在提供一种利用外延工艺制备垂直沟道的围栅型MOSFET的方法，该方法可以与传统CMOS工艺良好兼容，从而达到节约工艺成本和降低工艺难度的目的。
本发明提供一种利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其包括以下步骤：
步骤S01：选取一个从上到下依次包含有顶层膜、中间介质层和底层膜的半导体衬底；
步骤S02：采用外延工艺在半导体衬底上制备第一外延层；
步骤S03：经过光刻和刻蚀工艺刻蚀第一外延层和顶层膜，在顶层膜中形成源/漏电极图形；
步骤S04：经过光刻和刻蚀工艺刻蚀第一外延层，在第一外延层中形成垂直沟道结构；
步骤S05：在垂直沟道结构表面形成栅介质层；
步骤S06：在半导体衬底上形成“底层侧墙层—栅电极层—顶层侧墙层”的三明治结构；
步骤S07：经过光刻工艺和刻蚀工艺刻蚀顶层侧墙层和所述栅电极层，在所述栅电极层中形成栅电极图形；
步骤S08：在栅电极图形上沉积一层介质层，对介质层进行平坦化处理，直至露出垂直沟道结构的顶部，而在介质层中形成顶层侧墙结构；
步骤S09：采用外延工艺在顶层侧墙结构上形成第二外延层，且第二外延层的材料与半导体衬底的顶层膜的材料相同；
步骤S10：经过光刻和刻蚀工艺刻蚀第二外延层，在第二外延层中形成源/漏电极图形。
优选地，步骤S03、步骤S04、步骤S07和步骤S10中所述的刻蚀工艺为各向异性刻蚀工艺。
优选地，步骤S05中栅介质层的形成包括采用热氧化工艺或者采用原子层淀积工艺。
优选地，步骤S06中，采用化学气相沉积法形成三明治结构，包括从下到上依次沉积底层侧墙层、栅电极层和顶层侧墙层。
优选地，步骤S06中，还包括利用化学机械研磨工艺对顶层侧墙层的表面进行平坦化处理。
优选地，步骤S08中，平坦化处理的方法为化学机械研磨法。
优选地，第二外延层的材料与第一外延层的材料不同，且第二外延层的材料与半导体衬底的顶层膜的材料相同。
优选地，半导体衬底为绝缘层上的硅或锗衬底。
优选地，第一外延层的材料为Si，Ge，GeSi，或III-V族化合物。
优选地，第二外延层中的源/漏电极图形与顶层膜中的源（漏）电极图形相对称。
本发明所提出的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，通过先后使用两次外延工艺分别生长两种不同材料的外延层（第一外延层和第二外延层），即可制备垂直沟道的围栅型MOSFET，从而实现与传统的CMOS工艺相兼容，使其可以在原有设备规模上进行制备，节约了成本；而且当垂直沟道的尺寸进一步减小时，即可形成垂直沟道的纳米线晶体管，从而解决了继FinFET之后MOS器件尺寸进一步缩小的技术难点；由于外延工艺在材料生长方面的灵活性，本发明所提出的制备围栅型MOSFET的方法也可用于制备多种不同沟道材料的场效应晶体管，如Ge、GeSi以及III-V族化合物半导体晶体管等，从而拓宽了器件的应用领域。
附图说明
图1为现有的围栅型MOSFET器件的结构示意图
图2为本发明的一个较佳实施例的利用外延工艺制备垂直沟道的围栅型MOSFET的方法的流程示意图
图3-12为本发明的上述较佳实施例的利用外延工艺制备垂直沟道的围栅型MOSFET的方法中各个制备步骤所对应的截面结构示意图
具体实施方式
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例，本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
以下结合具体实施例和附图2-12对本发明的利用外延工艺制备垂直沟道的围栅型MOSFET的方法作进一步详细说明。其中，图2为本发明的一个较佳实施例的利用外延工艺制备垂直沟道的围栅型MOSFET的方法的流程示意图，图3-12为本发明的一个较佳实施例的利用外延工艺制备垂直沟道的围栅型MOSFET的方法中各个制备步骤所对应的截面结构示意图。
如前所述，垂直沟道的围栅MOSFET结构导电沟道垂直于衬底表面，栅极环绕导电沟道形成围栅器件结构，从而实现较为理想的亚阈值特性，栅极的特征尺寸通过淀积工艺即可实现，无需借助光刻工艺，从而使得器件尺寸更易于进一步缩小，降低了工艺难度。但是目前仍然缺乏与传统CMOS工艺兼容的用于制备垂直沟道的围栅型MOSFET器件的制备工艺，为此，本发明提出了能够与传统CMOS工艺相兼容的制备垂直沟道的围栅型MOSFET器件的方法，实现了能够在原有设备规模的基础上进行制备，不仅避免了成本的扩大，还克服了器件尺寸进一步缩小的工艺难度。
请参阅图2，本发明的一个较佳实施例的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其包括以下步骤：
步骤S01：请参阅图3，选取一个从上到下依次包含有顶层膜1、中间介质层2和底层膜3的半导体衬底；
具体的，在本发明中，半导体衬底可以是具有底层膜、中间介质层和顶层膜的任意半导体衬底，比如介质层上的硅衬底或介质层上的锗衬底，在本发明的本实施例中，半导体衬底为介质层上的硅衬底，包括底层硅膜、中间二氧化硅层和顶层硅膜；在另一个较佳实施例中，半导体衬底为介质层上的锗衬底，但这不用于限制本发明的范围。
步骤S02：请参阅图4，采用外延工艺在半导体衬底上制备第一外延层4；
具体的，在本发明中，制备第一外延层的外延工艺可以是常规的外延生长法，在本发明的本实施例中，在顶层硅膜上外延生长第一外延层4，所述第一外延层的材料可以为Si，Ge，GeSi，或III-V族化合物，在本实施例中，该第一外延层4的材料与半导体衬底的顶层膜1的材料不同，由于顶层膜为硅膜，因此，第一外延层4的材料可以为除了Si以外的任意半导体材料，较佳的，本实施例中的第一外延层4的材料可以为Ge，GeSi，或III-V族化合物。
步骤S03：请参阅图5，经过光刻和刻蚀工艺刻蚀第一外延层4和顶层膜1，在顶层膜1中形成源/漏电极图形；
具体的，在本发明的本实施例中，采用光刻工艺，首先在半导体衬底上涂覆一层光刻胶，然后经曝光显影，在光刻胶中定义出源、漏电极图形，再采用各向异性刻蚀法刻蚀第一外延层4和顶层膜1，从而在顶层膜1中刻蚀出源/漏电极图形，这里，需要说明的是，在本发明中，采用各向异性刻蚀的过程中，不可避免也刻蚀到第一外延层，在本发明的本实施例中，在第一外延层4中也同时刻蚀出源/漏电极图形。
步骤S04：请参阅图6，经过光刻和刻蚀工艺刻蚀第一外延层4，在第一外延层4中形成垂直沟道结构5；
具体的，在本发明的本实施例中，采用光刻工艺，首先在半导体衬底上涂覆一层光刻胶，然后经曝光显影，在光刻胶中定义出垂直沟道结构的图形，再采用各向异性刻蚀法刻蚀第一外延层4，最后在第一外延层4中刻蚀出垂直沟道结构5。
步骤S05：请参阅图7，在垂直沟道结构5表面形成栅介质层6；
具体的，在本发明中，形成栅介质层6的方法可以采用物理沉积或化学沉积法，需要说明的是，可以根据垂直沟道结构5的材料不同，选取不同的形成栅介质层6的方法，在本发明的本实施例中，由于第一外延层4可以是除硅以外的任意半导体材料，例如Ge，GeSi，或III-V族化合物，可以采用原子层淀积工艺，制备高K栅介质层；在另一实施例中，当第一外延层4为硅时，可以采用热氧化工艺形成SiO2栅介质层。
步骤S06：请参阅图8，在半导体衬底上形成“底层侧墙层7—栅电极层8—顶层侧墙层9”的三明治结构；
具体的，在本发明中，沉积底层侧墙层7-栅电极层8-顶层侧墙层9的方法可以是物理沉积法、化学沉积法等，在本实施例中，采用化学气相沉积法在半导体衬底上从下至上依次沉积底层侧墙层7，栅电极层8和顶层侧墙层9，从而形成三明治结构。
进一步的，在本实施例中，在形成三明治结构之后，还包括采用化学机械研磨法对顶层侧墙层9进行平坦化处理。这里，底层侧墙层7和顶层侧墙层9用于隔绝栅电极和源、漏电极。本实施例中，栅电极层8的材料可以采用多晶硅、金属栅材料等，本发明对此不作任何限制。
步骤S07：请参阅图9，经过光刻工艺和刻蚀工艺刻蚀顶层侧墙层9和栅电极层8，在栅电极层8中形成栅电极图形；
具体的，在本发明的本实施例中，首先采用光刻工艺在光刻胶中定义出栅电极图形，然后采用各项异性刻蚀法刻蚀顶层侧墙层9和栅电极层8，从而在栅电极层8中刻蚀出栅电极图形；这里需要说明的是，在实际的各项异性刻蚀过程中，不可避免的要刻蚀到顶层侧墙层9，在本实施例中，同时在顶层侧墙层9中也刻蚀出栅电极图形，但这并用于限制本发明的范围。
步骤S08：请参阅图10，在栅电极图形上沉积一层介质层，对介质层进行平坦化处理，直至露出垂直沟道结构5的顶部，从而在介质层中形成顶层侧墙结构10；
具体的，由于上述步骤S07中，进行各向异性刻蚀之后，如前所述，顶层侧墙层9被刻蚀掉一部分，由于顶层侧墙层9的作用是用于隔离栅电极层8和源、漏电极的，为了使栅电极层8和源、漏电极不接触，需要再次沉积一层介质层，用于修复顶层侧墙层9，该介质层的顶部可以高出原有顶层侧墙层9的顶部，然后对该介质层的顶部表面进行平坦化处理，本实施例中，可以采用化学机械研磨法对该介质层进行进行磨平，直至露出垂直沟道结构5的顶部，这样这层介质层就形成了顶层侧墙结构10。
步骤S09：请参阅图11，采用外延工艺在顶层侧墙结构10上形成第二外延层11；
具体的，本发明的本实施例中，可以采用外延生长法在顶层侧墙结构10上形成第二外延层11，这里，第二外延层11的材料与半导体衬底的顶层膜1的材料相同，这样可以确保第二外延层11中的源/漏电极图形与顶层膜1中的源（漏）电极图形所构成的源、漏电极的对称性。本实施例的顶层膜1的材料为硅，因此，第二外延层11的材料为硅；并且，在本发明的本实施例中，第一外延层4的材料与第二外延层11的材料不同，如前所述，第一外延层4的材料可以是除硅以外的其它半导体材料。同样，在另一实施例中，当半导体衬底的顶层膜1为锗时，第二外延层11材料与顶层膜1的材料相同，也为锗材料，此时，由于第二外延层11的材料与第一外延层4材料不同，第一外延层4可以是除了锗以外的其它半导体材料。
步骤S10：请参阅图12，经过光刻和刻蚀工艺刻蚀第二外延层11，在第二外延层11中形成源/漏电极图形12。
具体的，本实施例中，首先采用光刻工艺定义出源/漏电极图形，然后，采用各向异性刻蚀工艺刻蚀第二外延层11，从而在第二外延层11中形成源/漏电极图形。这里，凡是能够在第二外延层11中刻蚀出源/漏电极的刻蚀方法均在本发明范围之内，比如还可以采用湿化学法刻蚀等。本实施例中，第二外延层11中的源/漏电极图形12与顶层膜1中的源/漏电极图形相同，且两者的水平投影相重合，也即是，第二外延层11中的源/漏电极图形12与顶层膜1中的源/漏电极图形互为镜像对称图形。
本发明所提出的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，通过交替使用两次外延工艺分别生长两种不同材料的外延层即可制备垂直沟道的围栅型MOSFET，从而实现与传统的CMOS工艺相兼容，使其可以在原有设备规模上进行制备，节约了成本；而且当垂直沟道的尺寸进一步减小时，即可形成垂直沟道的纳米线晶体管，从而解决了继FinFET之后MOS器件尺寸进一步缩小的技术难点；由于外延工艺在材料生长方面的灵活性，本发明所提出的制备围栅型MOSFET的方法也可用于制备多种不同沟道材料的场效应晶体管，如Ge、GeSi以及III-V族化合物半导体晶体管等，从而拓宽了器件的应用领域。
虽然本发明已以较佳实施例揭示如上，然所述实施例仅为了便于说明而举例而已，并非用以限定本发明，本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰，本发明所主张的保护范围应以权利要求书所述为准。

Claims (10)

1.一种利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，包括以下步骤：
步骤S01：选取一个从上到下依次包含有顶层膜、中间介质层和底层膜的半导体衬底；
步骤S02：采用外延工艺在所述半导体衬底上制备第一外延层；
步骤S03：经过光刻和刻蚀工艺刻蚀所述第一外延层和所述顶层膜，在所述顶层膜中形成源/漏电极图形；
步骤S04：经过光刻和刻蚀工艺刻蚀所述第一外延层，在所述第一外延层中形成垂直沟道结构；
步骤S05：在所述垂直沟道结构表面形成栅介质层；
步骤S06：在所述半导体衬底上形成“底层侧墙层—栅电极层—顶层侧墙层”的三明治结构；；
步骤S07：经过光刻工艺和刻蚀工艺刻蚀所述顶层侧墙层和所述栅电极层，在所述栅电极层中形成栅电极图形；
步骤S08：在所述栅电极图形上沉积一层介质层，对所述介质层进行平坦化处理，直至露出所述垂直沟道结构的顶部，而在所述介质层中形成顶层侧墙结构；
步骤S09：采用外延工艺在所述顶层侧墙结构上形成第二外延层，且第二外延层的材料与所述半导体衬底的顶层膜的材料相同；
步骤S10：经过光刻和刻蚀工艺刻蚀所述第二外延层，在所述第二外延层中形成源/漏电极图形。
2.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述步骤S03、步骤S04、步骤S07和步骤S10中所述的刻蚀工艺为各向异性刻蚀工艺。
3.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述步骤S05中所述的栅介质层的形成包括采用热氧化工艺或者采用原子层淀积工艺。
4.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述步骤S06中，采用化学气相沉积法形成所述三明治结构，包括从下到上依次沉积所述底层侧墙层、所述栅电极层和所述顶层侧墙层。
5.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述步骤S06中，还包括利用化学机械研磨工艺对所述顶层侧墙层的表面进行平坦化处理。
6.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述步骤S08中，所述平坦化处理的方法为化学机械研磨法。
7.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述第二外延层的材料与所述第一外延层的材料不同，且所述第二外延层的材料与所述半导体衬底的顶层膜的材料相同。
8.根据权利要求1或7的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述半导体衬底为绝缘层上的硅或锗衬底。
9.根据权利要求1或7的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述第一外延层的材料为Si，Ge，GeSi，或III-V族化合物。
10.根据权利要求1所述的利用外延工艺制备垂直沟道的围栅型MOSFET的方法，其特征在于，所述第二外延层中的漏/源电极图形与所述顶层膜中的源/漏电极图形互为镜像对称图形。
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CN105336597A (zh) * 2015-10-26 2016-02-17 上海集成电路研发中心有限公司 一种全包围栅结构的制备方法
CN105336597B (zh) * 2015-10-26 2018-05-01 上海集成电路研发中心有限公司 一种全包围栅结构的制备方法
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