CN103700752A - Salient point bonding structure of vertical structure LED chip and process - Google Patents

Salient point bonding structure of vertical structure LED chip and process Download PDF

Info

Publication number
CN103700752A
CN103700752A CN201310665416.0A CN201310665416A CN103700752A CN 103700752 A CN103700752 A CN 103700752A CN 201310665416 A CN201310665416 A CN 201310665416A CN 103700752 A CN103700752 A CN 103700752A
Authority
CN
China
Prior art keywords
substrate
bonding
bump
salient point
epitaxial wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310665416.0A
Other languages
Chinese (zh)
Other versions
CN103700752B (en
Inventor
云峰
郭茂峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Optics Technology Shaanxi Co ltd
Original Assignee
Xian Jiaotong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Jiaotong University filed Critical Xian Jiaotong University
Priority to CN201310665416.0A priority Critical patent/CN103700752B/en
Publication of CN103700752A publication Critical patent/CN103700752A/en
Application granted granted Critical
Publication of CN103700752B publication Critical patent/CN103700752B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors

Abstract

The invention discloses a salient point bonding structure of a vertical structure LED chip and a process. The salient point bonding structure comprises an epitaxial wafer, a substrate and a salient point array structure, wherein the salient point array structure is arranged between the epitaxial wafer and the substrate; a metalization layer is arranged on the epitaxial wafer; one end of the salient point array structure is bonded with the metalization layer, and the other end is connected with the substrate; or a metalization layer is arranged on the substrate, one end of the salient point array structure is bonded with the metalization layer, and the other end is connected with the epitaxial wafer; the salient point array structure is filled with acrylic or epoxy resins. The substrate and the epitaxial wafer are bonded to form a bonding layer with the duty ratio structure, and the bonding layer is filled to form a stable bonding structure so as to reduce stress between the epitaxial layer and the substrate.

Description

A kind of bump bonding structure &processes of light emitting diode (LED) chip with vertical structure
Technical field:
The present invention relates to the preparing technical field of light emitting semiconductor device, particularly a kind of chip bonding process.
Background technology:
Current, GaN base LED has two kinds of basic structures: horizontal structure and vertical stratification.In recent years, vertical structure LED has become the emphasis of research and development.LED compares with horizontal structure, vertical structure LED passes through translate substrate, GaN base epitaxial loayer is transferred to conduction and the good backing material of heat conductivility from Sapphire Substrate, P, N electrode are distributed up and down, electric current vertically injects, thereby solve in horizontal structure GaN base LED because electrode plane distributes, electric current side direction inject cause as poor heat radiation, the unequal shortcoming of CURRENT DISTRIBUTION.
Wherein, chip bonding process is one of critical process of making light emitting diode (LED) chip with vertical structure, and the alloys such as current main employing AuSn, Au are by epitaxial wafer and substrate Direct Bonding.Because thermal coefficient of expansion between the alloys such as AuSn, Au, epitaxial wafer and substrate is different, after bonding, between epitaxial loayer and substrate, produce larger stress, bring impact to the techniques such as follow-up laser lift-off.
Summary of the invention:
The object of the present invention is to provide a kind of bump bonding structure &processes of light emitting diode (LED) chip with vertical structure, to reduce the stress between epitaxial loayer and substrate after bonding.
To achieve these goals, the present invention adopts following technical scheme:
A bump bonding structure for light emitting diode (LED) chip with vertical structure, comprises epitaxial wafer, substrate and bump array structure; Bump array structure is arranged between epitaxial wafer and substrate; Described epitaxial wafer is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, and the other end connects described substrate; Or described substrate is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, the other end connects described epitaxial wafer.
The present invention further improves and is: bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the duty ratio of salient point is 1:0.03 to 1:30.Duty ratio is at sustained height place, the ratio of spacing between the width of salient point and adjacent two salient points.
The present invention further improves and is: the height of salient point is 1.2 microns to 80 microns, and the duty ratio of salient point is 1:0.3 to 1:3.
The present invention further improves and is: in bump array structure, be filled with acrylic compounds or epoxylite.
The present invention further improves and is: the material of bump array structure bumps is one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof.
The present invention further improves and is: the described coat of metal is Gold plated Layer or silver coating.
A preparation technology for the bump bonding structure of light emitting diode (LED) chip with vertical structure, described epitaxial wafer is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, the other end connects described substrate; Comprise the following steps:
1), on substrate, prepare complex metal layer (102); Described substrate is metal substrate or silicon substrate;
2), on complex metal layer surface, make to do with photoresist periodically photoengraving pattern;
3), corrosion complex metal layer, expose substrate;
4), remove after photoengraving pattern, on substrate, form bump array structure;
5), the coat of metal bonding on bump array structure and epitaxial wafer; .
The present invention further improves and is: further comprising the steps of: gap-fill acrylic compounds or the epoxylite of the bump array structure 6), after bonding.
A preparation technology for the bump bonding structure of light emitting diode (LED) chip with vertical structure, described substrate is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, the other end connects described epitaxial wafer; Comprise the following steps:
1), on epitaxial wafer fabrication cycle photoengraving pattern, periodically photoengraving pattern is around the pyramid, prism, round platform or the cylindrical space that form some arrays; Described substrate is metal substrate or silicon substrate;
2), at epitaxial wafer and photoengraving pattern surface, prepare complex metal layer;
3), adopt and remove photoresist after solution removal photoengraving pattern, the salient point array that formation complex metal layer forms;
4), the Gold plated Layer bonding on bump array structure and substrate.
The present invention further improves and is: further comprising the steps of: in the salient point gap 5), after bonding, to fill acrylic compounds or epoxylite.
The present invention prepares salient point array on epitaxial wafer or substrate; Chip and substrate bonding, form " duty ratio structure " bonded layer; Fill bonded layer, form rock-steady structure.
The present invention further improves and is: described salient point adopts round platform or column structure; The material of salient point is one or more of gold, silver, indium, its alloy of tin; Preferably 1.2 microns to 80 microns of the height of salient point; The duty ratio of salient point, between 1:0.3 to 1:3.
With respect to prior art, beneficial effect of the present invention is as follows: after substrate and wafer bonding, form " duty ratio structure " bonded layer, after filling bonded layer, form and stablize bonding structure, thereby reduce the stress between epitaxial loayer and substrate.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 d is the embodiment of the present invention 1 Solder bumping process schematic representation;
Fig. 1 e is the embodiment of the present invention 1 bonding technology schematic diagram;
Fig. 1 f is the embodiment of the present invention 1 fill process schematic diagram;
Fig. 2 a to Fig. 2 d is the embodiment of the present invention 2 Solder bumping process schematic representations;
Fig. 2 e is the embodiment of the present invention 2 bonding technology schematic diagrames;
Fig. 2 f is the embodiment of the present invention 2 fill process schematic diagrames;
Fig. 3 a to Fig. 3 d is the embodiment of the present invention 3 Solder bumping process schematic representations;
Fig. 3 e is the embodiment of the present invention 3 bonding technology schematic diagrames;
Fig. 3 f is the embodiment of the present invention 3 fill process schematic diagrames;
Fig. 4 a to Fig. 4 d is the embodiment of the present invention 4 Solder bumping process schematic representations;
Fig. 4 e is the embodiment of the present invention 4 bonding technology schematic diagrames;
Fig. 4 f is the embodiment of the present invention 4 fill process schematic diagrames.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Embodiment 1
Fig. 1 a to 1f is the technical process of the bump bonding structure with 1 one kinds of light emitting diode (LED) chip with vertical structure of the embodiment of the present invention, and it specifically comprises the following steps:
1), in metal substrate 101, prepare complex metal layer 102, complex metal layer 102 is made by one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof, complex metal layer 102 can be one deck prepared by hybrid metal, or sandwich construction, such as 0.3 micron of titanium of evaporation and 5 micron chickens;
2), on complex metal layer 102 surfaces, make to do with photoresist periodically photoengraving pattern 103, as shown in Figure 1 b;
3), corrode compound bonded layer 102 metals, expose metal substrate 101, as shown in Fig. 1 c;
4), remove after photoengraving pattern 103, in metal substrate 101, form bump array structure, form bump bonding substrate 111, as Fig. 1 d; Bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the scope of the duty ratio of salient point is between 1:0.03 to 1:30; The height of preferred salient point is 1.2 microns to 80 microns, and the duty ratio of preferred salient point is between 1:0.3 to 1:3.Duty ratio is at sustained height place, the ratio of spacing between the width of salient point and adjacent two salient points.
5), the bump array structure of bump bonding substrate 111 and Gold plated Layer 104 bondings on epitaxial wafer 105, as Fig. 1 e;
6) the gap-fill epoxy resin 106 of the bump array structure, after bonding, forms stable bonding structure, as Fig. 1 f, completes bump bonding technique overall process.
Embodiment 2
Fig. 2 a to 2f is the technical process of the bump bonding structure with 2 one kinds of light emitting diode (LED) chip with vertical structure of the embodiment of the present invention, and it specifically comprises the following steps:
1), on silicon substrate 201 fabrication cycle photoengraving pattern 202, periodically photoengraving pattern 202 is around the round platform or the cylindrical space that form some arrays;
2), if Fig. 2 b(Fig. 2 b is schematic diagram, the height of complex metal layer 203 should lower than or maintain an equal level with photoengraving pattern 202), at silicon substrate 201 and photoengraving pattern 202 surfaces, prepare complex metal layer 203, complex metal layer 203 can be by one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof, such as electroplating 0.5 micron of nickel and 20 micron chickens ashbury metal structures;
3), as shown in Figure 2 c, adopt and remove photoresist after solution removal photoengraving pattern 202, form the salient point array that complex metal layer 203 forms; And then form bump bonding substrate 222, as shown in Figure 2 d; Bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the scope of the duty ratio of salient point is between 1:0.03 to 1:30; The height of preferred salient point is 1.2 microns to 80 microns, and the duty ratio of preferred salient point is between 1:0.3 to 1:3.
4), as Fig. 2 e, Gold plated Layer 204 bondings on the bump array structure of bump bonding substrate 222 and epitaxial wafer 205;
5) in the salient point gap, after bonding, fill acrylic resin 206, form and stablize bonding structure, Fig. 2 f, completes bump bonding technique overall process.
Embodiment 3
Fig. 3 a to 3f is the technical process of the bump bonding structure with 3 one kinds of light emitting diode (LED) chip with vertical structure of the embodiment of the present invention, and it specifically comprises the following steps:
1), on epitaxial wafer 301 fabrication cycle photoengraving pattern 302, periodically photoengraving pattern 202 is around the round platform or the cylindrical space that form some arrays;
2), if Fig. 3 b(Fig. 3 b is schematic diagram, the height of complex metal layer 303 should lower than or maintain an equal level with photoengraving pattern 302), at epitaxial wafer 301 and photoengraving pattern 302 surfaces, prepare complex metal layer 303, complex metal layer 303 can be by one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof, such as electroplating 0.5 micron of chromium and 10 microns of indium structures;
3), as shown in Figure 3 c, adopt and remove photoresist after solution removal photoengraving pattern 302, form salient point array; And then form bump bonding epitaxial wafer 333, as shown in Figure 3 d; Bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the scope of the duty ratio of salient point is between 1:0.03 to 1:30; The height of preferred salient point is 1.2 microns to 80 microns, and the duty ratio of preferred salient point is between 1:0.3 to 1:3.
4), as Fig. 3 e, Gold plated Layer 304 bondings of the bump array structure of bump bonding epitaxial wafer 333 and metal substrate 305;
5) in the salient point gap, after bonding, fill acrylic resin 306, form and stablize bonding structure, Fig. 3 f, completes bump bonding technique overall process.
Embodiment 4
Fig. 4 a to 4f is the technical process of the bump bonding structure with 4 one kinds of light emitting diode (LED) chip with vertical structure of the embodiment of the present invention, and it specifically comprises the following steps:
1), on epitaxial wafer 401, prepare complex metal layer 402, complex metal layer 402 can be by one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof, such as 2 microns of titaniums of evaporation and 5 microns of indiums;
2), on complex metal layer 402 surfaces, make to do with photoresist periodically photoengraving pattern 403, as shown in Figure 4 b;
3), corrode compound bonded layer 402 metals, expose epitaxial wafer 401, as shown in Fig. 4 c;
4), remove after photoresist 403, on epitaxial wafer 401, form bump array structure, epitaxial wafer 401 and bump array structure form bump bonding epitaxial wafer 444, as Fig. 4 d; Bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the scope of the duty ratio of salient point is between 1:0.03 to 1:30; The height of preferred salient point is 1.2 microns to 80 microns, and the duty ratio of preferred salient point is between 1:0.3 to 1:3.
5), the bump array structure of bump bonding epitaxial wafer 444 and silver coating 404 bondings of silicon substrate 405, as Fig. 4 e;
6) the gap-fill epoxy resin 406 of the bump array structure, after bonding, forms stable bonding structure, as Fig. 4 f, completes bump bonding technique overall process.

Claims (10)

1. a bump bonding structure for light emitting diode (LED) chip with vertical structure, is characterized in that, comprises epitaxial wafer, substrate and bump array structure; Bump array structure is arranged between epitaxial wafer and substrate;
Described epitaxial wafer is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, and the other end connects described substrate; Or described substrate is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, the other end connects described epitaxial wafer.
2. the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure according to claim 1, it is characterized in that, bump structure be pyramid, prism, round platform or cylindrical one or more, the height of salient point is at 1 micron to 120 microns, the duty ratio of salient point is 1:0.03 to 1:30.
3. the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure according to claim 2, is characterized in that, the height of salient point is 1.2 microns to 80 microns, and the duty ratio of salient point is 1:0.3 to 1:3.
4. the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure according to claim 1, is characterized in that, is filled with acrylic compounds or epoxylite in bump array structure.
5. the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure according to claim 1, is characterized in that, the material of bump array structure bumps is one or more of gold, silver, aluminium, indium, tin, nickel, chromium, titanium, platinum and alloy thereof.
6. the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure according to claim 1, is characterized in that, the described coat of metal is Gold plated Layer or silver coating.
7. the preparation technology of the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure described in any one in claim 1 to 6, it is characterized in that, described epitaxial wafer is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, and the other end connects described substrate; Comprise the following steps:
1), on substrate, prepare complex metal layer (102); Described substrate is metal substrate or silicon substrate;
2), on complex metal layer surface, make to do with photoresist periodically photoengraving pattern;
3), corrosion complex metal layer, expose substrate;
4), remove after photoengraving pattern, on substrate, form bump array structure;
5), the coat of metal bonding on bump array structure and epitaxial wafer.
8. preparation technology claimed in claim 7, is characterized in that, further comprising the steps of:
6), gap-fill acrylic compounds or the epoxylite of the bump array structure after bonding.
9. the preparation technology of the bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure described in any one in claim 1 to 6, it is characterized in that, described substrate is provided with layer of metal coating, described bump array structure one end and described coat of metal bonding, and the other end connects described epitaxial wafer; Comprise the following steps:
1), on epitaxial wafer fabrication cycle photoengraving pattern, periodically photoengraving pattern is around the pyramid, prism, round platform or the cylindrical space that form some arrays; Described substrate is metal substrate or silicon substrate;
2), at epitaxial wafer and photoengraving pattern surface, prepare complex metal layer;
3), adopt and remove photoresist after solution removal photoengraving pattern, the salient point array that formation complex metal layer forms;
4), the Gold plated Layer bonding on bump array structure and substrate.
10. preparation technology claimed in claim 9, is characterized in that, further comprising the steps of:
5), in the salient point gap after bonding, fill acrylic compounds or epoxylite.
CN201310665416.0A 2013-12-10 2013-12-10 The bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure and technique Active CN103700752B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310665416.0A CN103700752B (en) 2013-12-10 2013-12-10 The bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure and technique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310665416.0A CN103700752B (en) 2013-12-10 2013-12-10 The bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure and technique

Publications (2)

Publication Number Publication Date
CN103700752A true CN103700752A (en) 2014-04-02
CN103700752B CN103700752B (en) 2016-12-07

Family

ID=50362220

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310665416.0A Active CN103700752B (en) 2013-12-10 2013-12-10 The bump bonding structure of a kind of light emitting diode (LED) chip with vertical structure and technique

Country Status (1)

Country Link
CN (1) CN103700752B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623059A (en) * 2017-08-31 2018-01-23 西安交通大学 A kind of composite transferring substrat structure and preparation technology for reducing laser lift-off energy threshold
CN111326949A (en) * 2018-12-15 2020-06-23 深圳市中光工业技术研究院 Laser chip manufacturing method and laser chip
CN111599704A (en) * 2020-06-01 2020-08-28 深圳市美科泰科技有限公司 Method for constructing salient points of integrated circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050082556A1 (en) * 2003-10-16 2005-04-21 Ying-Che Sung InGaN-based led
CN1731592A (en) * 2005-08-26 2006-02-08 杭州士兰明芯科技有限公司 Flip-chip bonded structure light-emitting diode and its manufacture method
CN101005107A (en) * 2006-01-19 2007-07-25 杭州士兰明芯科技有限公司 Flip-chip light emitting diode with metal convex spot array structure and its producing method
CN101241963A (en) * 2007-12-12 2008-08-13 厦门三安电子有限公司 A film LED chip part based on compound low-resistance buffer structure and its making method
CN102598236A (en) * 2009-11-09 2012-07-18 索尼化学&信息部件株式会社 Adhesive composition

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050082556A1 (en) * 2003-10-16 2005-04-21 Ying-Che Sung InGaN-based led
CN1731592A (en) * 2005-08-26 2006-02-08 杭州士兰明芯科技有限公司 Flip-chip bonded structure light-emitting diode and its manufacture method
CN101005107A (en) * 2006-01-19 2007-07-25 杭州士兰明芯科技有限公司 Flip-chip light emitting diode with metal convex spot array structure and its producing method
CN101241963A (en) * 2007-12-12 2008-08-13 厦门三安电子有限公司 A film LED chip part based on compound low-resistance buffer structure and its making method
CN102598236A (en) * 2009-11-09 2012-07-18 索尼化学&信息部件株式会社 Adhesive composition

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623059A (en) * 2017-08-31 2018-01-23 西安交通大学 A kind of composite transferring substrat structure and preparation technology for reducing laser lift-off energy threshold
CN107623059B (en) * 2017-08-31 2019-08-23 西安交通大学 A kind of composite transferring substrat structure and preparation process reducing laser lift-off energy threshold
CN111326949A (en) * 2018-12-15 2020-06-23 深圳市中光工业技术研究院 Laser chip manufacturing method and laser chip
CN111599704A (en) * 2020-06-01 2020-08-28 深圳市美科泰科技有限公司 Method for constructing salient points of integrated circuit

Also Published As

Publication number Publication date
CN103700752B (en) 2016-12-07

Similar Documents

Publication Publication Date Title
US7989948B2 (en) Chip package structure and method of fabricating the same
CN104690383B (en) Between a kind of all-metal, compound interconnects preparation method and the structure of solder joint
US20110121326A1 (en) Submount Having Reflective Cu-Ni-Ag Pads Formed Using Electroless Deposition
US8970053B2 (en) Semiconductor package having light-emitting-diode solder-bonded on first and second conductive pads separated by at least 75 UM
CN103928300B (en) A kind of bonding method based on multi-scenarios method
CN103700752A (en) Salient point bonding structure of vertical structure LED chip and process
JP2012015438A (en) Semiconductor light emitting device
CN104078431A (en) Packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill
CN108963050A (en) A kind of small spacing LED chip and preparation method thereof
US20140021603A1 (en) Using an interconnect bump to traverse through a passivation layer of a semiconductor die
US20120153329A1 (en) Wafer substrate bonding structure and light emitting device comprising the same
CN104409434A (en) Package structure of semiconductor device
TW200847357A (en) Integrated circuit package with soldered lid for improved thermal performance
CN102324409A (en) Semiconductor package with heat dispersion structure and manufacturing method for semiconductor package
CN102522695A (en) Nano silver soldering paste packaged 60-watt 808-nano high-power semiconductor laser module and packaging method thereof
US20150327360A1 (en) Mounting carrier and method of mounting a mounting carrier on a connecting carrier
CN105244425A (en) Flip-chip LED (light-emitting diode) chip and manufacturing method for electrodes of flip-chip LED chip
CN104217969A (en) Semiconductor device packaging method
JP6299494B2 (en) Light emitting device and manufacturing method thereof
TWI426630B (en) A packaging method for light emitting die and structure thereof
CN208400879U (en) A kind of small spacing LED chip
CN203760508U (en) All-metal structure LED packaging support
JP2018520515A (en) Component comprising a metal carrier and method for manufacturing the component
CN207458983U (en) LED ultraviolet sources
CN102244021B (en) Low-k chip encapsulating method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240123

Address after: Room 1027, 1st Floor, JuGou Hongde Building, No. 20, West China Science and Technology Innovation Port, Fengxi New City, Xixian New District, Xi'an City, Shaanxi Province, China, 710061

Patentee after: Core Optics Technology (Shaanxi) Co.,Ltd.

Country or region after: China

Address before: Beilin District Xianning West Road 710049, Shaanxi city of Xi'an province No. 28

Patentee before: XI'AN JIAOTONG University

Country or region before: China