CN103700649B - Photoetching mark applying epitaxial technology and method thereof - Google Patents
Photoetching mark applying epitaxial technology and method thereof Download PDFInfo
- Publication number
- CN103700649B CN103700649B CN201210367921.2A CN201210367921A CN103700649B CN 103700649 B CN103700649 B CN 103700649B CN 201210367921 A CN201210367921 A CN 201210367921A CN 103700649 B CN103700649 B CN 103700649B
- Authority
- CN
- China
- Prior art keywords
- photo
- dielectric layer
- etching
- etching mark
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a photoetching mark applying an epitaxial technology and a method thereof. The photoetching mark is put in a medium material, and any outer boundary or outer interface is surrounded by an epitaxial protecting layer which is hard to grow. The photoetching mark is thoroughly isolated from a silicon material, and the influence of epitaxial growth on the photoetching mark is thoroughly solved.
Description
Technical field
The present invention relates to the semiconductor making method in a kind of microelectronic chip manufacture field.
Background technology
Epitaxy technique in semiconductor fabrication is a kind of common film-forming process.But in epitaxial growth, picture distortion
It is a kind of relatively common phenomenon.And picture distortion can affect follow-up lithography alignment accuracy, thus restricting the alignment essence of photoetching
Degree, limits exploitation and the manufacture of small size epitaxial device.How to avoid or reduce the picture distortion amount producing during epitaxial growth,
For improving photoetching alignment precision, there is very important meaning.
Alignment mark before common epitaxy technique generally adopts direct etching silicon substrate to produce, and therefore it is distorted by extension
Impact is very big, and therefore its alignment precision is generally than relatively low.
In order to solve the problems, such as the pattern alignment after epitaxial growth, some new methods are suggested, and main thought is right
Some protection materials are filled in fiducial mark note, when making epitaxial growth, photo-etching mark region not grown epitaxial layer, or by delaying outward,
By the use of protective layer as etch stop layer, etching epitaxial material thereon, form alignment mark.
Using the impact to photo-etching mark for the extension can be obviously improved after said method, but in epitaxial growth thickness very
Thickness, or epitaxial selective be not well in the case of, that is, on protective layer epitaxial growth speed still compare high in the case of, effect
Unsatisfactory, as represented by Fig. 1,2.Because even being selective epitaxial growth, generally produce monocrystal silicon on a silicon substrate, and
It is polysilicon on other materials.Raw on the interface of silicon and other materials, the monocrystal silicon that silicon substrate is grown up and other materials
The interface of long polysilicon is by broadening, and extends to other materials region from silicon substrate.And now because outside photo-etching mark
Still there are silicon materials in boundary and interface, therefore when epitaxial growth rate is very fast, growth thickness is thicker, or select than high when, from
The monocrystal silicon growing up on silicon substrate can extend to photo-etching mark region, lead to photo-etching mark can cannot be formed or be formed bad, lead
Cause measurement result inaccurate.
Affected although reducing photo-etching mark using protective layer by epitaxy technique in conventional methods where, but because entirely right
Still there is the part contacting with silicon in fiducial mark note, and the protection materials on photo-etching mark still can be covered by extension with technique change
Lid.
Equally, all utilization silicon and other materials interface formed photo-etching mark, equally can be epitaxially grown this
One characteristic is affected.Therefore to thoroughly solve the impact to photo-etching mark for the epitaxy technique, be necessary for being formed using non-silicon material,
And completely cut off the contact that photo-etching mark is with silicon materials.
Content of the invention
The technical problem to be solved is to provide a kind of photo-etching mark being applied to epitaxy technique, and it can be by light
Marking thoroughly completely cuts off with silicon materials, thoroughly solves the impact to photo-etching mark for the epitaxial growth.
In order to solve above technical problem, the invention provides a kind of photo-etching mark being applied to epitaxy technique, light blaze
Note is placed in dielectric material, and the protective layer that any one external boundary or outer boundary all are difficult to grow by extension surrounds.
The beneficial effects of the present invention is：Photo-etching mark is thoroughly completely cut off with silicon materials, thoroughly solves epitaxial growth pair
The impact of photo-etching mark.
It is difficult to during epitaxial growth grow on the protection layer, growth rate is less compared with the growth rate on substrate layer.
Protective layer can be with oxide or nitride.
After epitaxial growth, dielectric layer and non-dielectric layer Epitaxial growth thickness difference >=200 angstrom.
Whole photo-etching mark is all surrounded by dielectric layer region.
Present invention also offers a kind of method that generation is applied to the photo-etching mark of epitaxy technique, comprise the following steps：Step
Rapid 1, etching silicon substrate forms the larger groove of an area；Step 2, deposition or pass through thermal oxide filled media material in the trench
Material, forms the substrate of photo-etching mark；Step 3, in basal region etch media layer formed photo-etching mark.
Dielectric layer etching depth >=500 angstrom in step 2.
Dielectric layer etching depth >=200 angstrom in step 3, and the 1/2 × selection ratio less than subsequently epitaxial growing thickness, choosing
Select than the ratio for dielectric layer and non-dielectric layer area epitaxy growth thickness.
From silicon area to more than 2 times of areas of dielectric development length during photo-etching mark prohibited area >=epitaxial growth.
Brief description
With reference to the accompanying drawings and detailed description the present invention is described in further detail.
Figure 1A present invention and conventional lithography labelling section comparison diagram；
Figure 1B present invention shows comparison diagram with conventional lithography labelling light；
The layout design figure of Fig. 2 this patent photo-etching mark；
Fig. 3 photo-etching mark forming process schematic diagram.
Specific embodiment
A kind of photo-etching mark being applied to epitaxy technique of the present invention, photo-etching mark is placed in dielectric material,
And the material that any one external boundary or outer boundary all are difficult to grow by extension surrounds.
Its implementation comprises two parts, and domain is realized and technological process.
Its domain is realized as represented by Fig. 2.Constitute a dielectric layer basal region, realized by light shield one.Constitute photoetching
Marker graphic, is realized by light shield two, and figure contains two parts, photo-etching mark region and photo-etching mark itself.Photo-etching mark area
The figure that domain non-genuine is formed, is used only to the region of labelling photo-etching mark formation it is ensured that photo-etching mark and dielectric layer basal area
Form a prohibited area, its size meets during photo-etching mark prohibited area >=epitaxial growth from silicon area to Jie between domain
More than 2 times of matter region development length.Wherein epitaxial growth when from silicon area to areas of dielectric development length pass through technique survey
Scale is levied.Originally as the reality pictures on light shield two, its type can be in alignment with labelling (alignment mark) to photo-etching mark,
The housing of alignment precision measurement markers or inside casing (out box/inner box in Overlay mark), critical size measures
Labelling (CD mark) or the other kinds of figure being applied to photoetching process measurement or characterizing.Photo-etching mark is in photoetching in itself
In marked region, photo-etching mark prohibited area must not be entered
Its technological process is as represented in fig. 3
Step 1, using light shield one pass through photoetching, etching silicon substrate define dielectric layer basal region
Step 2, dielectric layer basal region pass through deposition or thermal oxide filled media material, formed photo-etching mark substrate
Region
Step 3, using light shield two pass through photoetching, etching basal region inner medium layer formed photo-etching mark.
Used dielectric layer basal region material is usually during epitaxial growth and is difficult to growth or growth rate on the protection layer
There is significantly different (general substrate layer is silicon) with substrate layer.
For the sake of simple process, protective layer can be conventional oxide in semiconductor manufacturing or nitride it is also possible to
Using other, there is the material of same characteristic features.It is usually SiO2 it is also possible to doping B, the impurity material such as P is to improve it in extension life
Selection ratio in length.
Its growth rate and substrate layer have visibly different be characterized mainly in that epitaxial growth after, dielectric layer and non-dielectric layer
Epitaxial growth thickness difference >=200 angstrom, generally for CL or F system gas growing epitaxial silicon technique as etching gas is used,
Can ensure that and silicon epitaxy layer is hardly grown on SiO2.
Dielectric layer etching depth >=500 angstrom in step 1.But generally all relatively deep, 0.5～10um can be selected.For depositing
Technique at deep plough groove etched (etching silicon substrate, and depth >=1um), it is possible to use deep plough groove etched realization
After step 2 filled media material, a step can be added and return quarter or CMP, remove beyond dielectric layer basal region
Silicon substrate on dielectric material it is ensured that subsequently epitaxial growing can directly be carried out on a silicon substrate.But must assure that dielectric layer
The deielectric-coating of base area is not less than silicon substrate, or both differences in height<500 angstroms
Etching in step 3 etches for dielectric layer, it is necessary to assure have sufficient medium between photo-etching mark bottom and silicon substrate
Layer isolation, it remains thickness of dielectric layers >=1000 angstrom.
Etching depth >=200 angstrom in step 3, effect preferably can be 500 angstroms～1500 angstroms.And can be with here
The measurement integral multiple of wavelength or the half of integral multiple is added on the basis of depth.Such as measurement wavelength is 6328 angstroms of HONGGUANG, then may be used
Increase by 6328 angstroms with depth on the basis of 500～1500 angstroms or 6328 angstroms of half are 3164 angstroms of integral multiple.
Etching depth in step 3 can not be too big, if because epitaxy technique silicon and dielectric material selection are higher than too, carved
Erosion gas flow is a lot, and deposition velocity is slower, now in order to improve deposition velocity, can select to drop low selection ratio, on dielectric layer according to
So meeting growth part epitaxial material, now must assure that epitaxial material can not fill photo-etching mark region.Therefore step 3 etches depth
Degree need less than and less than subsequently epitaxial growing thickness 1/2 × select ratio, select than for outside dielectric layer and non-dielectric layer region
The ratio of epitaxial growth thickness.Ensure to be filled up completely with by extension in photo-etching mark, and photo-etching mark size during layout design
It is less than 1/2 × selection ratio of subsequently epitaxial growing thickness.
In this patent method, photo-etching mark is thoroughly completely cut off with silicon materials, thoroughly solves epitaxial growth to photo-etching mark
Impact.
The present invention is not limited to embodiment discussed above.Description to specific embodiment is intended to retouch above
State and illustrate technical scheme according to the present invention.Obvious conversion based on present invention enlightenment or replacement should also be as being considered
Fall into protection scope of the present invention.Above specific embodiment is used for disclosing the optimal implementation of the present invention, so that this
The those of ordinary skill in field can apply the numerous embodiments of the present invention and multiple alternative to reach the present invention's
Purpose.
Claims (7)
1. a kind of photo-etching mark being applied to epitaxy technique is it is characterised in that photo-etching mark is placed in the dielectric layer and any
The dielectric layer that one external boundary all is difficult to grow by extension surrounds；
Described dielectric layer is formed in the groove being formed after silicon substrate etching, and the forming region of described dielectric layer is dielectric layer base
Bottom region, described photo-etching mark is formed in photo-etching mark region, and described photo-etching mark is by more than one to described dielectric layer
The medium groove composition being formed after performing etching；Described dielectric layer is equal with the surface of described silicon substrate, described dielectric layer substrate
Region and described photo-etching mark region are defined by photoetching process respectively, and described photo-etching mark region is located at described dielectric layer substrate
Intra-zone, the described dielectric layer basal region outside described photo-etching mark region is photo-etching mark prohibited area, and photo-etching mark is prohibited
Only the lateral dimension in region is more than or equal to during epitaxial growth from silicon area to 2 times of areas of dielectric development length.
2. it is applied to the photo-etching mark of epitaxy technique as claimed in claim 1 it is characterised in that being difficult to during epitaxial growth be situated between
Grow on matter layer, growth rate is less compared with the growth rate on silicon substrate.
3. it is applied to the photo-etching mark of epitaxy technique as claimed in claim 1 or 2 it is characterised in that dielectric layer is oxide
Or nitride.
4. it is applied to the photo-etching mark of epitaxy technique as claimed in claim 3 it is characterised in that after epitaxial growth, dielectric layer
With non-dielectric layer Epitaxial growth thickness difference >=200 angstrom.
5. a kind of generation is applied to the method for the photo-etching mark of epitaxy technique it is characterised in that comprising the following steps：
Step 1, etching silicon substrate form a groove, and the region of groove is defined by photoetching process；
Step 2, deposition or pass through thermal oxide filled media layer in the trench, formed photo-etching mark substrate；Described dielectric layer
Forming region is dielectric layer basal region,
Step 3, define photo-etching mark region and photo-etching mark figure using photoetching process, described photo-etching mark region is located at institute
State inside dielectric layer basal region, the described dielectric layer basal region outside described photo-etching mark region is photo-etching mark exclusion area
Domain, the lateral dimension of photo-etching mark prohibited area is more than or equal to during epitaxial growth from silicon area to the 2 of areas of dielectric development length
Times；
Formation photo-etching mark is performed etching to described dielectric layer, photo-etching mark is placed in the dielectric layer, and outside any one
The dielectric layer that boundary all is difficult to grow by extension surrounds；Described photo-etching mark is formed in photo-etching mark region, described smooth blaze
Note by more than one described dielectric layer is performed etching after the medium groove that formed form.
6. generation as claimed in claim 5 is applied to the method for the photo-etching mark of epitaxy technique it is characterised in that in step 1
Dielectric layer etching depth >=500 angstrom.
7. generation as claimed in claim 6 is applied to the method for the photo-etching mark of epitaxy technique it is characterised in that in step 3
Dielectric layer etching depth >=200 angstrom, and less than subsequently epitaxial growing thickness 1/2 × select ratio, select than for dielectric layer with
The ratio of non-dielectric layer area epitaxy growth thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210367921.2A CN103700649B (en) | 2012-09-28 | 2012-09-28 | Photoetching mark applying epitaxial technology and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210367921.2A CN103700649B (en) | 2012-09-28 | 2012-09-28 | Photoetching mark applying epitaxial technology and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103700649A CN103700649A (en) | 2014-04-02 |
| CN103700649B true CN103700649B (en) | 2017-02-15 |
Family
ID=50362131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210367921.2A Active CN103700649B (en) | 2012-09-28 | 2012-09-28 | Photoetching mark applying epitaxial technology and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103700649B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314837A (en) * | 1992-06-08 | 1994-05-24 | Analog Devices, Incorporated | Method of making a registration mark on a semiconductor |
| CN101320215A (en) * | 2008-06-02 | 2008-12-10 | 中国电子科技集团公司第五十五研究所 | Photo-etching mark on semiconductor material and its production method |
| CN101882570A (en) * | 2009-05-04 | 2010-11-10 | 上海华虹Nec电子有限公司 | Method for improving alignment precision after epitaxial growth |
| CN103676485A (en) * | 2012-09-04 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Photoetching alignment marking structure for thick epitaxy process |
-
2012
- 2012-09-28 CN CN201210367921.2A patent/CN103700649B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314837A (en) * | 1992-06-08 | 1994-05-24 | Analog Devices, Incorporated | Method of making a registration mark on a semiconductor |
| CN101320215A (en) * | 2008-06-02 | 2008-12-10 | 中国电子科技集团公司第五十五研究所 | Photo-etching mark on semiconductor material and its production method |
| CN101882570A (en) * | 2009-05-04 | 2010-11-10 | 上海华虹Nec电子有限公司 | Method for improving alignment precision after epitaxial growth |
| CN103676485A (en) * | 2012-09-04 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Photoetching alignment marking structure for thick epitaxy process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103700649A (en) | 2014-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102969353B (en) | Many fin devices and its manufacture method | |
| CN105097649B (en) | The forming method of semiconductor structure | |
| CN103151261B (en) | Trench Schottky diode and manufacturing method thereof | |
| KR20140111575A (en) | Finfet with rounded source/drain profile | |
| KR100559518B1 (en) | Method for formating sti in semiconductor | |
| CN104347346A (en) | Method for flattening deep grooves with different structures | |
| CN103137434A (en) | Manufacture method of silica-based GaN film | |
| CN104882436A (en) | Preparation method for lithography alignment mark in two epitaxial processes | |
| CN103578968B (en) | The structure of holohedral form silicon epitaxy process photoetching alignment mark and making method | |
| CN103872019B (en) | It is applied to photo-etching mark and the manufacture method thereof of epitaxy technique | |
| US8603889B2 (en) | Integrated circuit structure having air-gap trench isolation and related design structure | |
| TWI434372B (en) | Method of forming a trench by a silicon-containing mask | |
| CN103700649B (en) | Photoetching mark applying epitaxial technology and method thereof | |
| CN104779241A (en) | Photoetching mark manufacturing method in epitaxy technology | |
| CN105047647B (en) | The production method of photoetching alignment mark in thick epitaxy technique | |
| CN102386056A (en) | Semiconductor device and manufacturing method thereof | |
| CN105633070B (en) | A kind of semiconductor devices and preparation method thereof | |
| CN105489501B (en) | The manufacturing method of groove-shaped super junction | |
| CN103227143A (en) | Shallow trench isolation technology | |
| CN107248495B (en) | Method for forming high aspect ratio isolation in high-energy ion implantation process | |
| CN108122762B (en) | Semiconductor structure and forming method thereof | |
| CN101882570A (en) | Method for improving alignment precision after epitaxial growth | |
| CN109148560A (en) | The manufacturing method of groove-shaped super junction | |
| CN105789049B (en) | The method for patterning multiple components of fin formula field effect transistor (FINFET) device | |
| CN104064564B (en) | Bipolar integrated circuit chip based on groove dielectric isolation and production technology thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |