CN109148560A - The manufacturing method of groove-shaped super junction - Google Patents
The manufacturing method of groove-shaped super junction Download PDFInfo
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- CN109148560A CN109148560A CN201810919990.7A CN201810919990A CN109148560A CN 109148560 A CN109148560 A CN 109148560A CN 201810919990 A CN201810919990 A CN 201810919990A CN 109148560 A CN109148560 A CN 109148560A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000006396 nitration reaction Methods 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000002203 pretreatment Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 239000011800 void material Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention discloses a kind of manufacturing methods of groove-shaped super junction, comprising steps of Step 1: forming the hard mask layers being formed by stacking by the first oxide layer, the second nitration case and third oxide layer on the first conductive type epitaxial layer surface；Step 2: forming multiple grooves, including step by step: step 21 opens groove forming region；Step 22, the first opening that hard mask layers are performed etching and form hard mask layers；Step 23 performs etching to form groove to the first conductive type epitaxial layer；Step 3: carrying out laterally returning to carve to the second nitration case that the enlarged open third of the second nitration case is made to be open；Step 4: removal third oxide layer；Step 5: forming sacrificial oxide layer and removing, the second opening of the top of the groove, which can be expanded to, tends to be equal with the width of third opening；Step 6: carrying out being epitaxially-formed the second conductive type epitaxial layer and composition super junction.The present invention can eliminate the dislocation defects and cavity blemish of the epitaxial layer filled in the trench.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of groove-shaped super junction
Manufacturing method.
Background technique
Super junction is to be made of the alternately arranged p-type thin layer and N-type thin layer that are formed in semiconductor substrate, existing super
It include the manufacturing method of groove-shaped super junction in the manufacturing method of knot, this method is to make super junction device by trench process
Part needs first to etch the groove of certain depth and width on the n-type doping epitaxial layer of semiconductor substrate such as surface of silicon, so
It fills the silicon epitaxy of p-type doping on the groove carved in the way of extension filling (EPI Filling) afterwards, and requires to fill out
Region is filled with intact crystal structure, so that follow-up process makes high performance device.The maximum difficult point of this technique is
Silicon epitaxy is filled in the trench.
In super-junction device, the primitive unit cell size (pitch) of the groove of super junction is designed as the width of p-type column by five generation structures
Ratio=1:1.5 of the width of degree and N-type column, the method that wherein p-type column generallys use trench fill p-type epitaxial layer obtains, small
The device of size is very helpful for reducing RDSON parameter, can effectively improve the performance of device, but in device making technics
Very big difficulty is increased in the process, especially critical process, that is, deep trench extension filling.
In existing method, the groove of super junction is generallyd use to be aoxidized by the first oxide layer, the second nitration case and third and is laminated
The definition of hard mask layers made of adding can remove third oxide layer, later to the inside table of groove after etching groove completion
Face forms sacrificial oxide layer and is removing, and after sacrificial oxide layer removal, can remove the second nitration case again, can also retain the second nitrogen
Change layer, using the first oxide layer or the second nitration case is again later that exposure mask realizes progress selective epitaxial growth in the trench and by ditch
Slot filling.Existing method dislocation easy to form (dislocation) defect, and while remaining the second nitration case, is also easy to form sky
Hole (void) defect.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of groove-shaped super junction, can eliminate in groove
The dislocation defects and cavity blemish of the epitaxial layer of middle filling improve the quality for the epitaxial layer filled in groove and and then improve device
Performance.
In order to solve the above technical problems, the manufacturing method of groove-shaped super junction provided by the invention includes the following steps:
Step 1: providing semi-conductive substrate, it is formed with the first conductive type epitaxial layer in the semiconductor substrate surface,
Hard mask layers are formed on first conductive type epitaxial layer surface, the hard mask layers are by being sequentially formed in described first
First oxide layer, the second nitration case and the third oxide layer on conductive type epitaxial layer surface are formed by stacking.
Step 2: forming multiple grooves in first conductive type epitaxial layer using lithographic etch process, including such as
Under step by step:
Step 21, in the hardmask layer surface coating photoresist, carry out photoetching process for the groove forming region
It opens.
Step 22 performs etching the hard mask layers using the photoresist as mask, and the etching technics is by the ditch
The hard mask layers of slot forming region remove and are formed the first opening, and the hard mask layers outside the groove retain.
Step 23, the removal photoresist, are mask to first conductive type epitaxial layer using the hard mask layers
It performs etching to form the groove, the top of the groove has the second opening, what second opening and described first were open
It is of same size.
It is carved Step 3: laterally return to second nitration case from two sides of first opening, Hui Kehou's
Second nitration case forms the third opening after expanding, and the width of the third opening is greater than the width of first opening.
Step 4: the third oxide layer is removed, first oxide layer during removing the third oxide layer
Also can be by lateral etching, first oxide layer after lateral etching forms the 4th opening after expanding, the 4th opening
Width is greater than the width of third opening.
Step 5: forming sacrificial oxide layer and removing, the sacrificial oxide layer is by described first to the flute surfaces
Conductive type epitaxial layer carries out oxidation formation, and the second opening for removing the top of the groove after the sacrificial oxide layer can expand
Greatly, the opening of third described in step 3 is used to offset the expansion of second opening relative to the expansion value of first opening
The width of value, second opening after making the third be open and expand tends to be equal.
Step 6: be epitaxially-formed the second conductive type epitaxial layer, second conductive type epitaxial layer is by institute
It states groove to be filled up completely, the width of second opening after being open and expand using the third tends to equal structure and improves
The quality of epitaxial growth；By filling described the between second conductive type epitaxial layer and the groove in the groove
One conductive type epitaxial layer is alternately arranged composition super junction.
A further improvement is that the semiconductor substrate is silicon substrate, first conductive type epitaxial layer is led for first
Electric type silicon epitaxy layer, second conductive type epitaxial layer are the second conduction type silicon epitaxy layer.
A further improvement is that the material of first oxide layer and the third oxide layer is all silica；Described
The material of nitride layer is silicon nitride.
A further improvement is that first oxide layer is thermal oxide layer, with a thickness of 100 Ethylmercurichlorendimides~2000 Ethylmercurichlorendimides；It is described
Second nitration case with a thickness of 100 Ethylmercurichlorendimides~1500 Ethylmercurichlorendimides；The third oxide layer with a thickness of 0.5 micron~3 microns.
A further improvement is that the size of the lateral etching of second nitration case is 0.1 micron, described in step 3
The width of third opening is 0.2 micron bigger than the width of first opening.
A further improvement is that the ratio of the spacing between the width of the groove and the groove is 1:1.5.
A further improvement is that the first conduction type is N-type, the second conduction type is p-type；Alternatively, the first conduction type
For p-type, the second conduction type is N-type.
A further improvement is that the semiconductor substrate is N-type heavy doping.
A further improvement is that the bottom of the groove is located in first conductive type epitaxial layer.
It is carved a further improvement is that laterally return to second nitration case using wet-etching technology in step 3.
A further improvement is that removing the third oxide layer using wet-etching technology in step 4.
A further improvement is that thermal oxidation technology forms the sacrificial oxide layer in step 5.
A further improvement is that removing the sacrificial oxide layer using wet-etching technology in step 5.
A further improvement is that after step 5 removes the sacrificial oxide layer and step 6 to carry out the extension raw
Before length, further include the steps that carrying out pre-treatment to the groove.
A further improvement is that the step of carrying out pre-treatment to the groove includes:
Carry out H2Baking；
Carry out HCl etching.
The present invention after the trenches are formed, has done particularly the size of the opening of the second nitration case in hard mask layers
Setting, mainly before the removal of third oxide layer, the characteristics of using the top and bottom of the second nitration case being all oxide layer, is real
The lateral etching of the second nitration case now pair, so that the opening of the second nitration case, which becomes larger, become greater to third opening, third opening
Need to be greater than opening i.e. the second opening of the top of the groove at this time；In this way by subsequent removal third oxide layer and to groove
Inner surface carry out sacrificial oxide layer growth and removal after, even if sacrificial oxide layer growth and removal technique can make ditch
Slot becomes large-sized, and the width that the top opening of groove i.e. second is open can also become larger, but since the present invention is in advance by second
The width that the opening of nitration case is open from the width expansion of the first opening to third, and the second opening after third opening and expansion
Width tend to be equal；It is raw that extension is carried out again under conditions of the width of the second opening after third is open and expands tends to be equal
Long, the process gas of at this moment epitaxial growth, which can be entered well in groove, to be realized epitaxial growth and can prevent in the second nitration case
Opening it is smaller when generated filling cavity appearance；Simultaneously as the second nitration case retains in epitaxial growth, therefore can prevent
Epitaxial layer can also be formed by the surface in lateral etching region in the first oxide layer when only removing the second nitration case, so as to prevent
First oxide layer generates dislocation defects when forming epitaxial layer by the surface in lateral etching region；So the present invention can be eliminated in ditch
The dislocation defects and cavity blemish for the epitaxial layer filled in slot improve the quality for the epitaxial layer filled in groove and and then improve device
The performance of part.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 F is the device architecture schematic diagram in each step of manufacturing method of the first existing groove-shaped super junction；
Fig. 2A is the corresponding photo of structure of Fig. 1 E；
Fig. 2 B is the corresponding photo of structure of Fig. 1 F；
Fig. 3 A- Fig. 3 B is the device architecture schematic diagram in each step of manufacturing method of existing second groove-shaped super junction；
Fig. 4 A is the corresponding photo of structure of Fig. 3 A；
Fig. 4 B is the corresponding photo of structure of Fig. 3 B；
Fig. 5 is the flow chart of present invention method；
Fig. 6 A- Fig. 6 E is the device architecture signal in each step of manufacturing method of the groove-shaped super junction of the embodiment of the present invention
Figure.
Specific embodiment
Problem possessed by the manufacturing method of existing groove-shaped super junction is introduced first, and the present invention is exactly directed to these
Technical problem has done specific improvement:
Existing first method:
It is the device in each step of manufacturing method of the first existing 201 type super junction of groove as shown in Figure 1A to Fig. 1 F
Structural schematic diagram；The manufacturing method of the first existing 201 type super junction of groove includes the following steps:
Step 1: as shown in Figure 1A, providing semi-conductive substrate 101, the is formed on 101 surface of semiconductor substrate
One conductive type epitaxial layer 102 forms hard mask layers 103, the hard on 102 surface of the first conductive type epitaxial layer
Mask layer 103 is by being sequentially formed in the first oxide layer 103a, second nitration case on 102 surface of the first conductive type epitaxial layer
103b and third oxide layer 103c are formed by stacking.
Step 2: as shown in Figure 1A, being formed in first conductive type epitaxial layer 102 using lithographic etch process more
A groove 201, including as follows step by step:
Step 21, in the 103 surface coating photoresist of hard mask layers, carry out photoetching process for 201 shape of groove
It is opened at region.
Step 22 performs etching the hard mask layers 103 using the photoresist as mask, which will be described
The hard mask layers 103 of 201 forming region of groove remove, and the hard mask layers 103 outside the groove 201 retain.
Step 23, the removal photoresist are mask to the first conduction type extension with the hard mask layers 103
Layer 102 performs etching to form the groove 201.
Step 3: as shown in Figure 1B, the third oxide layer 103c is removed, in the mistake for removing the third oxide layer 103c
First oxide layer 103a described in journey also can be by lateral etching, and the first oxide layer 103a is by the region of lateral etching such as dotted line
Shown in frame 202.
Step 4: as shown in Figure 1 C, forming sacrificial oxide layer 203；As shown in figure iD, sacrificial oxide layer 203 is removed.It is described
Sacrificial oxide layer 203 carries out oxidation formation by first conductive type epitaxial layer 102 to 201 surface of groove, removal
The size of the groove 201 can become larger after the sacrificial oxide layer 203.The first oxide layer 103a by lateral etching
Region 202 also will increase.
Step 5: as referring to figure 1E, removing the second nitration case 103b.
Step 6: as shown in fig. 1F, carrying out being epitaxially-formed the second conductive type epitaxial layer 104, described second is conductive
The groove 201 is filled up completely by type epitaxial layer 104；By filling the second conduction type extension in the groove 201
First conductive type epitaxial layer 102 between layer 104 and the groove 201 is alternately arranged composition super junction.
In the above method, conduction type is usual are as follows: the first conduction type is N-type, and the second conduction type is p-type, by filling
Second conductive type epitaxial layer 104 in the groove 201 forms p-type column, by described first between the groove 201
Conductive type epitaxial layer 102 forms N-type column.
As shown in Fig. 1 F it is found that since the first oxide layer 103a can be by lateral etching, in first oxide layer
First conductive type epitaxial layer, 102 surface described in region 202 of the 103a by lateral etching directly exposes, in this way in epitaxial growth
It is middle to form epitaxial layer on 102 surface of the first conductive type epitaxial layer in region 202 and first oxygen can be extended to
The surface for changing layer 103a can make the second conductive type epitaxial layer 104 eventually formed generate dislocation near region 202 and lack
It falls into, the regional location of dislocation defects is as shown in virtual coil 203.
It as shown in Figure 2 A, is the corresponding photo of structure of Fig. 1 E；As can be seen that before epitaxial growth, N-type epitaxy layer
102 width dimensions are 1.17 μm, only 0.74 μm of the width of the first oxide layer 103a, laterally return first oxygen before carving
The width for changing layer 103a and N-type epitaxy layer 102 should be equal, so the two sides of the first oxide layer 103a are by lateral etching
About 0.44 μm of the width in region 202, about 38% N-type epitaxy layer 102 is exposed to outside.It carries out selective epitaxial and fills ditch
When slot 201, be exposed to outer N-type epitaxy layer 102 above also can growing P-type epitaxial layer 104, and rapidly in first oxide layer
Merge (merge) on 103a and generate stress, occurs dislocation defect when to making trench fill, such as the void in Fig. 2 B
Shown in coil 203.
Existing second method:
It is the device architecture in each step of manufacturing method of existing second groove-shaped super junction as shown in Fig. 3 A to Fig. 3 B
Schematic diagram；In place of the difference of existing first method are as follows:
Existing second method is on the basis of existing first method, after completing step 4, without step
Five, directly retain and carries out epitaxial growth in the case of the second nitration case 103b.
The structural schematic diagram of Fig. 3 A is identical with Fig. 1 D, in order to which the opening of vivider expression the second nitration case 103b is small
In the top opening of the groove 201, it is added to dotted line 204 corresponding with the side of the groove 201 in figure 3 a.It can be with
Find out, the opening of the groove 201 and the opening superposition of the second nitration case 103b form that the small bottom in a top is big to open
Mouthful, the big opening in this small bottom in top is highly detrimental to the filling of groove, is easy in epitaxial growth at the top of groove 201
First merge, to be easy to produce cavity blemish in groove 201, cavity blemish is as shown in virtual coil 205.Simultaneously the 201 of groove
Top be also still easy to produce dislocation defects.
Fig. 4 A is the corresponding photo of structure of Fig. 3 A；As can be seen that the width dimensions of groove 201 are about 1.3um, and it is described
Second nitration case 103b opening width size only 1.1um.Carry out groove 201 fill when, the second nitration case 103b compared with
Small opening size enters the reaction that groove 201 carries out epitaxial growth for gas is unfavorable for, and causes to be easy when groove 201 is filled
There is dislocation and void defect, Fig. 4 B is the corresponding photo of structure of Fig. 3 B, and the virtual coil 205 in Fig. 4 B corresponds to
Void defect, virtual coil 206 correspond to dislocation defect.
Present invention method:
As shown in figure 5, being the flow chart of present invention method；It is the embodiment of the present invention as shown in Fig. 6 A to Fig. 6 E
Device architecture schematic diagram in each step of manufacturing method of 302 type super junction of groove, 302 type super junction of groove of the embodiment of the present invention
Manufacturing method include the following steps:
Step 1: as shown in Figure 6A, providing semi-conductive substrate 1, being formed with first on 1 surface of semiconductor substrate and lead
Electric type epitaxial layer 2,2 surface of the first conductive type epitaxial layer formed hard mask layers 3, the hard mask layers 3 by
It is sequentially formed in the first oxide layer 3a, the second nitration case 3b and third oxide layer on 2 surface of the first conductive type epitaxial layer
3c is formed by stacking.
In present invention method, the semiconductor substrate 1 is silicon substrate, and first conductive type epitaxial layer 2 is
First conduction type silicon epitaxy layer, subsequent second conductive type epitaxial layer are the second conduction type silicon epitaxy layer.
The material of the first oxide layer 3a and the third oxide layer 3c are all silica；The second nitration case 3b's
Material is silicon nitride.
The first oxide layer 3a is thermal oxide layer, with a thickness of 100 Ethylmercurichlorendimides~2000 Ethylmercurichlorendimides；The second nitration case 3b's
With a thickness of 100 Ethylmercurichlorendimides~1500 Ethylmercurichlorendimides；The third oxide layer 3c with a thickness of 0.5 micron~3 microns.With a specific example
For can be with are as follows: first oxide layer with a thickness of 1500 Ethylmercurichlorendimides；Second nitration case with a thickness of 1100 Ethylmercurichlorendimides；It is described
Third oxide layer with a thickness of 22000 Ethylmercurichlorendimides.
Step 2: forming multiple grooves 302 in first conductive type epitaxial layer 2 using lithographic etch process, wrap
It includes as follows step by step:
Step 21, as shown in Figure 6A, in the 3 surface coating photoresist of hard mask layers, carrying out photoetching process will be described
302 forming region of groove is opened.
Step 22, as shown in Figure 6A, the hard mask layers 3 are performed etching using the photoresist as mask, the etching
Technique is by the removal of the hard mask layers 3 of 302 forming region of groove and forms the first opening 301, outside the groove 302
The hard mask layers 3 retain.
Step 23, as shown in Figure 6A, remove the photoresist, with the hard mask layers 3 be mask led to described first
Electric type epitaxial layer 2 performs etching to form the groove 302, and the top of the groove 302 has the second opening, and described second opens
Mouth is of same size with first opening 301.
The ratio of spacing between the width and the groove 302 of the groove 302 is 1:1.5.
The bottom of the groove 302 is located in first conductive type epitaxial layer 2.
Step 3: as shown in Figure 6B, being carried out from two sides of first opening 301 to the second nitration case 3b horizontal
It is carved to returning, the second nitration case 3b of Hui Kehou forms the third opening 303 after expanding, the width of the third opening 303
Greater than the width of first opening 301.
In the embodiment of the present invention, the second nitration case 3b laterally return using wet-etching technology and is carved.Described
The size of the lateral etching of nitride layer 3b is 0.1 micron, and the width of the third opening 303 is than first opening 301
Width is 0.2 micron big.
Step 4: as shown in Figure 6 C, the third oxide layer 3c is removed, during removing the third oxide layer 3c
The first oxide layer 3a also can be by lateral etching, and what the first oxide layer 3a after lateral etching was formed after expanding the 4th opens
The width of mouth 304, the 4th opening 304 is greater than the width of third opening 303.
In the embodiment of the present invention, the third oxide layer 3c is removed using wet-etching technology.
Step 5: as shown in Figure 6 D, forming sacrificial oxide layer 305；As illustrated in fig. 6e, the sacrificial oxide layer 305 is removed.
The sacrificial oxide layer 305 is aoxidized by first conductive type epitaxial layer 2 to 302 surface of groove
It is formed, the second opening for removing 302 top of groove after the sacrificial oxide layer 305 can expand, the described in step 3
Three openings 303 are used to offset the expansion value of second opening relative to the expansion value of first opening 301, make the third
The width of second opening after opening 303 and expansion tends to be equal.In Fig. 6 E, dotted line 306 is increased to indicate the ditch
The side of slot 302 is equal with the side of third opening 303.
In the embodiment of the present invention, the sacrificial oxide layer 305 is formed using thermal oxidation technology.It is gone using wet-etching technology
Except the sacrificial oxide layer 305.
After step 5 removes the sacrificial oxide layer 305 and before subsequent step six carries out the epitaxial growth,
Further include the steps that carrying out pre-treatment to the groove 302.Include: to the step of groove 302 progress pre-treatment
Carry out H2Baking；
Carry out HCl etching.
Step 6: be epitaxially-formed the second conductive type epitaxial layer, second conductive type epitaxial layer is by institute
It states groove 302 to be filled up completely, the width of second opening using third opening 303 and after expanding tends to equal knot
The quality of structure raising epitaxial growth；By filling second conductive type epitaxial layer and the groove 302 in the groove 302
Between first conductive type epitaxial layer 2 be alternately arranged composition super junction.
In the embodiment of the present invention, the first conduction type is N-type, and the second conduction type is p-type, and the semiconductor substrate 1 is N
Type heavy doping.Also can in other embodiments are as follows: the first conduction type is p-type, and the second conduction type is N-type.
The embodiment of the present invention is after the formation of groove 302, to the ruler of the opening of the second nitration case 3b in hard mask layers 3
It is very little to have done special setting, mainly third oxide layer 3c removal before, using the second nitration case 3b top and bottom all
The lateral etching of second nitration case 3b of the characteristics of being oxide layer realization pair, becomes larger so that the opening of the second nitration case 3b becomes larger
To third opening 303, the opening that third opening 303 needs to be greater than 302 top of groove at this time is the second opening；Passing through in this way
After the subsequent growth and removal for removing third oxide layer 3c and carrying out sacrificial oxide layer 305 to the inner surface of groove 302,
Even if the growth of sacrificial oxide layer 305 and removal technique can make becoming large-sized for groove 302, the top opening of groove 302 i.e. the
Two opening width can also become larger, but due to the present invention in advance by the opening of the second nitration case 3b from first opening 301 width
Degree is expanded to the width of third opening 303, and the width of the second opening after third opening 303 and expansion tends to be equal；?
The width of the second opening after three openings 303 and expansion carries out epitaxial growth under conditions of tending to be equal again, at this moment epitaxial growth
Process gas can enter well and realized in groove 302 and epitaxial growth and the opening in the second nitration case 3b can be prevented smaller
When generated filling cavity appearance；Simultaneously as the second nitration case 3b retains in epitaxial growth, therefore removal the can be prevented
Epitaxial layer can also be formed by the surface in lateral etching region in the first oxide layer 3a when nitride layer 3b, so as to prevent first
Oxide layer 3a generates dislocation defects when forming epitaxial layer by the surface in lateral etching region；So the embodiment of the present invention can be eliminated
The dislocation defects and cavity blemish for the epitaxial layer filled in groove 302 improve the quality for the epitaxial layer filled in groove 302 simultaneously
And then improve the performance of device.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of groove-shaped super junction, which comprises the steps of:
Step 1: providing semi-conductive substrate, it is formed with the first conductive type epitaxial layer in the semiconductor substrate surface, in institute
It states the first conductive type epitaxial layer surface and forms hard mask layers, the hard mask layers are conductive by being sequentially formed in described first
The first oxide layer, the second nitration case and the third oxide layer of type epi-layer surface are formed by stacking；
Step 2: forming multiple grooves in first conductive type epitaxial layer using lithographic etch process, including divide as follows
Step:
Step 21, in the hardmask layer surface coating photoresist, carry out photoetching process and open the groove forming region；
Step 22 performs etching the hard mask layers using the photoresist as mask, and the etching technics is by the ditch flute profile
The first opening is removed and formed at the hard mask layers in region, and the hard mask layers outside the groove retain；
Step 23, the removal photoresist, carry out first conductive type epitaxial layer using the hard mask layers as mask
Etching forms the groove, and the top of the groove has the second opening, the width of second opening and first opening
It is identical；
It is carved Step 3: laterally return to second nitration case from two sides of first opening, Hui Kehou's is described
Second nitration case forms the third opening after expanding, and the width of the third opening is greater than the width of first opening；
Step 4: removing the third oxide layer, first oxide layer also can during removing the third oxide layer
By lateral etching, first oxide layer after lateral etching forms the 4th opening after expanding, the width of the 4th opening
Greater than the width of third opening；
Step 5: forming sacrificial oxide layer and removing, the sacrificial oxide layer is conductive by described first to the flute surfaces
Type epitaxial layer carries out oxidation formation, and the second opening for removing the top of the groove after the sacrificial oxide layer can expand, and walks
The opening of third described in rapid three is used to offset the expansion value of second opening relative to the expansion value of first opening, makes institute
The width of second opening after stating third opening and expanding tends to be equal；
Step 6: be epitaxially-formed the second conductive type epitaxial layer, second conductive type epitaxial layer is by the ditch
Slot is filled up completely, and the width of second opening after being open and expand using the third tends to equal structure and improves extension
The quality of growth；It is led by filling described first between second conductive type epitaxial layer and the groove in the groove
Electric type epitaxial layer is alternately arranged composition super junction.
2. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: the semiconductor substrate is silicon lining
Bottom, first conductive type epitaxial layer are the first conduction type silicon epitaxy layer, and second conductive type epitaxial layer is second
Conduction type silicon epitaxy layer.
3. the manufacturing method of groove-shaped super junction as claimed in claim 2, it is characterised in that: first oxide layer and described
The material of third oxide layer is all silica；The material of second nitration case is silicon nitride.
4. the manufacturing method of groove-shaped super junction as claimed in claim 3, it is characterised in that: first oxide layer is hot oxygen
Change layer, with a thickness of 100 Ethylmercurichlorendimides~2000 Ethylmercurichlorendimides；Second nitration case with a thickness of 100 Ethylmercurichlorendimides~1500 Ethylmercurichlorendimides；The third
Oxide layer with a thickness of 0.5 micron~3 microns.
5. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: in step 3, second nitrogen
The size for changing the lateral etching of layer is 0.1 micron, and the width of the third opening bigger than the width of first opening 0.2 is micro-
Rice.
6. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: the width of the groove and described
The ratio of spacing between groove is 1:1.5.
7. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: the first conduction type is N-type, the
Two conduction types are p-type；Alternatively, the first conduction type is p-type, the second conduction type is N-type.
8. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: the semiconductor substrate is N-type
Heavy doping.
9. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: the bottom of the groove is located at institute
It states in the first conductive type epitaxial layer.
10. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: carved in step 3 using wet process
Etching technique laterally return to second nitration case and be carved.
11. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: carved in step 4 using wet process
Etching technique removes the third oxide layer.
12. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: thermal oxidation technology in step 5
Form the sacrificial oxide layer.
13. the manufacturing method of groove-shaped super junction as claimed in claim 12, it is characterised in that: carved in step 5 using wet process
Etching technique removes the sacrificial oxide layer.
14. the manufacturing method of groove-shaped super junction as described in claim 1, it is characterised in that: removed in step 5 described sacrificial
After domestic animal oxide layer and before the step 6 progress epitaxial growth, further include the steps that carrying out pre-treatment to the groove.
15. the manufacturing method of groove-shaped super junction as claimed in claim 14, it is characterised in that: place before being carried out to the groove
The step of reason includes:
Carry out H2Baking；
Carry out HCl etching.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113555227A (en) * | 2021-07-19 | 2021-10-26 | 上海集成电路制造创新中心有限公司 | On-chip all-solid-state super capacitor and preparation method thereof |
| CN114068687A (en) * | 2021-11-26 | 2022-02-18 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
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| US20100197088A1 (en) * | 2009-02-05 | 2010-08-05 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN107946175A (en) * | 2017-11-06 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
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2018
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100197088A1 (en) * | 2009-02-05 | 2010-08-05 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN107946175A (en) * | 2017-11-06 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | The fill method of groove extension |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113555227A (en) * | 2021-07-19 | 2021-10-26 | 上海集成电路制造创新中心有限公司 | On-chip all-solid-state super capacitor and preparation method thereof |
| CN114068687A (en) * | 2021-11-26 | 2022-02-18 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
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| CN109148560B (en) | 2021-08-24 |
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