CN107611080A - The extension fill method of groove - Google Patents
The extension fill method of groove Download PDFInfo
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- CN107611080A CN107611080A CN201710734116.1A CN201710734116A CN107611080A CN 107611080 A CN107611080 A CN 107611080A CN 201710734116 A CN201710734116 A CN 201710734116A CN 107611080 A CN107611080 A CN 107611080A
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- groove
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Abstract
The invention discloses a kind of extension fill method of groove, comprise the following steps：Step 1: form groove；Step 2: carry out first time epitaxial growth technology and control the process time to form a unclosed slit between making the epitaxial layer to be formed in the trench；Step 3: being passed through HCL carries out epitaxial layer etching, HCL can be flowed into slit and the epitaxial layer of slit both sides and bottom is performed etching, and the fewer etch rate of amount flowed into the depth increase HCL of slit is slower and the width of the slit after etching is become big and is in the structure that reduces with the increase of depth formed with the width filled beneficial to extension；Step 4: carry out second of epitaxial growth technology carries out extension filling to slit；Width using slit is in that the structure that reduces with the increase of depth makes process gas in the second epitaxial growth technology smoothly reach the bottom of slit to fill without cavity so as to realize.The present invention can realize to fill without cavity, can prevent component failure caused by cavity and improve product yield.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, is filled more particularly to a kind of extension of groove
Method.
Background technology
Super junction is the p-type thin layer being alternately arranged and N-type thin layer composition being formed from semiconductor crystal wafer (wafer),
The manufacture method of existing super junction would generally use trench fill process method, and channel filling method is needed first in semiconductor die
The groove of certain depth and width is etched on the epitaxial layer such as n-type doping epitaxial layer of circle such as silicon wafer surface, then utilizes extension
The mode of filling (EPI Filling) fills the silicon epitaxy of p-type doping on the groove carved, and requires that filling region has
Intact crystal structure, so that follow-up process makes high performance device.
With the development of technique, in super junction project, three generations's technique is on the basis of two foundry skills, deep trench size,
Depth and pattern have a certain degree of optimization, therefore device performance gets a promotion.But then, new groove pattern is very big
EPI filling difficulty is added in degree.Because the depth-to-width ratio of the groove of super junction is larger and depth is deeper, therefore super junction
Groove typically directly be referred to as deep trench.
In extension filling process, process gas touches side wall and the bottom of groove, can be grown simultaneously in three directions
Monocrystalline silicon.Both sidewalls are drawn close to centre, after reaching to a certain degree, can form elongated slit；Because groove is deeper, two surface sides
The single-crystal Si epitaxial layers grown on wall can grow to trench interiors simultaneously, therefore the slit formed has elongated structure, namely narrow
Narrower in width, the depth of seam are very deep.Slit is narrower, process gas gap bottom reaction more difficult to get access so that gap bottom grown
It is slower and slower.Final the top of the groove covers with sealing, causes process gas to cannot be introduced into slit reaction.I.e. after end-of-fill in groove
There can be unfilled cavity.The cavity can directly result in component failure.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of extension fill method of groove, can realize and be filled out without cavity
Fill.
In order to solve the above technical problems, the extension fill method of groove provided by the invention comprises the following steps：
Step 1: semiconductor wafer is provided and forms groove in the semiconductor wafer surface.
Step 2: carry out first time epitaxial growth technology, first epitaxial growth technology in the bottom of the groove and
Two side while grown epitaxial layer, control the first time epitaxial growth process time to make the first time epitaxial growth technology shape
Into epitaxial layer in the trench between formed a unclosed slit.
Step 3: stopping the first time epitaxial growth technology and being passed through HCL progress epitaxial layer etchings, the epitaxial layer is carved
HCL can be flowed into the slit and the epitaxial layer of the slit both sides and bottom be performed etching, the knot of the slit in erosion
Structure cause more toward the slit bottom HCL reach amount it is fewer, make the epitaxial layer etch rate with the depth of the slit
The increase of degree and slow down and make the epitaxial layer etch after the width of the slit to become the width of big and described slit be in depth
The increase of degree and the structure reduced.
Step 4: carrying out second of epitaxial growth technology carries out extension filling to the slit so as to which the groove is complete
Filling, the width using the slit are in that the structure reduced with the increase of depth makes technique in second epitaxial growth technology
Filled so as to realize without cavity the bottom that gas smoothly reaches the slit.
Further improve is that the groove is super junction groove, is formed in step 1 in the semiconductor wafer surface
There is the first conductive type epitaxial layer and the groove includes multiple and is formed at the first conductive type epitaxial layer surface simultaneously
In.
The epitaxial layer that step 2 and step 4 are filled in the trench is all second with the doping of the second conduction type
Conductive type epitaxial layer；Second conductivity type columns are formed by second conductive type epitaxial layer being filled in the groove,
First conductivity type columns are formed by first conductive type epitaxial layer between each groove, by first conduction type
Post and second conductivity type columns are alternately arranged to form the super junction.
Further improve is that the semiconductor crystal wafer is Silicon Wafer, and first conductive type epitaxial layer is silicon epitaxy
Layer, second conductive type epitaxial layer is silicon epitaxy layer.
Further improve is included as follows step by step when the groove is formed in step 1：In first conductive-type
Type epi-layer surface forms hard mask layers, the forming region of the groove of super junction is gone out using lithographic definition, successively to the ditch
The hard mask layers of the forming region of groove and first conductive type epitaxial layer perform etching to form multiple grooves.
Further improve is that the hard mask layers are silicon nitride layer；Or the hard mask layers be silica and
The superimposed layer of silicon nitride.
Further improve is that the width for each groove that the photoetching process in step 1 defines is identical, each ditch
Spacing between groove is identical.
Further improve is also to include removing described the second of the surface of the hard mask layers successively after step 4
The step of conductive type epitaxial layer and the hard mask layers.
Further improve is that the first conduction type is N-type, and the second conduction type is p-type；Or first conduction type
For p-type, the second conduction type is N-type.
Further improve is the technique bar of the first time epitaxial growth technology and second of epitaxial growth technology
Part is identical and process gas all includes hydrogen and silicon source gas.
Further improve is that the silicon source gas is dichloro hydrogen silicon.
The extension filling process of groove is split up into two steps and is filled up completely with by epitaxial growth technology twice by the present invention
Groove, inserted between epitaxial growth technology twice be once passed through HCL carry out epitaxial layer etching technique, be passed through HCL when
Machine selection be first time epitaxial growth technology in the trench between formed a unclosed slit when be passed through, slit is due to groove
Formed during the epitaxial layer ingrowing of both sides, if continuing epitaxial growth, then process gas is unable to reach slit
Bottom or reach Slot bottom process gas amount be less than slit at the top of amount so that the speed of the bottom epitaxial growth of slit
It is slowed or stopped；Architectural feature that is of the invention then make use of slit is passed through HCL after slit is formed and carries out epitaxial layer etching, this
Sample, slit can equally have an impact to the flow of HCL gases, namely more fewer toward the amount of the bottom HCL arrival of the slit, but
It is the influence contrast of etching technics and epitaxial growth technology to epitaxial thickness, the changes in flow rate of etching gas can make epitaxial layer
Etch rate slow down with the increase of the depth of slit and make epitaxial layer etch after the width of slit become big and slit width
Degree is in the structure reduced with the increase of depth.So after being performed etching by HCL gases to epitaxial layer so that after etching
The width of slit be just rendered as being advantageous to the structure that process gas is flowed into Slot bottom, finally cause the second epitaxial growth
Process gas can smoothly reach the bottom of slit and be filled so as to realize without cavity in technique.So the present invention can be realized and filled out without cavity
Fill, component failure caused by cavity can be prevented and improve the yield of product.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Figure 1B is the existing device architecture schematic diagram in fluted each step of extension fill method；
Fig. 2 is the flow chart of present invention method；
Fig. 3 A- Fig. 3 C are the device architecture schematic diagrames in each step of extension fill method of groove of the embodiment of the present invention.
Embodiment
Problem possessed by existing method is introduced first, and present invention method is exactly to be directed to these technical problems
Specific improvement has been done, has been that the device architecture now in fluted each step of extension fill method shows as shown in Figure 1A to Figure 1B
It is intended to；Illustrated exemplified by using groove as the groove of super junction, existing method comprises the following steps：
Step 1: as shown in Figure 1A, there is provided semiconductor wafer 101, on the surface of semiconductor crystal wafer 101 formed with
One conductive type epitaxial layer 102.Hard mask layers 201 are formed on the surface of the first conductive type epitaxial layer 102, using photoetching
The forming region of the groove of super junction is defined, successively the hard mask layers 201 to the forming region of the groove and institute
The first conductive type epitaxial layer 102 is stated to perform etching to form multiple grooves 202.
Step 3: as shown in Figure 1A, carry out epitaxial growth and fill the second conductive type epitaxial layer in each groove 202
103.The second conductive type epitaxial layer 103 is from the lower surface of groove 202 and two sidewall surfaces during epitaxial growth
Grow simultaneously, the epitaxial layer in two sidewall surfaces be all to groove 202 growth inside and in the ideal situation can be in ditch
The middle section of groove 202 merges, and Figure 1A schematic diagram is the schematic diagram in epitaxial process, two in the structure shown in Figure 1A
Epitaxial layer in sidewall surfaces is not in contact also in the middle section of groove 202, is at this moment formed in the middle section of groove 202
One elongated slit 203.
As shown in Figure 1B, it is schematic diagram after epitaxial growth is continued after forming slit 203, due to the shape of slit 203
Cheng Hou, the narrower width of slit 203, and the process gas of epitaxial growth is flowed into from the front of semiconductor crystal wafer 101, in slit
Process gas can be passed through from the top of slit 203 and flow into portion on earth in 203, but because the width of slit 203 is narrow, it is more past
The bottom of slit 203, the amount that process gas flows into is fewer or even process gas is unable to reach, and last result is slit 203
The epitaxial growth rate of top area be more than bottom section epitaxial growth rate, namely with slit 203 position increasingly
Deep, epitaxial growth rate is less and less, sealing will certainly be so produced at the top of slit 203, sealing will be in ditch after being formed
Cavity 204 is formed in groove 202.The presence in cavity 204 can influence the reliability of super-junction device, or even can directly result in super junction
Component failure, influence the yield of product.
As shown in Fig. 2 it is the flow chart of present invention method；It is the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 C
Device architecture schematic diagram in each step of extension fill method of groove, it is the groove of super junction to illustrate using groove,
The extension fill method of groove of the embodiment of the present invention comprises the following steps：
Step 1: as shown in Figure 3A, there is provided semiconductor wafer 1 simultaneously forms groove on the surface of semiconductor crystal wafer 1
302.In present invention method, on the surface of semiconductor crystal wafer 1 formed with the first conductive type epitaxial layer 2 and the ditch
Groove 302 includes multiple and is formed at simultaneously in the surface of the first conductive type epitaxial layer 2.
Preferably, the semiconductor crystal wafer 1 is Silicon Wafer, and first conductive type epitaxial layer 2 is silicon epitaxy layer, described
Second conductive type epitaxial layer 3 is silicon epitaxy layer.
Include as follows step by step when forming the groove 302：Hard is formed on the surface of the first conductive type epitaxial layer 2
Mask layer 301, the forming region of the groove 302 of super junction is gone out using lithographic definition, successively to the forming region of the groove 302
The hard mask layers 301 and first conductive type epitaxial layer 2 perform etching to form multiple grooves 302.
The hard mask layers 301 are silicon nitride layer；Or the hard mask layers 301 are silica and silicon nitride
Superimposed layer.The width for each groove 302 that photoetching process defines is identical, and the spacing between each groove 302 is identical.
Step 2: as shown in Figure 3A, first time epitaxial growth technology is carried out, first epitaxial growth technology is in the ditch
The bottom and two side of groove 302 while grown epitaxial layer 3a, control the first time epitaxial growth process time to make described first
The epitaxial layer 3a that secondary epitaxial growth technology is formed forms a unclosed slit 303 among the groove 302.In Fig. 3 A individually
The epitaxial layer of the first time epitaxial growth technology formation is represented with mark 3a.The slit 303 represents epitaxial layer 3a from described
Do not merge the gap structure of formation after the two side ingrowing of groove 302 also, the size of the slit 303 at the top of guarantee not
It is controlled as needed under conditions of closing.In the embodiment of the present invention, before the formation of slit 303, namely the groove 302
When spacing between the epitaxial layer 3a of two side is larger, process gas can smoothly be flowed into the bottom of unfilled groove 302,
At this moment the epitaxial growth rate of two side in the position of the top-to-bottom of the groove 302 can be consistent；Work as institute
State spacing between the epitaxial layer 3a of the two side of groove 302 it is smaller when so that process gas is flowed into unfilled groove 302
Bottom quantitative change it is few so that from the epitaxial growth of the two side of the position of the top-to-bottom of the groove 302 speed
Rate gradually reduces, and is at this moment considered as the slit 303 formd.
Step 3: as shown in Figure 3 B, stop the first time epitaxial growth technology and be passed through HCL to carry out epitaxial layer etching,
HCL can be flowed into the slit 303 and the epitaxial layer of the both sides of slit 303 and bottom is carried out in the epitaxial layer etching
Etching, the structure of the slit 303 make it that the amount that is more reached toward the bottom HCL of the slit 303 is fewer, carves the epitaxial layer
Erosion speed slow down with the increase of the depth of the slit 303 and make the epitaxial layer etch after the slit 303 width
The width that degree becomes big and described slit 303 is in the structure reduced with the increase of depth.Still represented in Fig. 3 B using mark 303
The slit become large-sized after epitaxial layer etching.
Step 4: as shown in Figure 3 C, carry out second of epitaxial growth technology the slit 303 is carried out extension filling so as to
The groove 302 is filled up completely with, the width using the slit 303 is in that the structure that reduces with the increase of depth makes described the
Process gas smoothly reaches the bottom of the slit 303 and filled so as to realize without cavity in two epitaxial growth technologies.In Fig. 3 C, use
Formed after second of epitaxial growth technology of first time epitaxial growth technology and step 4 of the sign of mark 3 Jing Guo step 2
Epitaxial layer.
The first time epitaxial growth technology is identical with the process conditions of second of epitaxial growth technology and process gas
Body all includes hydrogen and silicon source gas.Preferably, the silicon source gas is dichloro hydrogen silicon.
In present invention method, epitaxial layer 3 that step 2 and step 4 are filled in the groove 302 be all with
Second conductive type epitaxial layer 3 of the second conduction type doping；By second conduction type being filled in the groove 302
Epitaxial layer 3 forms the second conductivity type columns, and the is formed by first conductive type epitaxial layer 2 between each groove 302
One conductivity type columns, it is alternately arranged by first conductivity type columns and second conductivity type columns and is formed the super junction.
Afterwards also include remove successively the hard mask layers 301 surface second conductive type epitaxial layer 3 with
And the step of hard mask layers 301.
In the embodiment of the present invention, the first conduction type is N-type, and the second conduction type is p-type, the super junction device at this moment manufactured
Part is usually N-type device.Also can be in other embodiments：First conduction type is p-type, and the second conduction type is N-type, at this moment
The super-junction device of manufacture is usually P-type device.
Further improve is the technique bar of the first time epitaxial growth technology and second of epitaxial growth technology
Part is identical and process gas all includes hydrogen and silicon source gas.
Further improve is that the silicon source gas is dichloro hydrogen silicon.
The embodiment of the present invention by the extension filling process of groove 302 be split up into two steps i.e. by epitaxial growth technology twice come
Groove 302 is filled up completely with, is inserted between epitaxial growth technology twice and is once passed through the technique that HCL carries out epitaxial layer etching,
The timing for being passed through HCL is led to when being and forming a unclosed slit 303 in first time epitaxial growth technology among groove 302
Enter, slit 303 is formed when being due to the epitaxial layer ingrowing of the both sides of groove 302, if continuing epitaxial growth, then
Process gas is unable to reach the bottom of slit 303 or reaches the amount of the process gas of the bottom of slit 303 less than the top of slit 303
Amount so that the speed of the bottom epitaxial growth of slit 303 is slowed or stopped, and the epitaxial growth rate at the top of slit 303 compared with
It hurry up, the top seal of slit 303 can be formed cavity by the epitaxial layer at the last top of slit 303；It is of the invention then make use of narrow
The architectural feature of seam 303 is passed through HCL after the formation of slit 303 and carries out epitaxial layer etching, and so, slit 303 equally can be to HCL gas
The flow of body has an impact, namely more fewer toward the amount of the bottom HCL arrival of the slit 303, but etching technics and extension
Influence contrast of the growth technique to epitaxial thickness, the changes in flow rate of etching gas can make epitaxial layer 3a etch rates with narrow
The increase of the depth of seam 303 and slow down and make epitaxial layer 3a etch after the width of slit 303 become big and slit 303 width and be in
The structure reduced with the increase of depth.So after being performed etching by HCL gases to epitaxial layer 3a so that after etching
The width of slit 303 is just rendered as being advantageous to the structure that process gas is flowed into the bottom of slit 303, finally causes the second extension
Process gas can smoothly reach the bottom of slit 303 and be filled so as to realize without cavity in growth technique.So embodiment of the present invention
It can realize and be filled without cavity, component failure caused by cavity can be prevented and improve the yield of product.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (10)
1. the extension fill method of a kind of groove, it is characterised in that comprise the following steps：
Step 1: semiconductor wafer is provided and forms groove in the semiconductor wafer surface；
Step 2: carrying out first time epitaxial growth technology, first epitaxial growth technology is in the bottom of the groove and both sides
Wall while grown epitaxial layer, the first time epitaxial growth process time is controlled to make what the first time epitaxial growth technology was formed
Epitaxial layer in the trench between formed a unclosed slit；
Step 3: stop the first time epitaxial growth technology and be passed through HCL progress epitaxial layer etchings, in the epitaxial layer etching
HCL can be flowed into the slit and the epitaxial layer of the slit both sides and bottom is performed etching, and the structure of the slit makes
Must be more fewer toward the amount of the bottom HCL arrival of the slit, make the epitaxial layer etch rate with the depth of the slit
Increase and slow down and make the epitaxial layer etch after the width of the slit to become the width of big and described slit be in depth
The structure for increasing and reducing；
Step 4: carrying out second of epitaxial growth technology carries out extension filling to the slit so as to which the groove be filled out completely
Fill, the width using the slit is in that the structure reduced with the increase of depth makes process gas in second epitaxial growth technology
Filled so as to realize without cavity the bottom that body smoothly reaches the slit.
2. the extension fill method of groove as claimed in claim 1, it is characterised in that：The groove is super junction groove, step
Include multiple and shape simultaneously formed with the first conductive type epitaxial layer and the groove in the semiconductor wafer surface in rapid one
In first conductive type epitaxial layer surface described in Cheng Yu；
The epitaxial layer that step 2 and step 4 are filled in the trench is all second with the doping of the second conduction type conductive
Type epitaxial layer；Second conductivity type columns are formed by second conductive type epitaxial layer being filled in the groove, by each
First conductive type epitaxial layer between the groove forms the first conductivity type columns, by first conductivity type columns and
Second conductivity type columns are alternately arranged to form the super junction.
3. the extension fill method of groove as claimed in claim 2, it is characterised in that：The semiconductor crystal wafer is Silicon Wafer,
First conductive type epitaxial layer is silicon epitaxy layer, and second conductive type epitaxial layer is silicon epitaxy layer.
4. the extension fill method of groove as claimed in claim 2 or claim 3, it is characterised in that：The groove is formed in step 1
When include it is following step by step：Hard mask layers are formed on the first conductive type epitaxial layer surface, using lithographic definition excess of export
The forming region of the groove of level knot, the successively hard mask layers to the forming region of the groove and first conductive-type
Type epitaxial layer performs etching to form multiple grooves.
5. the extension fill method of groove as claimed in claim 4, it is characterised in that：The hard mask layers are silicon nitride
Layer；Or the superimposed layer that the hard mask layers are silica and silicon nitride.
6. the extension fill method of groove as claimed in claim 2 or claim 3, it is characterised in that：Photoetching process in step 1 is determined
The width of each groove of justice is identical, and the spacing between each groove is identical.
7. the extension fill method of groove as claimed in claim 4, it is characterised in that：Also include removing successively after step 4
The step of second conductive type epitaxial layer on the surface of the hard mask layers and the hard mask layers.
8. the extension fill method of groove as claimed in claim 2 or claim 3, it is characterised in that：First conduction type is N-type, the
Two conduction types are p-type；Or first conduction type be p-type, the second conduction type is N-type.
9. the extension fill method of groove as claimed in claim 1, it is characterised in that：The first time epitaxial growth technology and
The process conditions of second of epitaxial growth technology are identical and process gas all includes hydrogen and silicon source gas.
10. the extension fill method of groove as claimed in claim 9, it is characterised in that：The silicon source gas is dichloro hydrogen silicon.
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|---|---|---|---|
| CN201710734116.1A CN107611080A (en) | 2017-08-24 | 2017-08-24 | The extension fill method of groove |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710734116.1A CN107611080A (en) | 2017-08-24 | 2017-08-24 | The extension fill method of groove |
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| CN107611080A true CN107611080A (en) | 2018-01-19 |
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| CN201710734116.1A Pending CN107611080A (en) | 2017-08-24 | 2017-08-24 | The extension fill method of groove |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108376670A (en) * | 2018-02-05 | 2018-08-07 | 上海华虹宏力半导体制造有限公司 | Deep trench extension fill method |
| CN113224093A (en) * | 2021-04-09 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Silicon epitaxial filling method for holes |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184883A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for filling deep trench having superstructure |
| CN103855002A (en) * | 2012-11-28 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Super junction depth groove filling process |
| CN105895533A (en) * | 2016-06-28 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Super junction structure manufacture method |
-
2017
- 2017-08-24 CN CN201710734116.1A patent/CN107611080A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184883A (en) * | 2011-04-08 | 2011-09-14 | 上海先进半导体制造股份有限公司 | Method for filling deep trench having superstructure |
| CN103855002A (en) * | 2012-11-28 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Super junction depth groove filling process |
| CN105895533A (en) * | 2016-06-28 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Super junction structure manufacture method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108376670A (en) * | 2018-02-05 | 2018-08-07 | 上海华虹宏力半导体制造有限公司 | Deep trench extension fill method |
| CN113224093A (en) * | 2021-04-09 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Silicon epitaxial filling method for holes |
| CN113224093B (en) * | 2021-04-09 | 2022-08-16 | 华虹半导体(无锡)有限公司 | Silicon epitaxial filling method for holes |
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