CN102386056A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102386056A CN102386056A CN2010102686351A CN201010268635A CN102386056A CN 102386056 A CN102386056 A CN 102386056A CN 2010102686351 A CN2010102686351 A CN 2010102686351A CN 201010268635 A CN201010268635 A CN 201010268635A CN 102386056 A CN102386056 A CN 102386056A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, and the method comprises the following steps: providing a substrate; forming a contrapuntal cursor doped area in the substrate; covering an oxide layer on the substrate with the contrapuntal cursor doped area, wherein the oxide layer in the contrapuntal cursor doped area is a contrapuntal cursor, the contrapuntal cursor doped area on the substrate is a first area, and the part beyond the contrapuntal cursor doped area is a second area; removing the oxide layer of the second area to expose out of the surface of the substrate; and taking the oxide layer of the first area as a mask, and forming an epitaxial layer on the surface of the substrate. Through the method provided by the invention, the problem that the contrapuntal cursor is in planarization by the epitaxial layer after epitaxial growth can be solved; and the method of the invention omits the aero-layer photoetching and etching, so that the capacity of the device is saved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of semiconductor device and manufacturing approach thereof.
Background technology
In field of manufacturing semiconductor devices, BCD (Bipolar, CMOS, DMOS) technology enjoys domestic and international industry to pay close attention to, and has the stronger market competitiveness.BCD technology is a kind of monolithic integrated technique technology, is taken the lead in succeeding in developing by company of STMicw Electronics (ST), and this technology can be made bipolar tube bipolar, CMOS and DMOS device on same chip, therefore is called for short BCD technology.BCD technology is mainly used in IC such as electrical lighting, automotive electronics, display driver, Industry Control and makes the field, has vast market prospect.
The BCD technological process is mainly: at first go up at substrate (silicon chip) and form buried regions, carry out epitaxial growth then, then in the epitaxial loayer of silicon chip, form bipolar device, MOS device, make metal connecting line etc. at last.Wherein, in forming the process of buried regions, inject and anneal oxidation forms the contraposition vernier, in follow-up photoetching process, carry out operations such as contraposition, exposure according to contraposition vernier and other regional graphics different through buried regions photoetching, buried regions.
But generally between 0.5 micron to 4 microns, so thick epitaxial loayer will cause the contraposition vernier to be flattened to the epitaxy layer thickness that grows out.In follow-up photoetching process,, cause the quality that to judge the photolithographic exposure contraposition according to the contrast difference of figure under light microscope like this, therefore, can't accurately read the contraposition vernier because the step of contraposition vernier shoals or disappears.
Referring to Fig. 1 a to Fig. 1 e; The problem that shoals or disappear to the step of contraposition vernier after the epitaxial growth; Before BCD technology contraposition vernier 3 formed, (Fig. 1 a), dry etching went out deep groove 2 then at first on substrate 1, to carry out once zero layer photoetching; Carry out buried regions photoetching (Fig. 1 b), buried regions injection and anneal oxidation (Fig. 1 c), extension cleaning (Fig. 1 d) and epitaxial growth (Fig. 1 e) below successively; Like this in follow-up photoetching process, under light microscope, just can see the step clearly 4 that forms owing to zero layer photoetching and etching, this step 4 can be used as equally and reads the contraposition vernier.
Yet zero layer photoetching and etching can have very big influence to the pattern of epitaxial loayer, even cause the serious distortion of epitaxial loayer pattern, and then influence reading of contraposition vernier; And the groove that forms after zero layer photoetching and the etching is deep, generally greater than 0.5 micron, adopts dry method to carry out etching, will waste equipment capacity.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of semiconductor device and manufacturing approach thereof, solving after the epitaxial growth epitaxial loayer, and then accurately read the contraposition vernier, and can save equipment capacity the problem of contraposition vernier planarization.
For realizing above-mentioned purpose, the present invention provides following technical scheme:
A kind of method, semi-conductor device manufacturing method comprises:
Substrate is provided;
In said substrate, form contraposition vernier doped region;
Capping oxidation layer on substrate with contraposition vernier doped region, the contraposition vernier doped region on the said substrate partly is the first area, the part outside the contraposition vernier doped region is a second area;
Remove the oxide layer of second area and expose substrate surface;
Oxide layer with the first area is a mask, forms epitaxial loayer at substrate surface.
Preferably, in said substrate, forming contraposition vernier doped region specifically comprises:
Form the photoresist layer of patterning at said substrate surface;
Photoresist layer with said patterning is mask implanted dopant in substrate, forms contraposition vernier doped region.
Preferably, the capping oxidation layer specifically comprises on the substrate with contraposition vernier doped region:
Remove the photoresist layer of substrate surface patterning;
Substrate is carried out anneal oxidation, form oxide layer.
Preferably, on substrate, after the capping oxidation layer, also comprise: have cvd nitride layer on the substrate of oxide layer with contraposition vernier doped region.
Preferably, said first area thickness of oxide layer is greater than second area.
Preferably, remove the oxide layer of second area and expose substrate surface and specifically comprise:
On the oxide layer of first area, form protective layer;
Remove the oxide layer of second area, and clean the protective layer of first area.
Preferably, said protective layer is a photoresist layer.
The present invention also provides a kind of semiconductor device, comprising: substrate; Contraposition vernier in the said substrate; Epitaxial loayer on the substrate outside the said contraposition vernier.
Preferably, the forming process of the contraposition vernier in the said substrate is:
In said substrate, form contraposition vernier doped region;
Capping oxidation layer on the substrate with contraposition vernier doped region, the oxide layer of said contraposition vernier doped region is the contraposition vernier.
Preferably, the forming process of the epitaxial loayer on the substrate outside the said contraposition vernier is:
Form protective layer on the contraposition vernier in substrate;
Remove the oxide layer on the substrate outside the contraposition vernier, and clean the protective layer on the contraposition vernier;
With said contraposition vernier is mask, forms epitaxial loayer at substrate surface.
This shows; Semiconductor device provided by the present invention and manufacturing approach thereof at first form contraposition vernier doped region, capping oxidation layer on substrate then in substrate; The oxide layer of said contraposition vernier doped region is the contraposition vernier; Removing the oxide layer on the substrate outside the contraposition vernier doped region and expose substrate surface, is that mask forms epitaxial loayer at substrate surface with the contraposition vernier then, owing to do not have grown epitaxial layer on the contraposition vernier; So the epitaxial loayer on the substrate outside the contraposition vernier can be with the planarization of contraposition vernier, make and follow-uply can accurately read the contraposition vernier; And method provided by the present invention has been cancelled zero layer photoetching and etching, thereby has saved equipment capacity.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention; To do simple introduction to the accompanying drawing of required use among the embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 a to Fig. 1 e is the sketch map of method, semi-conductor device manufacturing method in the prior art;
Fig. 2 is the flow chart of a kind of method, semi-conductor device manufacturing method that the embodiment of the invention provided;
Fig. 3 a to Fig. 3 e is the sketch map of the method, semi-conductor device manufacturing method that the embodiment of the invention provided.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention; But the present invention can also adopt other to be different from alternate manner described here and implement; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
Secondly, the present invention combines sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is example, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Said as the background technology part; Contraposition vernier step can shoal or disappear after traditional epitaxial growth; The inventor discovers, epitaxial loayer can be on the contraposition vernier and the growth of the substrate surface beyond the contraposition vernier when its essential reason was epitaxial growth, like this; When epitaxial loayer was enough thick, the step of contraposition vernier will shoal or disappear; Though and zero layer photoetching and etching can form darker groove; And then after epitaxial growth, can see step clearly; But zero layer photoetching can cause the distortion of epitaxial loayer pattern with etching, thereby influences reading of follow-up contraposition vernier, and zero layer photoetching and etching can be wasted equipment capacity.
Based on this, the present invention provides a kind of method, semi-conductor device manufacturing method, comprising: substrate is provided; In said substrate, form contraposition vernier doped region; Capping oxidation layer on substrate with contraposition vernier doped region, the contraposition vernier doped region on the said substrate partly is the first area, the part outside the contraposition vernier doped region is a second area; Remove the oxide layer of second area and expose substrate surface; Oxide layer with the first area is a mask, forms epitaxial loayer at substrate surface.
Specify the embodiment of said method, semi-conductor device manufacturing method below in conjunction with accompanying drawing.
Referring to Fig. 2, said method specifically may further comprise the steps:
Step 1: substrate is provided.
The substrate that is provided in the present embodiment is a monocrystalline silicon, and said substrate can also be other semi-conducting materials such as germanium, indium phosphide or GaAs.
Step 2: in said substrate, form contraposition vernier doped region.
Contraposition vernier doped region generally is the method for injecting through diffusion or ion; The heavily doped region that on substrate, forms in level or the vertical scribe line; Behind subsequently epitaxial growing, hope can reappear substrate surface on epitaxial loayer characteristic comprises contraposition vernier doped region.
In said substrate, form contraposition vernier doped region and specifically comprise following two steps:
Step 21: the photoresist layer that forms patterning at said substrate surface.
Referring to Fig. 3 a, the vernier of contraposition described in present embodiment doped region forms in buried regions technology, so at first carry out the buried regions photoetching on substrate 1 surface, promptly at substrate 1 surperficial spin coating photoresist layer, makes public then, develops, and forms the photoresist layer 5 with patterning.The pattern that has contraposition vernier doped region 6 and buried regions district (not shown) on this photoresist layer 5.
Step 22: the photoresist layer with said patterning is mask implanted dopant in substrate, forms contraposition vernier doped region.
Step 3: capping oxidation layer on substrate with contraposition vernier doped region, the contraposition vernier doped region on the said substrate partly is the first area, the part outside the contraposition vernier doped region is a second area.
At first; Remove the photoresist layer 5 of substrate surface patterning, expose the contraposition vernier doped region 6 on substrate 1 surface and the substrate 1, here; Contraposition vernier doped region 6 parts on the definition substrate are the first area, and the part outside the contraposition vernier doped region is a second area.
Then, capping oxidation layer on substrate 1 with contraposition vernier doped region 6, this step has formed oxide layer through annealing, injection oxygen on substrate.The destruction of when annealing mainly is used for recovering implanted dopant lattice being caused, and activate the atom that injects.
Referring to Fig. 3 b, adopt thermal oxidation technology on substrate, to form oxide layer in this step with contraposition vernier doped region, said oxide layer comprises the oxide layer 7 of second area and the oxide layer 3 of first area.Because the oxide layer 3 of first area forms at contraposition vernier doped region; And contraposition vernier doped region is the zone behind the implanted dopant antimony Sb; So the speed of growth oxide layer is fast in the contraposition vernier doped region, therefore, the thickness of first area oxide layer 3 is greater than the thickness of second area oxide layer 7.Oxide layer described in the present embodiment is a silicon dioxide.The oxide layer 3 of said first area is contraposition vernier 3.
Preferably, can also come the cvd nitride layer through the method for chemical vapour deposition (CVD) or physical vapour deposition (PVD) having on the substrate of oxide layer in this step, nitration case described in the present embodiment is a silicon nitride.Deposited silicon nitride former because: since the semiconductor device that has in manufacture process because of its characteristic requirements; When annealing, need feed less oxygen; Cause the oxidated layer thickness of generation to have only
(general oxidated layer thickness may wash said oxide layer when making protective layer (photoresist) on follow-up cleaning oxide layer for
; Thereby influence subsequent operation; So when the oxide layer of anneal oxidation formation approaches, need on oxide layer, deposit one deck silicon nitride through the method for vapour deposition.
Step 4: remove the oxide layer of second area and expose substrate surface.
This step is the crucial part of method provided by the present invention; Compare the oxide layer step of removing in the traditional handicraft on the substrate; The present invention only removes the oxide layer 7 of second area and exposes the substrate surface of second area in this step; Keep the oxide layer 3 of first area,, specifically comprise following two steps referring to Fig. 3 c and 3d:
Step 41: on the oxide layer of said first area, form protective layer.
For the oxide layer 3 that keeps the first area, need on the oxide layer 3 of said first area, form protective layer 8.Protective layer described in the present embodiment 8 is a photoresist layer; The concrete forming process of said photoresist layer 8 is: spin coating photoresist layer on the substrate with oxide layer 1; Exposure, development, the photoresist layer of removal second area promptly forms photoresist layer 8 on the oxide layer 3 of first area.Said protective layer 8 can also be hard mask.
Correspondingly, if deposited nitration case having on the substrate of oxide layer, then this step changes into: on the nitration case of said first area, form protective layer.
Step 42: remove the oxide layer of second area, and clean the protective layer of first area.
Correspondingly, if deposited nitration case having on the substrate of oxide layer, then this step changes into: remove the nitration case and the oxide layer of second area, and clean the protective layer of first area.
Step 5: the oxide layer with said first area is a mask, forms epitaxial loayer at substrate surface.
The oxide layer 3 of said first area is the oxide layer to forming behind substrate 1 anneal oxidation.Referring to Fig. 3 e, be mask with the oxide layer 3 of said first area, form epitaxial loayer 9 on substrate 1 surface, promptly carry out selective epitaxial growth on substrate 1 surface.9 substrate surfaces at second area of said epitaxial loayer are grown; There is not grown epitaxial layer on the oxide layer 3 of first area; Like this, after epitaxial loayer 9 forms, between the epitaxial loayer 9 of second area and the oxide layer 3 of first area a very high step is arranged; This step appearance can clearly be recognized at microscopically, thereby can be read the contraposition vernier according to said step appearance; And owing to do not have grown epitaxial layer on the oxide layer 3 of first area, and then fault and map migration have been eliminated to reading the influence of contraposition vernier.
Correspondingly, if deposited nitration case having on the substrate of oxide layer, then this step changes into: nitration case and oxide layer with said first area are mask, form epitaxial loayer at substrate surface.
Can know that by above description method, semi-conductor device manufacturing method provided by the present invention is at contraposition vernier doped region implanted dopant; Form oxide layer at substrate surface behind the anneal oxidation, the oxide layer of said contraposition vernier doped region is the contraposition vernier, through on the contraposition vernier, forming protective layer; And then in follow-up etching, cleaning process, said contraposition vernier is owing to the effect of said protective layer is able to remain, when carrying out epitaxial growth; The epitaxial loayer only substrate surface outside the contraposition vernier is grown; Like this, though outer layer growth get again thick can be with the planarization of contraposition vernier yet, and then can read the contraposition vernier according to the contrast difference of figure.Therefore method provided by the present invention has solved the contraposition vernier by the problem of epitaxial loayer planarization compared to existing technologies on the one hand, has guaranteed the accuracy and the repetition stability of subsequent technique Figure recognition; Cancelled zero layer photoetching and etching on the other hand, no longer needed the very dark groove of etching, thereby saved equipment capacity.
The present invention also provides a kind of semiconductor device, and the structure of said semiconductor device is the same with the sketch map shown in Fig. 3 e, comprising: substrate 1; Contraposition vernier 3 in the substrate 1; Epitaxial loayer 9 on the substrate 1 outside the contraposition vernier 3.
Substrate described in the present embodiment 1 is a monocrystalline silicon, can also be semi-conducting materials such as germanium, indium phosphide or GaAs; Said contraposition vernier 3 is the oxide layer that forms behind the anneal oxidation, can also comprise the nitration case of deposition; Substrate 1 lip-deep epitaxial loayer 9 outside the contraposition vernier 3 is silicon or germanium silicon.
The forming process of the contraposition vernier 3 in the said substrate 1 is: in said substrate, form contraposition vernier doped region; Capping oxidation layer on the substrate with contraposition vernier doped region, the oxide layer of said contraposition vernier doped region is the contraposition vernier.
The forming process of the epitaxial loayer 9 on the substrate 1 outside the said contraposition vernier 3 is: form protective layer on the contraposition vernier in substrate; Remove the oxide layer on the substrate outside the contraposition vernier, and clean the protective layer on the contraposition vernier; With said contraposition vernier is mask, forms epitaxial loayer at substrate surface.
Semiconductor device for present embodiment provided is not done too much explanation at this, and relevant part can be referring to the description of method, semi-conductor device manufacturing method part.
Need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. a method, semi-conductor device manufacturing method is characterized in that, comprising:
Substrate is provided;
In said substrate, form contraposition vernier doped region;
Capping oxidation layer on substrate with contraposition vernier doped region, the contraposition vernier doped region on the said substrate partly is the first area, the part outside the contraposition vernier doped region is a second area;
Remove the oxide layer of second area and expose substrate surface;
Oxide layer with the first area is a mask, forms epitaxial loayer at substrate surface.
2. method according to claim 1 is characterized in that, in said substrate, forms contraposition vernier doped region and specifically comprises:
Form the photoresist layer of patterning at said substrate surface;
Photoresist layer with said patterning is mask implanted dopant in substrate, forms contraposition vernier doped region.
3. method according to claim 2 is characterized in that, the capping oxidation layer specifically comprises on the substrate with contraposition vernier doped region:
Remove the photoresist layer of substrate surface patterning;
Substrate is carried out anneal oxidation, form oxide layer.
4. method according to claim 3 is characterized in that, on the substrate with contraposition vernier doped region, after the capping oxidation layer, also comprises: have cvd nitride layer on the substrate of oxide layer.
5. method according to claim 1 is characterized in that, said first area thickness of oxide layer is greater than second area.
6. method according to claim 1 is characterized in that, removes the oxide layer of second area and exposes substrate surface and specifically comprise:
On the oxide layer of first area, form protective layer;
Remove the oxide layer of second area, and clean the protective layer of first area.
7. method according to claim 6 is characterized in that, said protective layer is a photoresist layer.
8. a semiconductor device is characterized in that, comprising:
Substrate;
Contraposition vernier in the said substrate;
Epitaxial loayer on the substrate outside the said contraposition vernier.
9. semiconductor device according to claim 8 is characterized in that, the forming process of the contraposition vernier in the said substrate is:
In said substrate, form contraposition vernier doped region;
Capping oxidation layer on the substrate with contraposition vernier doped region, the oxide layer of said contraposition vernier doped region is the contraposition vernier.
10. semiconductor device according to claim 9 is characterized in that, the forming process of the epitaxial loayer on the substrate outside the said contraposition vernier is:
Form protective layer on the contraposition vernier in substrate;
Remove the oxide layer on the substrate outside the contraposition vernier, and clean the protective layer on the contraposition vernier;
With said contraposition vernier is mask, forms epitaxial loayer at substrate surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102686351A CN102386056A (en) | 2010-09-01 | 2010-09-01 | Semiconductor device and manufacturing method thereof |
| PCT/CN2011/079259 WO2012028109A1 (en) | 2010-09-01 | 2011-09-01 | Semicondunctor device and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2010102686351A CN102386056A (en) | 2010-09-01 | 2010-09-01 | Semiconductor device and manufacturing method thereof |
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| CN102386056A true CN102386056A (en) | 2012-03-21 |
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| CN2010102686351A Pending CN102386056A (en) | 2010-09-01 | 2010-09-01 | Semiconductor device and manufacturing method thereof |
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| CN (1) | CN102386056A (en) |
| WO (1) | WO2012028109A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231742A (en) * | 2017-12-29 | 2018-06-29 | 吉林华微电子股份有限公司 | Photo-etching mark alignment methods and chip preparation method |
| CN114843176A (en) * | 2022-07-06 | 2022-08-02 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN114927465A (en) * | 2022-07-19 | 2022-08-19 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN115084097A (en) * | 2022-07-19 | 2022-09-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP6975912B2 (en) * | 2017-10-04 | 2021-12-01 | パナソニックＩｐマネジメント株式会社 | Semiconductor devices and their manufacturing methods |
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| CN101452211A (en) * | 2007-11-28 | 2009-06-10 | 上海华虹Nec电子有限公司 | Method for producing photolithography alignment mark |
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- 2010-09-01 CN CN2010102686351A patent/CN102386056A/en active Pending
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| JPH02102516A (en) * | 1988-10-12 | 1990-04-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04304650A (en) * | 1991-04-02 | 1992-10-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH10312964A (en) * | 1997-05-13 | 1998-11-24 | Sony Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108231742A (en) * | 2017-12-29 | 2018-06-29 | 吉林华微电子股份有限公司 | Photo-etching mark alignment methods and chip preparation method |
| CN114843176A (en) * | 2022-07-06 | 2022-08-02 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN114843176B (en) * | 2022-07-06 | 2022-09-16 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN114927465A (en) * | 2022-07-19 | 2022-08-19 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN115084097A (en) * | 2022-07-19 | 2022-09-20 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012028109A1 (en) | 2012-03-08 |
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Application publication date: 20120321 |