CN107731734B - Manufacturing method of deep groove and PN junction mixed isolation structure for high-speed bipolar process - Google Patents
Manufacturing method of deep groove and PN junction mixed isolation structure for high-speed bipolar process Download PDFInfo
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- CN107731734B CN107731734B CN201711124872.9A CN201711124872A CN107731734B CN 107731734 B CN107731734 B CN 107731734B CN 201711124872 A CN201711124872 A CN 201711124872A CN 107731734 B CN107731734 B CN 107731734B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Abstract
The invention provides a manufacturing method of a deep groove and PN junction mixed isolation structure for a bipolar process, which comprises the following steps: setting a mask on a substrate silicon wafer; arranging an etching window penetrating through the mask on the mask, and etching the underlying substrate silicon wafer through the etching window to form a deep groove; injecting impurities with the opposite type to the bulk silicon doping type to form a groove bottom isolation PN junction; stripping the mask, and preparing an ONO composite film on the surface of the bulk silicon and in the deep groove; depositing polycrystalline silicon to fill the deep groove; removing the silicon oxide on the top layer of the ONO film outside the deep groove, and forming an active region by using the residual silicon nitride-silicon oxide structure; the ONO structure on the inner wall of the deep groove skillfully balances the internal stress of the groove, and simultaneously, the silicon nitride/oxide layer structure serves as a masking layer for the oxidation of the active area in the subsequent process, so that the additional step of manufacturing the masking layer during the manufacturing of the active area is avoided, the manufacturing cost of the process is effectively reduced, and the isolation effect is improved.
Description
Technical Field
The invention relates to the field of manufacturing of semiconductor analog integrated circuits, in particular to a manufacturing method of a deep groove and PN junction mixed isolation structure for a high-speed bipolar process.
Background
In semiconductors, both majority and minority carrier polarity carriers (holes and electrons) participate in the conduction of active components, such as typical NPN or PNP bipolar transistors. The monolithic integrated circuits based on such transistors are called bipolar integrated circuits, which are fast and widely used in analog integrated circuits and digital integrated circuits. Electrical isolation is required between components in bipolar integrated circuits.
Wherein, the deep groove isolation process has the remarkable advantages that: 1. the area of the device is reduced, and the integration level is improved; 2. the collector capacitance is reduced; 3. the breakdown voltage between the collectors of the bipolar transistors is increased. Deep trench isolation is therefore increasingly used in the field of integrated circuit fabrication.
At present, polysilicon is usually used for filling in a deep trench isolation structure, and due to a plurality of high-temperature thermal processes in a semiconductor process, the stress of a silicon wafer is greatly changed in the process, so that the performance of a device is reduced, and the subsequent process flow is influenced.
On the other hand, in the field of high-speed, high-precision analog integrated circuit applications, low leakage current between devices is required. In the prior art, high isolation effect is usually realized by adopting full-medium deep-groove isolation, however, full-medium isolation has two main problems, namely, the cost of the full-medium isolation process is high; and the yield of the all-dielectric isolation process is lower compared with that of the conventional silicon process. The PN junction isolation, which is the most commonly used isolation method, has the disadvantage of large isolation leakage current and cannot completely meet the design requirement, so a new technical means is needed to solve the above technical problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a deep trench and PN junction hybrid isolation structure for high-speed bipolar process to solve the above-mentioned technical problems.
The invention provides a manufacturing method of a deep groove and PN junction mixed isolation structure for a high-speed bipolar process, which comprises the following steps:
setting a mask on a substrate silicon wafer;
arranging an etching window penetrating through the mask on the mask, and etching the underlying substrate silicon wafer through the etching window to form a deep groove;
injecting impurities with the opposite type to the bulk silicon doping type to form a groove bottom isolation PN junction;
stripping the mask, and preparing an ONO composite film on the surface of the bulk silicon and in the deep groove;
depositing polycrystalline silicon to fill the deep groove;
and removing the silicon oxide on the top layer of the ONO film outside the deep groove, and forming an active region by using the residual silicon nitride-silicon oxide structure.
Further, the forming of the deep trench by etching the underlying base silicon wafer through the etching window includes:
etching the substrate silicon wafer at the lower layer through the etching window to form a shallow groove with an inverted trapezoidal section;
and continuously etching along the bottom surface of the shallow groove vertically downwards to form a deep groove.
Further, after depositing polycrystalline silicon to fill the deep groove, etching back the polycrystalline silicon at the top of the deep groove, and removing redundant polycrystalline silicon outside the deep groove.
Further, the mask is a silicon oxide mask layer, a photoresist window is formed on the silicon oxide mask layer through a photoetching process by utilizing photoresist, and the silicon oxide mask layer is etched through the photoresist window to obtain the etching window.
Further, the ONO composite film comprises a bottom layer oxide layer, a middle layer silicon nitride layer and a top layer silicon oxide layer, wherein the thickness of the bottom layer silicon oxide layer is 800-1200 angstroms, the thickness of the middle layer silicon nitride layer is 200-400 angstroms, and the thickness of the top layer silicon oxide layer is 800-1200 angstroms.
Further, the forming the active region using the remaining silicon nitride-silicon oxide structure includes: and locally removing the middle silicon nitride layer, and performing oxidation treatment to form a LOCOS region.
Further, the etching window is an annular closed structure.
Further, the deposited polysilicon has a thickness greater than 5000 angstroms.
The invention also provides a deep groove and PN junction mixed isolation structure for a high-speed bipolar process, which is prepared by any one of the methods.
The invention has the beneficial effects that: the manufacturing method of the deep groove and PN junction mixed isolation structure for the high-speed bipolar process aims at the problems that the cost of the full-medium deep groove isolation process is high, the yield is not high and the isolation effect of the single common PN junction and the single deep groove is not good in the high-speed bipolar process, skillfully balances the internal stress of the groove by the deep groove and PN junction mixed isolation structure and utilizing the ONO structure of the inner wall of the deep groove, and meanwhile, the silicon nitride/oxide layer structure serves as a masking layer for the oxidation of an active area in the subsequent process.
Drawings
FIG. 1 is a schematic diagram of a silicon oxide mask layer formed on a silicon substrate in an embodiment of the present invention.
Fig. 2 is a schematic diagram of forming an etching window on a silicon oxide by a photolithography process in an embodiment of the present invention.
FIG. 3 is a diagram illustrating an etching window according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view illustrating the removal of the photoresist according to the embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a shallow trench in the deep trench processing process in the embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view illustrating the deep trench etching process performed in the embodiment of the present invention.
Fig. 7 is a schematic structural diagram of implanting impurities with a type opposite to that of bulk silicon into the bottom of the trench in the embodiment of the present invention.
FIG. 8 is a schematic structural diagram of stripping a silicon oxide mask layer in an embodiment of the invention.
FIG. 9 is a schematic diagram of an ONO composite film formed on a bulk silicon surface and in a deep trench formed therein according to an embodiment of the present invention.
FIG. 10 is a cross-sectional view of an embodiment of the present invention after polysilicon deposition to fill the deep trench.
FIG. 11 is a schematic cross-sectional view illustrating a multi-poly etch back according to an embodiment of the invention.
FIG. 12 is a schematic view of a top silicon oxide layer of the ONO composite film removed in accordance with an embodiment of the present invention.
FIG. 13 is a schematic view of selectively removing a silicon nitride layer in the intermediate layer of the ONO composite film in accordance with one embodiment of the present invention.
Fig. 14 is a schematic cross-sectional structure diagram after the LOCOS process is completed in the embodiment of the present invention.
FIG. 15 is a cross-sectional SEM image of a deep trench after poly filling in an embodiment of the invention.
FIG. 16 is a graph comparing leakage current with voltage between devices according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The manufacturing method of the deep trench and PN junction hybrid isolation structure for the high-speed bipolar process in the embodiment includes:
setting a mask on a substrate silicon wafer;
arranging an etching window penetrating through the mask on the mask, and etching the underlying substrate silicon wafer through the etching window to form a deep groove;
injecting impurities with the opposite type to the bulk silicon doping type to form a groove bottom isolation PN junction;
stripping the mask, and preparing an ONO composite film on the surface of the bulk silicon and in the deep groove;
depositing polycrystalline silicon to fill the deep groove;
and removing the silicon oxide on the top layer of the ONO film outside the deep groove, and forming an active region by using the residual silicon nitride-silicon oxide structure.
In this embodiment, the etching window is an annular closed structure, the mask is a silicon oxide mask layer, in this embodiment, a photoresist window is formed on the silicon oxide mask layer by using a photoresist through a photolithography process, the silicon oxide mask layer is etched through the photoresist window to obtain the etching window, and the etching window is used to etch the underlying substrate silicon wafer to form a deep trench, specifically:
etching the substrate silicon wafer at the lower layer through the etching window to form a shallow groove with an inverted trapezoidal section;
and continuously etching along the bottom surface of the shallow groove vertically downwards to form a deep groove.
In this embodiment, after the deep trench is filled with deposited polysilicon, the polysilicon at the top of the deep trench is etched back to remove the excess polysilicon outside the deep trench, and meanwhile, the over-etching of the polysilicon in the deep trench is avoided.
In this embodiment, forming the active region using the remaining silicon nitride-silicon oxide structure includes: and locally removing the middle silicon nitride layer, and performing oxidation treatment to form a LOCOS region. Removing the silicon oxide 6 on the top layer of the ONO film outside the deep groove, realizing selective oxidation of silicon (LOCOS) by utilizing the residual silicon oxide and silicon nitride structure, selectively removing the silicon nitride 5 according to the requirement through photoetching, oxidizing, forming field oxide 8 by the polysilicon on the top of the deep groove, activating the injected impurities, and forming a PN junction 9 at the bottom of the groove.
The following is a detailed description of a specific example:
s1, selecting a substrate silicon wafer to form a layer of silicon oxide mask on the surface of the silicon wafer;
s2, forming an etching window on the silicon oxide through a photoetching process;
s3, etching the silicon oxide mask to form a window penetrating through the silicon oxide layer;
s4, removing the photoresist;
s5, etching the bulk silicon below the window to form a deep groove;
s6, injecting impurities with the opposite type to the bulk silicon doping type to form a groove bottom isolation PN junction;
s7, stripping the silicon oxide mask;
s8, preparing an ONO composite film on the surface of bulk silicon and the inner wall of the formed deep groove;
s9, depositing polysilicon to fill the deep groove;
s10, etching back the polysilicon outside the deep groove;
and S11, removing the silicon oxide on the top layer of the ONO film outside the deep groove, and realizing local oxidation of silicon (LOCOS) by utilizing the residual silicon nitride/silicon oxide structure to form an active region.
As shown in fig. 1, in step S1, the present embodiment selects a P-type silicon substrate 1 with a thickness of 625 microns, and the top layer is an N-type epitaxial layer with a thickness of 2.5 microns. A silicon oxide mask layer is formed, preferably by PECVD in this embodiment a silicon oxide mask 2 of thickness 5000 angstroms is deposited.
As shown in fig. 2, a photoresist window is formed on the silicon oxide by a photolithography process using a photoresist 3. Preferably, in this embodiment, the size of the formed window is 1 micron, as shown in fig. 2.
As shown in fig. 3, the silicon oxide mask 2 is etched to form an opening through the silicon oxide mask, i.e., an etching opening, so that the silicon wafer 1 under the mask is exposed. I.e. the silicon wafer 1 is below the window and the silicon oxide mask 2 is around it. Preferably, in this embodiment, the silicon oxide mask is etched by using a dry etching process.
As shown in fig. 4, after removing the photoresist 3 on the surface of the silicon oxide, a step-by-step etching is performed to the deep trench. In this embodiment, a trench with an inclination angle of about 85 ° and a depth of about 2 μm is etched first, as shown in fig. 5, the interface is a trapezoid structure, and the bottom dimension of the trapezoid structure is smaller than the top dimension; and continuing etching at the bottom of the groove to form a steep deep groove, as shown in fig. 6. The total depth of the grooves in this example was 7.5 microns. The deep groove penetrates through the N-type epitaxial layer to reach the substrate silicon wafer. Preferably, the deep trench etching process in this embodiment adopts a Reactive Ion Etching (RIE) technique with anisotropic etching characteristics to meet the anisotropic requirement.
As shown in fig. 7, impurities of opposite doping type to the bulk silicon are implanted into the deep trench. In an embodiment, boron is implanted as a P-type impurity, and then the silicon oxide mask 2 is removed. Preferably, in the present embodiment, the silicon oxide mask 2 is removed by wet etching, as shown in fig. 8.
As shown in fig. 9, an ONO composite film is formed on the surface of the silicon wafer and in the deep trench formed. Preferably, in the embodiment, an oxide layer 4 with a thickness of 1000 angstroms is formed on the bottom by thermal oxidation; then growing a silicon nitride layer 5 with the thickness of 300 angstroms by a vertical furnace; finally, a 1000 angstrom silicon oxide layer 6 is grown on top by CVD.
As shown in fig. 10, polysilicon 7 is deposited to fill the deep trench. Preferably, the thickness of the deposited polysilicon is 8000A, and the time slot is filled with polysilicon. The surface of the silicon wafer also has a layer of polysilicon, which needs to be removed in subsequent process steps.
As shown in fig. 11, the polysilicon excess outside the deep trench is removed. In this embodiment, the etching back is performed by dry etching. The silicon oxide layer 6 on the top layer of the ONO composite film can provide an end point detection signal for polycrystalline etching, so that polycrystalline etching in a deep groove is avoided.
As shown in fig. 12, the silicon oxide 6 on the top layer of the ONO film outside the deep trench is removed, and then the selective oxidation of silicon (LOCOS) is implemented by using the remaining silicon oxide plus silicon nitride structure. In an embodiment, the silicon oxide layer 6 on the top layer of the ONO composite film is removed using a wet etch.
As shown in fig. 13, the silicon nitride 5 is selectively removed by photolithography etching, and then field oxidation is performed.
As shown in fig. 14, the LOCOS region of selective oxidation is not drawn in the schematic diagrams (fig. 13 and 14). At this point, the polysilicon at the top of the deep trench will be oxidized to form field oxide 8. At the same time, the implanted P-type impurity is activated to form a PN junction 9 at the bottom of the trench.
Correspondingly, the embodiment also provides a deep trench and PN junction hybrid isolation structure for high-speed bipolar process, which is manufactured by the method, and FIG. 15 shows a cross-sectional SEM image of the deep trench manufactured by the manufacturing method of the invention after polycrystalline filling.
As shown in fig. 16, in this embodiment, in order to verify the practical effect of the deep trench and PN junction hybrid isolation structure of the present invention, the leakage current of the deep trench isolation structure with or without PN junction isolation is compared. It can be seen that, with the structure manufactured by the method in the embodiment, the isolation leakage between devices is obviously reduced, and the isolation effect is obviously improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for fabricating a deep trench and PN junction hybrid isolation structure for high speed bipolar processing, comprising:
setting a mask on a substrate silicon wafer;
arranging an etching window penetrating through the mask on the mask, and etching the underlying substrate silicon wafer through the etching window to form a deep groove;
injecting impurities with the opposite type to the bulk silicon doping type to form a groove bottom isolation PN junction;
stripping the mask, and preparing an ONO composite film on the surface of the bulk silicon and in the deep groove;
depositing polycrystalline silicon to fill the deep groove;
removing the silicon oxide on the top layer of the ONO film outside the deep groove, and forming an active region by using the residual silicon nitride-silicon oxide structure;
the etching of the underlying substrate silicon wafer through the etching window to form the deep trench includes:
etching the substrate silicon wafer at the lower layer through the etching window to form a shallow groove with an inverted trapezoidal section;
and continuously etching along the bottom surface of the shallow groove vertically downwards to form a deep groove.
2. The method of claim 1, wherein after depositing polysilicon to fill the deep trench, etching back polysilicon at the top of the deep trench to remove excess polysilicon outside the deep trench.
3. The method of claim 1, wherein the mask is a silicon oxide mask layer, a photoresist window is formed on the silicon oxide mask layer by a photolithography process using a photoresist, and the silicon oxide mask layer is etched through the photoresist window to obtain the etching window.
4. The method as claimed in claim 1, wherein the ONO composite film comprises a bottom oxide layer, a middle silicon nitride layer and a top silicon oxide layer, the bottom silicon oxide layer has a thickness of 800-1200 angstroms, the middle silicon nitride layer has a thickness of 200-400 angstroms, and the top silicon oxide layer has a thickness of 800-1200 angstroms.
5. The method of claim 4, wherein the forming an active region using the remaining silicon nitride-silicon oxide structure comprises: and locally removing the middle silicon nitride layer, and performing oxidation treatment to form a LOCOS region.
6. The method of manufacturing a deep trench and PN junction hybrid isolation structure for high speed bipolar process as claimed in claim 1, wherein: the etching window is in an annular closed structure.
7. The method of claim 1 wherein the deposited polysilicon has a thickness greater than 5000 angstroms.
8. A deep groove and PN junction mixed isolation structure for high-speed bipolar process is characterized in that: the structure is prepared by the method of any one of claims 1-7.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108783A (en) * | 1988-12-23 | 1992-04-28 | Sharp Kabushiki Kaisha | Process for producing semiconductor devices |
| CN103187355A (en) * | 2013-01-29 | 2013-07-03 | 中航（重庆）微电子有限公司 | Semiconductor substrate with isolated structure and manufacturing method thereof |
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| US8623726B2 (en) * | 2010-12-23 | 2014-01-07 | Macronix International Co., Ltd. | Method for filling a physical isolation trench and integrating a vertical channel array with a periphery circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108783A (en) * | 1988-12-23 | 1992-04-28 | Sharp Kabushiki Kaisha | Process for producing semiconductor devices |
| CN103187355A (en) * | 2013-01-29 | 2013-07-03 | 中航（重庆）微电子有限公司 | Semiconductor substrate with isolated structure and manufacturing method thereof |
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