CN106229265A - Method for half floating transistor floating boom technique - Google Patents
Method for half floating transistor floating boom technique Download PDFInfo
- Publication number
- CN106229265A CN106229265A CN201610692299.0A CN201610692299A CN106229265A CN 106229265 A CN106229265 A CN 106229265A CN 201610692299 A CN201610692299 A CN 201610692299A CN 106229265 A CN106229265 A CN 106229265A
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- Prior art keywords
- floating boom
- half floating
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- coating
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 18
- 238000000576 coating method Methods 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 238000005406 washing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of method for half floating transistor floating boom technique, including: first step: form half floating boom well region in substrate, form oxide skin(coating) at substrate surface, and in half floating boom well region, form the half floating boom groove separated by isolation area；Sequentially form SOC material layer, ARC and photoresist layer on the oxide layer, and form the pattern of photoresist layer；The photoresist layer etching ARC, SOC material layer and the oxide skin(coating) that form pattern is utilized to form opening in the oxide layer to be formed；Remove SOC material layer, ARC and photoresist layer, wherein eliminate the SOC material layer in half floating boom groove；Clean the oxide skin(coating) exposed；Deposit gate polysilicon layer after the washing.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to one is floated for half floating transistor
The method of grid technique.
Background technology
Half floating transistor be microelectronics institute of Fudan University develop between MOSFET and floating transistor
Scientific achievement.Conventional floating gate transistor is by the silicon dioxide insulator of too high for electron tunneling potential barrier (energy gap close to 8.9eV)
Medium, and the tunnelling of half floating transistor occurs in the silicon materials of energy gap only 1.1eV, tunneling barrier is greatly lowered.
This structure design of half floating transistor can allow the data of half floating transistor are erasable to be more prone to and rapidly,
Whole process can complete under low voltage condition, creates condition for realizing chip low power operation.
At present Fudan University and Shanghai integrated circuit research and development centre (ICRD), magnificent power R & D Cooperation are based on 40nm platform new
Type half floating transistor.Compared with magnificent power existing 40nm platform technology, need to increase extra five light shields and define half floating boom
Device.
The technique of floating boom through hole is the most special in half floating boom technique, and its main purpose is to allow floating boom and substrate connect
Together, and after via opening dry stripping (Dry Strip) is since it is desired that give substantial amounts of remaining photoresistance and SOC material
Remove, so dry stripping (uses O2) time longer, cause the place of substrate floating gate through hole can grow one layer of primary oxidation
Layer (Native Oxide) and can not get design structure.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can be protected
The method for half floating transistor floating boom technique that card floating boom and substrate link together.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of for half floating transistor floating boom technique
Method, including:
First step: form half floating boom well region in substrate, forms oxide skin(coating) at substrate surface, and at half floating boom well region
The half floating boom groove that middle formation is separated by isolation area；
Second step: sequentially form SOC material layer, ARC and photoresist layer on the oxide layer, and form light
The pattern of photoresist layer；
Third step: utilize the photoresist layer etching ARC, SOC material layer and the oxide skin(coating) that form pattern with shape
Become to form opening in the oxide layer；
4th step: remove SOC material layer, ARC and photoresist layer, wherein eliminate in half floating boom groove
SOC material layer；
5th step: clean the oxide skin(coating) exposed；
6th step: deposit gate polysilicon layer after the washing.
Preferably, the thickness of SOC material layer is 2000A.
Preferably, the thickness of ARC is 380A.
Preferably, the thickness of photoresist layer is 900A.
Preferably, half floating boom well region is the trap of p-type doping.
Preferably, the height of half floating boom groove is 1200A.
Preferably, the width of half floating boom groove is 60nm.
Preferably, the thickness of gate polysilicon layer is 1000A.
Preferably, diluted hydrofluoric acid is utilized to clean the oxide skin(coating) exposed in the 5th step.
Preferably, substrate is silicon substrate.
The present invention is by increasing by one layer of polysilicon and cleaning increasing before follow-up polycrystalline silicon growth after floating boom gate oxide growth
Add the technique that DHF cleans, both prevented the subsequent technique damage to grid oxygen, and can clean, by DHF, the primary oxygen that will produce again
Change layer is got rid of, thus ensures that floating boom and substrate link together.
And, use the advantage of polysilicon to be, rapid thermal oxidation (RTO) board itself has the function of long polysilicon,
Without going past extra board, more without waiting for the problem of time (Qtime).If using other material of such as silicon nitride etc
Material, it is necessary to through extra board.And, use the advantage of polysilicon to also reside in, polysilicon need not wash off completely, passes through
DHF cleans can be to superpose with follow-up polycrystalline silicon growth.If using other material of such as silicon nitride etc, follow-up just have together
Phosphoric acid cleans, and phosphoric acid can cause the uniformity of grid oxygen to be deteriorated.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows method for half floating transistor floating boom technique according to the preferred embodiment of the invention
First step.
Fig. 2 schematically shows method for half floating transistor floating boom technique according to the preferred embodiment of the invention
Second step.
Fig. 3 schematically shows method for half floating transistor floating boom technique according to the preferred embodiment of the invention
Third step.
Fig. 4 schematically shows method for half floating transistor floating boom technique according to the preferred embodiment of the invention
The 4th step.
Fig. 5 schematically shows method for half floating transistor floating boom technique according to the preferred embodiment of the invention
The 6th step.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 to Fig. 5 schematically shows according to the preferred embodiment of the invention for half floating transistor floating boom technique
Each step of method.
As shown in Figures 1 to 5, according to the preferred embodiment of the invention for the method bag of half floating transistor floating boom technique
Include:
First step: form half floating boom well region 10 in substrate 100, at substrate 100 surface formation oxide skin(coating) 30, and
Half floating boom well region 10 forms the half floating boom groove 20 separated by isolation area, as shown in Figure 1；Half floating boom groove surfaces is also oxidation
Nitride layer.
Typically, substrate 100 is silicon substrate.Such as, half floating boom well region 10 is the trap of p-type doping.
Preferably, the height of half floating boom groove 20 is 1200A.And preferably, the width of half floating boom groove 20 is 60nm.
Second step: sequentially form SOC material layer 40, ARC 50 and photoresist layer 60 on oxide skin(coating) 30,
And form the pattern of photoresist layer 60, as shown in Figure 2；
Preferably, the thickness of SOC material layer 40 is 2000A.Preferably, the thickness of ARC 50 is 380A.Preferably
Ground, the thickness of photoresist layer 60 is 900A.
Third step: utilize the photoresist layer 60 forming pattern to etch ARC 50, SOC material layer 40 and oxide
Layer 30 is to be formed in oxide skin(coating) 30 formation opening 31, as shown in Figure 3；
4th step: remove SOC material layer 40, ARC 50 and photoresist layer 60, wherein eliminate half floating boom recessed
SOC material layer 40 in groove 20；As shown in Figure 4；
5th step: clean the oxide skin(coating) 30 exposed；Preferably, diluted hydrofluoric acid (DHF) is utilized to clean in the 5th step
The oxide skin(coating) 30 exposed.
6th step: deposition gate polysilicon layer 70 after the washing, as shown in Figure 5.
Preferably, the thickness of gate polysilicon layer 70 is 1000A.
The present invention is by increasing by one layer of polysilicon and cleaning increasing before follow-up polycrystalline silicon growth after floating boom gate oxide growth
Add the technique that DHF cleans, both prevented the subsequent technique damage to grid oxygen, and can clean, by DHF, the primary oxygen that will produce again
Change layer is got rid of, thus ensures that floating boom and substrate link together.
And, use the advantage of polysilicon to be, rapid thermal oxidation (RTO) board itself has the function of long polysilicon,
Without going past extra board, more without waiting for the problem of time (Qtime).If using other material of such as silicon nitride etc
Material, it is necessary to through extra board.And, use the advantage of polysilicon to also reside in, polysilicon need not wash off completely, passes through
DHF cleans can be to superpose with follow-up polycrystalline silicon growth.If using other material of such as silicon nitride etc, follow-up just have together
Phosphoric acid cleans, and phosphoric acid can cause the uniformity of grid oxygen to be deteriorated.
It should be noted that unless stated otherwise or point out, otherwise the term in description " first ", " second ", "
Three " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each assembly, unit
Element, logical relation between step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (10)
1. the method for half floating transistor floating boom technique, it is characterised in that including:
First step: form half floating boom well region in substrate, forms oxide skin(coating), and shape in half floating boom well region at substrate surface
Become the half floating boom groove separated by isolation area；
Second step: sequentially form SOC material layer, ARC and photoresist layer on the oxide layer, and form photoresist
The pattern of layer；
Third step: utilize the photoresist layer etching ARC, SOC material layer and the oxide skin(coating) that form pattern to be formed at
Oxide skin(coating) is formed opening；
4th step: remove SOC material layer, ARC and photoresist layer, wherein eliminate the SOC material in half floating boom groove
The bed of material；
5th step: clean the oxide skin(coating) exposed；
6th step: deposit gate polysilicon layer after the washing.
Method for half floating transistor floating boom technique the most according to claim 1, it is characterised in that SOC material layer
Thickness be 2000A.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that antireflection
The thickness of coating is 380A.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that photoresist
The thickness of layer is 900A.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that half floating boom
Well region is the trap of p-type doping.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that half floating boom
The height of groove is 1200A.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that half floating boom
The width of groove is 60nm.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that grid is many
The thickness of crystal silicon layer is 1000A.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that the 5th
Step utilizes diluted hydrofluoric acid to clean the oxide skin(coating) exposed.
Method for half floating transistor floating boom technique the most according to claim 1 and 2, it is characterised in that substrate is
Silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610692299.0A CN106229265A (en) | 2016-08-19 | 2016-08-19 | Method for half floating transistor floating boom technique |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610692299.0A CN106229265A (en) | 2016-08-19 | 2016-08-19 | Method for half floating transistor floating boom technique |
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| Publication Number | Publication Date |
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| CN106229265A true CN106229265A (en) | 2016-12-14 |
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| CN201610692299.0A Pending CN106229265A (en) | 2016-08-19 | 2016-08-19 | Method for half floating transistor floating boom technique |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600380A (en) * | 2019-08-29 | 2019-12-20 | 长江存储科技有限责任公司 | Preparation method of semi-floating gate transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
| CN102931073A (en) * | 2011-08-11 | 2013-02-13 | 无锡华润上华半导体有限公司 | Method for manufacturing semiconductor device |
| CN104701263A (en) * | 2015-03-23 | 2015-06-10 | 上海集成电路研发中心有限公司 | Manufacturing method of semi-floating-gate device |
-
2016
- 2016-08-19 CN CN201610692299.0A patent/CN106229265A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254821A (en) * | 2011-07-11 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor |
| CN102931073A (en) * | 2011-08-11 | 2013-02-13 | 无锡华润上华半导体有限公司 | Method for manufacturing semiconductor device |
| CN104701263A (en) * | 2015-03-23 | 2015-06-10 | 上海集成电路研发中心有限公司 | Manufacturing method of semi-floating-gate device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600380A (en) * | 2019-08-29 | 2019-12-20 | 长江存储科技有限责任公司 | Preparation method of semi-floating gate transistor |
| CN110600380B (en) * | 2019-08-29 | 2023-03-10 | 长江存储科技有限责任公司 | Preparation method of semi-floating gate transistor |
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Application publication date: 20161214 |