JPH10312964A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor reducing the shifting of alignment at the time of exposure in a lithography process after forming an epitaxial layer. SOLUTION: On a semiconductor substrate 1 such as a p-type Si substrate, an SiO3 N4 film 3 are successively laminated and formed, and the films 3 and 2 are patterned in a prescribed form to form an alignment mark, consisting of the laminated film of the films 2 and 3 on the surface of the substrate 1. After then an epitaxial layer 4 is selectively formed at between 700 deg.C and 800 deg.C only on a surface, where the substrate 1 is exposed. Temperature at the time of forming the layer 4 is made between 900 deg.C and 1100 deg.C, preferably between 950 deg.C and 1000 deg.C, to selectively form the layer 4 on the surface of the substrate 1 and a polycrystalline Si film can be stacked on the film 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, in which an epitaxial layer is formed on a semiconductor substrate, and a high withstand voltage bipolar integrated circuit, a high withstand voltage MOS integrated circuit, The present invention relates to a method for manufacturing a semiconductor device in which a high breakdown voltage BiCMOS integrated circuit or the like is formed.

[0002]

2. Description of the Related Art In recent years, with the spread of personal computers and the increase in size of home televisions, the display market has been rapidly expanding. At present, cathode ray tube (CRT) displays having excellent visibility such as high definition, high brightness, wide viewing angle, and high contrast are the most common in the field of displays. However, this CRT display has a problem that its occupied area increases with the increase in screen size. Therefore, in addition to a liquid crystal display and a projector display, a flat panel display such as a plasma display using a new method using plasma can be made thin. Is expected as a next-generation display replacing a CRT display. Under these circumstances, in the field of semiconductor devices, high breakdown voltage transistors having a breakdown voltage of about several hundred volts are required, such as driver transistors for controlling liquid crystal and plasma. Such a high breakdown voltage transistor forms an epitaxial layer on a semiconductor substrate,
It is generally manufactured by forming a diffusion layer in this epitaxial layer.

[0003]

However, when a high breakdown voltage transistor is formed using an epitaxial layer, the thickness of the epitaxial layer formed on the semiconductor substrate increases with the increase in the breakdown voltage of the transistor. Conventionally, the following problem has occurred.

That is, usually, in the process of manufacturing such a transistor, a resist pattern having a predetermined shape used as an ion implantation mask for ion implantation of impurities or an etching mask for patterning an insulating film by etching is formed. For this purpose, it has a plurality of lithography steps. For this reason, it is necessary to precisely perform alignment (alignment) of a photomask and a reticle each time exposure is performed in each lithography process. Therefore, conventionally, a step has been formed on the surface by etching a semiconductor substrate, and this step has been used as an alignment mark as a reference for alignment.

However, when the semiconductor substrate is etched to form a stepped portion of the alignment mark on the surface, a crystal orientation different from that of the main surface of the semiconductor substrate is present at the stepped portion, so that the semiconductor substrate has a different crystal orientation. When the epitaxial layer is formed, the step of the alignment mark is distortedly transferred to the surface of the epitaxial layer, and there is a problem that the alignment shift occurs during exposure in a lithography process performed after the formation of the epitaxial layer. This misalignment occurs because the thickness of the epitaxial layer formed on the semiconductor substrate is large (for example, 5 μm
Above), which is a serious problem when a high breakdown voltage transistor is formed using an epitaxial layer.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing misalignment during exposure in a lithography step after formation of an epitaxial layer.

[0007]

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device in which an epitaxial layer is formed on a semiconductor substrate. And forming a step on the surface of the semiconductor substrate by patterning the insulating film into a predetermined shape, and selectively forming an epitaxial layer on the surface of the semiconductor substrate not covered with the insulating film. It is characterized by having.

[0008] In a typical embodiment of the invention,
A silicon substrate is used as a semiconductor substrate.

In a preferred embodiment of the present invention, a laminated film of a silicon dioxide film formed on a semiconductor substrate and a silicon nitride film formed on the silicon dioxide film is used as an insulating film. This is because the stress of the silicon nitride film can be reduced by forming the silicon nitride film on the silicon dioxide film, and the difference in growth rate is utilized by using the silicon nitride film as the top layer of the insulating film. This is because it becomes easy to selectively form the epitaxial layer only on the semiconductor substrate.

In one embodiment of the present invention, when forming an epitaxial layer on a semiconductor substrate, the temperature at which the epitaxial layer is formed is selected from the viewpoint of performing selective epitaxial growth without depositing a film on an insulating film. Is selected, for example, between 700 ° C. and 800 ° C.

In another embodiment of the present invention, when forming an epitaxial layer on a semiconductor substrate, a polycrystalline semiconductor film can be deposited on an insulating film, and an alignment mark is formed on the surface of the epitaxial layer. From the viewpoint of being able to form a recognizable step,
The temperature for forming the epitaxial layer is, for example, 90
The temperature is selected from 0 ° C to 1100 ° C, preferably, for example, from 950 ° C to 1000 ° C.

According to the present invention, an insulating film is formed on a semiconductor substrate, and the insulating film is patterned into a predetermined shape to form a step on the surface of the semiconductor substrate. A convex alignment mark made of an insulating film is formed on the surface of the base. in this case,
Since the growth rate of the epitaxial layer on the insulating film is significantly lower than the growth rate of the epitaxial layer on the semiconductor substrate, the epitaxial layer is hardly deposited on the insulating film so that the exposed surface of the semiconductor substrate is prevented. Can be selectively formed only on the substrate. At this time, unlike the conventional method in which the alignment mark is formed by etching the semiconductor substrate, there is no crystal orientation different from that of the surface of the semiconductor substrate at the stepped portion. The alignment mark thus formed can be transferred without distortion, and therefore in the same shape. Thus, in a lithography process performed after the formation of the epitaxial layer, alignment deviation during exposure can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, the method for fabricating the semiconductor device according to the first embodiment of the present invention will be described. 1 to 4
A method for manufacturing the semiconductor device according to the first embodiment will be described. Here, an example in which an epitaxial layer is formed on a semiconductor substrate and a high breakdown voltage npn transistor is formed using the epitaxial layer will be described.

That is, in this method of manufacturing a semiconductor device, as shown in FIG. 1, for example, p-type silicon (S
i) By thermally oxidizing a semiconductor substrate 1 such as a substrate at a temperature of 900 ° C. to 1000 ° C. in steam, for example,
A silicon dioxide (SiO ₂ ) film 2 having a thickness of about 10 to 50 nm is formed on the semiconductor substrate 1, and a thickness of 50 to 100 nm is formed on the SiO ₂ film 2 by, for example, a chemical vapor deposition (CVD) method. A silicon nitride (Si ₃ N ₄ ) film 3 is formed to a degree.

Next, as shown in FIG. 2, the Si ₃ N ₄ film 3
After a resist pattern (not shown) having a predetermined shape is formed thereon by lithography, using this resist pattern as a mask, for example, reactive ion etching (RI)
By selectively etching and removing the Si ₃ N ₄ film 3 and the SiO ₂ film 2 by the method E), a step is formed on the surface of the semiconductor substrate 1 in the alignment mark forming region. As a result, a convex alignment mark composed of a laminated film of the SiO ₂ film 2 and the Si ₃ N ₄ film 3 is formed on the surface of the semiconductor substrate 1. After this, the Si ₃ N ₄ film 3
The resist pattern used as an etching mask for the SiO ₂ film 2 is stripped using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution.

Next, as shown in FIG. 3, the semiconductor substrate 1 is, for example, 70 nm thick by an existing epitaxial growth method.
At a temperature of 0 ° C. to 800 ° C., an epitaxial layer 4 made of, for example, n-type Si is formed. This epitaxial layer 4
Is formed to a thickness that can provide an absolute rating (particularly, a withstand voltage) required for an npn transistor to be finally formed.
Here, the thickness of the epitaxial layer 4 is set to, for example, 5 μm.
m or more. Thereby, the finally formed npn
A high value of, for example, 90 V or more is obtained as the breakdown voltage of the transistor. At this time, the portion on the Si ₃ N ₄ film 3, as compared to the portion on the semiconductor substrate 1, since the growth rate of the epitaxial layer 4 is significantly decreased, the epitaxial layer 4, the Si ₃ N ₄ film 3 above And is selectively formed only on the exposed surface of the semiconductor substrate 1. As described above, as a result of the selective formation of the epitaxial layer 4 on the semiconductor substrate 1, the surface of the epitaxial layer 4
The alignment mark formed on the semiconductor substrate 1 is transferred in the same shape without distortion. After the formation of the epitaxial layer 4, the steps formed on the surface of the epitaxial layer 4 are used as alignment marks.

After forming up to the epitaxial layer 4 on the semiconductor substrate 1 in this manner, as shown in FIG. 4, a high breakdown voltage is applied to the epitaxial layer 4 in the element forming region according to a normal bipolar transistor manufacturing process. An npn transistor is formed. In FIG. 4, reference numeral 11 denotes an n ⁺ type buried layer formed in the semiconductor substrate 1. The n ⁺ -type buried layer 11 is formed by ion-implanting an n-type impurity such as phosphorus (P) into the semiconductor substrate 1 before forming the epitaxial layer 4. The n ⁺ type buried layer 11 is also formed below the epitaxial layer 4 when the epitaxial layer 4 is grown.

In order to form a high breakdown voltage npn transistor in the epitaxial layer 4, first, after the epitaxial layer 4 is formed, a predetermined portion of the epitaxial layer 4 is selectively oxidized by, for example, the LOCOS method.
After forming the field oxide film 12 and performing element isolation,
In a predetermined portion of the epitaxial layer 4 in the active region, for example, by selectively doped with n-type impurities such as P, and form an n ⁺ -type collector contact region 13 to be connected to the n ⁺ -type buried layer 11. Next, after an insulating film 14 made of a SiO ₂ film is formed on the entire surface by, for example, a CVD method, an opening 15 is formed in a predetermined portion of the insulating film 14.

Next, a polycrystalline Si film serving as a base electrode is formed on the entire surface by, for example, a CVD method, and BF ₂ is doped into the polycrystalline Si film by, for example, an ion implantation method. Next, Si is deposited on this polycrystalline Si film by, for example, a CVD method.
An insulating film 16 made of an O ₂ film is formed. Next, by patterning the insulating film 16 and the polycrystalline Si film into a predetermined shape, a base electrode 17 is formed in a predetermined portion and an opening 18 is formed. Next, the p-type base region 1 is doped into the epitaxial layer 4 through the opening 18 by, for example, doping BF ₂ by ion implantation.
9 is formed.

Next, for example, by the CVD method,
After the O ₂ film is formed, the SiO ₂ film is etched back to form a sidewall 20 on the inner wall of the opening 18.
To form Next, after a polycrystalline Si film is formed on the entire surface by, for example, a CVD method, an n-type impurity such as As is doped into the polycrystalline Si film by, for example, an ion implantation method. After that, the emitter electrode 21 is formed by patterning the polycrystalline Si film into a predetermined shape. The emitter electrode 21 is separated from the base electrode 17 by the sidewall 20.

Next, for example, by the CVD method,
After the insulating film 22 made of an O ₂ film is formed, a heat treatment is performed in an inert gas atmosphere such as N ₂ , so that the base electrode 17 and the underlying epitaxial layer 4
B, which is a p-type impurity, is diffused to form ap ⁺ -type graft base region 23 connected to the p-type base region 19 in this portion, and an n-type impurity is introduced from the emitter electrode 21 into the p-type base region 19. Is diffused, and an n ⁺ -type emitter region 24 is formed in this portion.

Next, BP is applied to the entire surface by, eg, CVD.
After the SG film 25 is formed, a heat treatment is performed to reflow the BPSG film 25 to perform a surface flattening process. Next, the BPSG film 25 and the insulating films 22, 16, 1
The connection holes 26 to 28 are formed by etching and removing a predetermined portion of No. 4. Next, after an Al film or an Al alloy film is formed on the entire surface by, for example, a sputtering method,
By patterning this into a predetermined shape, a base electrode wiring 29, an emitter electrode wiring 30, and a collector electrode wiring 31 are formed.

As described above, an intended high breakdown voltage npn transistor is formed above the epitaxial layer 4. As described above, the high breakdown voltage npn transistor has a high breakdown voltage of about 90 V or more because the thickness of the epitaxial layer 4 is 5 μm or more.

According to this first embodiment, the SiO ₂ film 2 and the Si ₃ N ₄ film 3 are sequentially stacked to form on the semiconductor substrate 1, these the Si ₃ N ₄ film 3 and SiO ₂ film 2
Is patterned into a predetermined shape to form a step on the surface of the semiconductor substrate 1, thereby forming SiO ₂ on the semiconductor substrate 1.
Since a convex alignment mark composed of a laminated film of the film 2 and the Si ₃ N ₄ film 3 is formed, the growth rate of the epitaxial layer 4 on the Si ₃ N ₄ film Taking advantage of the fact that the growth rate of the layer 4 is significantly reduced as compared with that of the
It can be selectively formed only on the exposed surface of the semiconductor substrate 1 so that it is hardly deposited on the ₃ N ₄ film 3. For this reason, even when the thickness of the epitaxial layer 4 is increased to 5 μm or more, the alignment mark formed on the semiconductor substrate 1 is transferred onto the surface of the epitaxial layer 4 in the same shape without distortion. Can be.

As a result, the following effects can be obtained. That is, in this method of manufacturing a semiconductor device, after the epitaxial layer 4 is formed, as shown in FIG.
The high breakdown voltage n is applied to the epitaxial layer 4 in the element forming region.
A pn transistor is formed. At this time, for example, n
A step of implanting impurities into the epitaxial layer 4 as in the step of forming the ⁺ type collector extraction region 13 and the step of forming the p-type base region 19, or
For example, a step of forming the opening 15 in the insulating film 14, a step of forming the opening 18 while forming the base electrode 17 by patterning the insulating film 16 and the polycrystalline Si film into a predetermined shape, and a step of forming the BPSG film 25 A step of forming connection holes 26 to 28 by etching and removing predetermined portions of insulating films 22, 16, 14, and a base electrode wiring 29 and an emitter electrode wiring by patterning an Al film or an Al alloy film into a predetermined shape. In a process of patterning an insulating film or a conductive film, such as a process of forming the gate electrode 30 and the collector electrode wiring 31, a resist pattern having a predetermined shape is used as an ion implantation mask or an etching mask. Each of these resist patterns is formed by patterning a resist film by a lithography method.

At this time, as described above, since the alignment mark formed on the surface of the semiconductor substrate 1 is transferred onto the surface of the epitaxial layer 4 without distortion, the alignment mark at the time of exposure is used in each lithography step. Can be performed with high accuracy, and misalignment can be reduced. Thereby, it is possible to improve the production yield of the high breakdown voltage npn transistor.

Next, the method for fabricating the semiconductor device according to the second embodiment of the present invention will be described. FIG. 5 shows a method of manufacturing the semiconductor device according to the second embodiment.

That is, in the method for manufacturing a semiconductor device, the SiO ₂ film 2 and the Si ₃ N ₄ film 3 formed on the semiconductor substrate 1 are similar to the method for manufacturing the semiconductor device according to the first embodiment. After patterning into a predetermined shape, the temperature is higher than that of the first embodiment by an epitaxial growth method, specifically, for example, 950 ° C. to 10 ° C.
The epitaxial layer 4 is formed at a temperature of 00 ° C. Thereby, as shown in FIG. 5, the epitaxial layer 4 is selectively formed on the exposed surface of the semiconductor substrate 1, and the polycrystalline Si film 41 is deposited on the Si ₃ N ₄ film 3. In this case, the surface of the polycrystalline Si film 41 is lower than the surface of the epitaxial layer 4, and a step is formed on the surface of the epitaxial layer 4. After the formation of the epitaxial layer 4, this step is used as an alignment mark.

Here, when forming the epitaxial layer 4, S
The reason why the polycrystalline Si film 41 is deposited on the i ₃ N ₄ film 3 is as follows.
For the following reasons. That is, in the method of manufacturing the semiconductor device, the temperature at the time of forming the epitaxial layer 4 is set to, for example, 950 ° C. to 1000 ° C., which is higher than that of the first embodiment (700 ° C. to 800 ° C.). ₃ growth rate of the epitaxial layer 4 in the N ₄ film 3 on the order to increase as compared with the case of the first embodiment, the film also on the the Si ₃ N ₄ film 3 is to deposit, S
Since the i ₃ N ₄ film 3 does not have a specific crystal orientation unlike the semiconductor substrate 1, the i ₃ N ₄ film 3 is deposited not as a single crystal film but as a polycrystalline film on the Si ₃ N ₄ film 3. Because you do.

The temperature at the time of forming the epitaxial layer 4 at this time is determined for the following reasons. That is, in order to form the polycrystalline Si film 41 on the Si ₃ N ₄ film 3 when forming the epitaxial layer 4,
What is necessary is just to make the temperature at the time of formation of the epitaxial layer 4 higher than in the case of the first embodiment. From this viewpoint, the temperature at the time of forming the epitaxial layer 4 is selected to be approximately 900 ° C. or higher, and preferably 950 ° C. or higher. On the other hand, when the epitaxial layer 4 is formed, the growth rate of the epitaxial layer 4 on the semiconductor substrate 1 and the polycrystalline Si on the Si ₃ N ₄ film 3
When the growth rate of the film 41 becomes substantially equal, the surface of the epitaxial layer 4 and the surface of the polycrystalline Si film 41 substantially coincide with each other, and it becomes difficult to recognize a step of the alignment mark in a subsequent step. From this viewpoint, the temperature at the time of forming the epitaxial layer 4 is selected to be approximately 1100 ° C. or lower, preferably 1000 ° C. or lower. As described above, the temperature at the time of forming the epitaxial layer 4 is 950 here.
C. to 1000.degree.

The other points are the same as those in the method of manufacturing the semiconductor device according to the first embodiment, and thus the description is omitted.

According to the second embodiment, in addition to the effect similar to that of the first embodiment, the amount of the epitaxial layer 4 is reduced by the amount of the polycrystalline Si film 41 deposited on the Si ₃ N ₄ film 3. There is an advantage that a step formed on the surface can be reduced.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values, materials, and the like described in the embodiments are merely examples, and the present invention is not limited thereto.

For example, in the first and second embodiments described above, the high breakdown voltage npn transistor is formed by using the epitaxial layer 4, but a pnp transistor may be formed instead of the npn transistor. Good. In addition, a high breakdown voltage MOS transistor may be formed in place of the high breakdown voltage bipolar transistor, or a high breakdown voltage bipolar transistor and a high breakdown voltage MOS transistor may be used.
A transistor and a transistor may be mounted together to form a high breakdown voltage BiCMOS integrated circuit. Further, a diode, a capacitor, a resistor, or the like may be formed in addition to the high withstand voltage transistor.

Further, for example, in the above-described first and second embodiments, the case where a Si substrate is used as a semiconductor substrate has been described as an example. However, the present invention provides a method in which an epitaxial layer is formed on a GaAs substrate, for example. The present invention can also be applied to a case where a GaAs substrate is used as a semiconductor substrate, such as a case where a semiconductor light emitting element is formed by using a semiconductor substrate.

[0037]

As described above, according to the present invention, an insulating film is formed on a semiconductor substrate, and the insulating film is patterned into a predetermined shape to form a step on the surface of the semiconductor substrate. Utilizing that a convex alignment mark made of an insulating film is formed on a semiconductor substrate, so that the growth rate of the epitaxial layer on the insulating film is significantly lower than the growth rate of the epitaxial layer on the semiconductor substrate. Thus, the epitaxial layer can be selectively formed only on the exposed surface of the semiconductor substrate while hardly being deposited on the insulating film. For this reason, even if the thickness of the epitaxial layer is increased, it is possible to transfer the alignment mark formed on the semiconductor substrate to the surface of the epitaxial layer in the same shape without distortion. Thereby, in the lithography process performed after the formation of the epitaxial layer, the misalignment at the time of exposure can be reduced. This also gives
The manufacturing yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

1 ... semiconductor substrate, ₂ ··· SiO 2 film, 3 ··· S
i ₃ N ₄ film, 4 ... epitaxial layer, 41 ... polycrystalline Si film

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device wherein an epitaxial layer is formed on a semiconductor substrate, comprising: forming an insulating film on the semiconductor substrate; and patterning the insulating film into a predetermined shape. Manufacturing a semiconductor device, comprising: a step of forming a step on the surface of the substrate; and a step of selectively forming the epitaxial layer on the surface of the semiconductor substrate not covered with the insulating film. Method. 2. The method according to claim 1, wherein said semiconductor substrate is a silicon substrate. 3. The semiconductor device according to claim 1, wherein said insulating film comprises a laminated film of a silicon dioxide film formed on said semiconductor substrate and a silicon nitride film formed on said silicon dioxide film. A method for manufacturing a semiconductor device. 4. The method according to claim 1, wherein the epitaxial layer is formed at a temperature of 700.degree.
2. The method according to claim 1, wherein the film is formed at a temperature of not more than 00.degree.
The manufacturing method of the semiconductor device described in the above. 5. The method according to claim 1, wherein the epitaxial layer is formed at 900 ° C. or higher.
The method according to claim 1, wherein the semiconductor device is formed at a temperature of 100 ° C. or less. 6. The method according to claim 1, wherein the epitaxial layer has a temperature of 950 ° C. or higher.
2. The method according to claim 1, wherein the semiconductor device is formed at a temperature of 000 ° C. or less. 7. The method according to claim 1, wherein said epitaxial layer has a thickness of 5 μm or more.