CN103698635B - The saturated A/D method of sampling based on high pressure static reactive power compensator - Google Patents
The saturated A/D method of sampling based on high pressure static reactive power compensator Download PDFInfo
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Abstract
The invention discloses a kind of saturated A/D method of sampling based on high pressure static reactive power compensator, comprise the following steps, 1), select the master cpu chip with successive approximation type a/d converter, as the main control chip of high pressure static reactive power compensator; 2), a sampling period, same sampled signal is carried out saturated sampling by master cpu chip; 3), the sampled data obtained is carried out unified management; 4) oscillogram of sampled signal, is described; 5), select all of invalid data in the oscillogram sampling interval, valid data in sampling period are carried out the discrete Fourier transform collection to periodic variable each in sampled signal, the valid data in the sampling period are carried out the root-mean-square computing each harmonic collection to comprising in sampled signal. The present invention adopts saturated sampling, and sampled data carries out unified management and computing, improves the precision of systematic sampling, reduces hardware cost, has a good application prospect.
Description
Technical field
The present invention relates to parameters of electric power technical field, be specifically related to a kind of saturated A/D method of sampling based on high pressure static reactive power compensator.
Background technology
In high pressure static reactive power compensator (SVC), sampling system occupies critical role, require that sampling system can be quickly, accurately catch the transient state characteristic of analog quantity, if sampling system adopts the special A/D conversion chip extended out, although can meet design requirement, but it is relatively costly, the producer of the current high pressure static reactive power compensator (SVC) produced is extremely many, Market competition, installation cost is reduced under the premise not sacrificing device performance, improve product competitiveness extremely necessary, then, how to reduce the production cost of high pressure static reactive power compensator, and the producer that the sampling precision not reducing sampling system is the current high pressure static reactive power compensator (SVC) produced needs the urgent problem solved.
Summary of the invention
The acquisition system that technical problem is that the high pressure static reactive power compensator overcoming prior art solved by the invention, adopts the special A/D conversion chip extended out, relatively costly, the problem of complex circuit designs.
In order to solve above-mentioned technical problem, the technical solution adopted in the present invention is:
The saturated A/D method of sampling based on high pressure static reactive power compensator, it is characterised in that: comprise the following steps,
Step (1), selects the master cpu chip with successive approximation type a/d converter, as the main control chip of high pressure static reactive power compensator;
Step (2), a sampling period, same sampled signal is carried out saturated sampling by master cpu chip;
Step (3), the sampled data obtained is carried out unified management by master cpu chip;
Step (4), according to the historical data gathered, describes the oscillogram of sampled signal;
Step (5), all of invalid data in the sampling interval is selected according to oscillogram, valid data in sampling period are carried out discrete Fourier transform and realizes the collection to periodic variable each in sampled signal, the valid data in the sampling period are carried out the root-mean-square computing realization each harmonic collection to comprising in sampled signal.
The aforesaid saturated A/D method of sampling based on high pressure static reactive power compensator, it is characterised in that: described master cpu chip is signal is STM32F103ZE, and inside carries 3 A/D converters.
The aforesaid saturated A/D method of sampling based on high pressure static reactive power compensator, it is characterised in that: described step (2) sampling period is 1/1200Hz, and the number of times of described saturated sampling is 32 times.
The aforesaid saturated A/D method of sampling based on high pressure static reactive power compensator, it is characterised in that: the process that the sampled data obtained is carried out unified management by described step (3) master cpu chip is,
(1) sampled point number in each sampling period is added up, it is thus achieved that the accurate sampling period, it is ensured that the maximum time error between the sampling period is within 1 sampling interval;
(2) ping-pong operation mode is adopted to store the sampled data in each sampling period;
(3) when the data amount check of storage is not up to saturated sampling number; for ensureing the correctness that data process; low speed data buffer module is in writes open, reading blocking; till not having new sampled data to be stored in data buffering module; low speed data buffer module enters write-protect, reads open state; repetitive cycling, it is achieved the master cpu chip unified management to gathering data.
The aforesaid saturated A/D method of sampling based on high pressure static reactive power compensator, it is characterized in that: the process that described ping-pong operation mode carries out storing is that data are stored in the first buffer module by first collection period, data are stored in the second buffer module by second collection period, the data of the first buffer module are transported to arithmetic element simultaneously, data are stored in the first buffer module by the 3rd collection period, the data of the second buffer module are transported to arithmetic element simultaneously, repetitive operation, realize the process to saturated sampling high speed data of the low speed data buffer module, described first buffer module and the second buffer module are low speed data buffer module.
The invention has the beneficial effects as follows: the saturated A/D method of sampling based on high pressure static reactive power compensator of the present invention, the A/D of 12, high speed SAR (Approach by inchmeal) type that selection master cpu chip carries, within a sampling period, carry out saturated sampling, sampled data is carried out unified management computing, improve the precision of systematic sampling, reduce hardware cost, have a good application prospect.
Accompanying drawing explanation
Fig. 1 is the flow chart of the saturated A/D method of sampling based on high pressure static reactive power compensator of the present invention.
The sampled data that Fig. 2 is the present invention adopts ping-pong operation mode to carry out the flow chart stored.
Detailed description of the invention
Below in conjunction with Figure of description, the present invention is further illustrated.
As it is shown in figure 1, based on the saturated A/D method of sampling of high pressure static reactive power compensator, it is characterised in that: comprise the following steps,
Step (1), select the master cpu chip with successive approximation type a/d converter, main control chip as high pressure static reactive power compensator, master cpu chip is signal is STM32F103ZE, inside carries 3 A/D converters, change the A/D converter of time 0.5us (system clock is 24MHz), device sample frequency is designed as 1200Hz, the A/D sampling interval is 833us, in an A/D sampling interval, analogue signal is carried out saturated sampling, namely same analogue signal is carried out 32 samplings, so the conversion time is at about 32x0.5=16us, well below the A/D sampling interval, again 32 sampled values are performed mathematical calculations, so under the premise keeping higher sample rate, improve the precision of sampling,
Step (2), a sampling period, same sampled signal is carried out saturated sampling by master cpu chip, and the sampling period is 1/1200Hz, and the number of times of described saturated sampling is 32 times;
Step (3), the sampled data obtained is carried out unified management by master cpu chip, manages process, as in figure 2 it is shown,
(1) sampled point number in each sampling period is added up, it is thus achieved that the accurate sampling period, it is ensured that the maximum time error between the sampling period is within 1 sampling interval;
(2) ping-pong operation mode is adopted to store the sampled data in each sampling period, the process that ping-pong operation mode carries out storing is that data are stored in the first buffer module by first collection period, data are stored in the second buffer module by second collection period, the data of the first buffer module are transported to arithmetic element simultaneously, data are stored in the first buffer module by the 3rd collection period, the data of the second buffer module are transported to arithmetic element simultaneously, repetitive operation, realize the process to saturated sampling high speed data of the low speed data buffer module, first buffer module and the second buffer module are low speed data buffer module,
(3) when the data amount check of storage is not up to saturated sampling number, for ensureing the correctness that data process, low speed data buffer module is in writes open, reading blocking, till not having new sampled data to be stored in data buffering module, low speed data buffer module enters write-protect, reads open state, repetitive cycling, it is achieved the master cpu chip unified management to gathering data;
Step (4), according to the historical data gathered, describes the oscillogram of sampled signal;
Step (5), all of invalid data in the sampling interval is selected according to oscillogram, valid data in sampling period are carried out discrete Fourier transform and realizes the collection to periodic variable each in sampled signal, the valid data in the sampling period are carried out the root-mean-square computing realization each harmonic collection to comprising in sampled signal.
Experiments verify that, high pressure static reactive power compensator adopts the above-mentioned method of sampling, reaches target, improves the precision of systematic sampling, reduces hardware cost, has a good application prospect.
The ultimate principle of the present invention and principal character and advantages of the present invention have more than been shown and described. Skilled person will appreciate that of the industry; the present invention is not restricted to the described embodiments; described in above-described embodiment and description is that principles of the invention is described; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements both fall within the claimed scope of the invention. Claimed scope is defined by appending claims and equivalent thereof.
Claims (3)
1. based on the saturated A/D method of sampling of high pressure static reactive power compensator, it is characterised in that: comprise the following steps,
Step (1), selects the master cpu chip with successive approximation type a/d converter, as the main control chip of high pressure static reactive power compensator;
Step (2), a sampling period, same sampled signal is carried out saturated sampling by master cpu chip;
Step (3), the sampled data obtained is carried out unified management by master cpu chip;
Step (4), according to the historical data gathered, describes the oscillogram of sampled signal;
Step (5), all of invalid data in the sampling interval is selected according to oscillogram, valid data in sampling period are carried out discrete Fourier transform and realizes the collection to periodic variable each in sampled signal, the valid data in the sampling period are carried out the root-mean-square computing realization each harmonic collection to comprising in sampled signal;
The process that the sampled data obtained is carried out unified management by described step (3) master cpu chip is,
(1) sampled point number in each sampling period is added up, it is thus achieved that the accurate sampling period, it is ensured that the maximum time error between the sampling period is within 1 sampling interval;
(2) ping-pong operation mode is adopted to store the sampled data in each sampling period;
(3) when the data amount check of storage is not up to saturated sampling number, for ensureing the correctness that data process, low speed data buffer module is in writes open, reading blocking, till not having new sampled data to be stored in data buffering module, low speed data buffer module enters write-protect, reads open state, repetitive cycling, it is achieved the master cpu chip unified management to gathering data;
The process that described ping-pong operation mode carries out storing is that data are stored in the first buffer module by first collection period, data are stored in the second buffer module by second collection period, the data of the first buffer module are transported to arithmetic element simultaneously, data are stored in the first buffer module by the 3rd collection period, the data of the second buffer module are transported to arithmetic element simultaneously, repetitive operation, realizing the process to saturated sampling high speed data of the low speed data buffer module, described first buffer module and the second buffer module are low speed data buffer module.
2. the saturated A/D method of sampling based on high pressure static reactive power compensator according to claim 1, it is characterised in that: described master cpu chip is signal is STM32F103ZE, and inside carries 3 A/D converters.
3. the saturated A/D method of sampling based on high pressure static reactive power compensator according to claim 1, it is characterised in that: described step (2) sampling period is 1/1200Hz, and the number of times of described saturated sampling is 32 times.
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| CN201060245Y (en) * | 2007-03-21 | 2008-05-14 | 辽宁荣信电力电子股份有限公司 | SVC signal generating device |
| CN202285332U (en) * | 2011-04-02 | 2012-06-27 | 中冶华天工程技术有限公司 | Reactive power compensation controller and low voltage dynamic reactive power compensation control device |
| CN102759675A (en) * | 2012-07-27 | 2012-10-31 | 深圳市中电软件有限公司 | On-line electric energy quality monitoring device |
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| JPH10174278A (en) * | 1996-12-05 | 1998-06-26 | Toshiba Corp | Electrical equipment |
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Patent Citations (3)
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| CN201060245Y (en) * | 2007-03-21 | 2008-05-14 | 辽宁荣信电力电子股份有限公司 | SVC signal generating device |
| CN202285332U (en) * | 2011-04-02 | 2012-06-27 | 中冶华天工程技术有限公司 | Reactive power compensation controller and low voltage dynamic reactive power compensation control device |
| CN102759675A (en) * | 2012-07-27 | 2012-10-31 | 深圳市中电软件有限公司 | On-line electric energy quality monitoring device |
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| STM32F103ZE应用手册;意法半导体(中国)投资有限公司;《http://www.st.com》;20100110 * |
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