CN204216884U

CN204216884U - A kind of device utilizing FPGA to form gradual approaching A/D converter

Info

Publication number: CN204216884U
Application number: CN201420570064.0U
Authority: CN
Inventors: 沈绍祥; 周斌; 方广有; 李玉喜; 花小磊
Original assignee: Institute of Electronics of CAS
Current assignee: Institute of Electronics of CAS
Priority date: 2014-09-29
Filing date: 2014-09-29
Publication date: 2015-03-18
Anticipated expiration: 2024-09-29

Abstract

The utility model discloses a kind of device utilizing FPGA to form gradual approaching A/D converter.Use the utility model can change remote measurement amount slowly collection to spaceborne multi way temperature, voltage, electric current etc., and can reduce costs easily, alleviate circuit weight, especially taking remote measurement to Multi-channel monitoring amount can miniaturized, lightweight, also the complexity of circuit is alleviated, low-power consumption, lightweight.

Description

A kind of device utilizing FPGA to form gradual approaching A/D converter

Technical field

The utility model relates to data acquisition technology field, is specifically related to a kind of device utilizing FPGA to form gradual approaching A/D converter.

Background technology

In data acquisition technology, generally have real-time sampling and the large sample mode of equivalent sampling two kinds to signal sampling, its sampling criterion all must meet the sampling thheorem of Shannon.As real-time sampling, increase with signal frequency, its sample rate requires high naturally, and especially in engineer applied, over-sampling is more.Equivalent sampling is then make use of signal (standard) periodic characteristics, and adopt low speed sample rate method to gather high-frequency signal, its efficiency is relatively low.These method of samplings all need, by hardware circuit analog to digital converter (being abbreviated as ADC), analog signal is converted to discrete digital signal, and wherein ADC is absolutely necessary a circuit devcie.

But in actual applications, the especially data collecting field of AEROSPACE APPLICATION, faces the restriction of many factors, as system the factor such as weight of equipment, power consumption, performance index, purchase channel and affect the feasibility of actual design scheme.

At present for the data acquisition system of AEROSPACE APPLICATION, an indispensable function is had to be then remote measurement to system mode, mainly comprise the remote measurement of the signals such as temperature, voltage, electric current, and these telemetered signals all there is similar feature: for slow variable signal maybe can think approximate DC signal.For the collection of these signals, in the past most rules of doing utilizes the scheme of multichannel low speed ADC or Port Multiplier+low speed ADC to complete the acquisition tasks of telemetered signal, and low speed ADC so is here essential.But the model that low speed ADC is applied to space industry is not difficult to obtain relatively, but face the problem of weight and power consumption equally.

Approach by inchmeal (being abbreviated as SAR) type ADC is a kind of ideal middling speed analog to digital converter, and its structure is simple, is easy to integration realization.Current the type transducer implementation method is two large classes mainly:

The first kind adopts existing process conditions, and advanced semiconductor technology improves the ADC of traditional SAR, and the direction of setting about improving mainly concentrates on precision, speed, power consumption three broad aspect.If number of patent application is CN102158231A, mainly consider to improve precision from chip design angle; Number of patent application is CN103166644 A, considers to reduce power consumption by improving chip area from integrated circuit (IC) design angle; Number of patent application is CN103152050 A and CN102832941 A, all considers to carry out hoisting velocity from integrated circuit (IC) design angle.The former directly realizes promoting from structure, and the latter mainly utilize can pre-detection method to reduce resetting time, thus hoisting velocity.This kind of improvement is and realizes single-chip integration SAR type ADC and effort, explores the lifting of three aspect performance index.

Equations of The Second Kind is then utilize existing device to realize the analog-digital conversion function circuit without integrated ADC form, and its thinking is equally by means of SAR ADC mode, and this mode is relatively flexible.Relatively be applicable to the occasion that weight, limited power consumption system are required.If number of patent application is CN 102457280A, be the I/O port utilizing MCU, realize A/D conversion in conjunction with PWM technology, solve the digitized process not adopting integrated ADC or V/F to convert of on-site supervision analog signal.The IO driving force of MCU is limited obviously, and formed PWM wave frequency and precision not high, not easily adjust, and multichannel extended capability is very limited.

The utility model is for overcoming above-mentioned Equations of The Second Kind defect, solves the application difficult problem to weight and power consumption constraints in data acquisition system better.Thus propose the device utilizing FPGA to form gradual approaching A/D converter.

The purpose of this utility model is the digitized process without ADC utilizing general-purpose device to solve analog signal, thus meet the restriction of weight, power consumption, reduce design cost, under especially comparatively harsh applied environment, when not easily obtaining corresponding integrated device advantageously.

Utility model content

In view of this, the utility model provides a kind of device utilizing FPGA to form gradual approaching A/D converter, remote measurement amount slowly collection can be changed to spaceborne multi way temperature, voltage, electric current etc., and lightweight, power consumption is little, expansion capability is good.

The device utilizing FPGA to form gradual approaching A/D converter of the present utility model, comprise monolithic FPGA and filter, wherein, comprise differential envelope detector circuit in monolithic FPGA, timer circuit, monobit digital sample circuit, logic judging circuit, reference comparison voltages arrange circuit, Delta-Sigma type DAC-circuit; Wherein, logic judging circuit comprises summer and multilevel iudge device; It is shift register that described reference comparison voltages arranges circuit;

Wherein, the termination in the same way of differential envelope detector circuit treats telemetered signal, the reference comparison voltages that its reverse termination filter exports, and its output is connected with the input of monobit digital sample circuit; The input of monobit digital sample circuit is also connected with timer circuit, and its output is connected with the input of the summer of logic judging circuit; The output of summer is connected with the input of multilevel iudge device, and the input that output and the reference comparison voltages of multilevel iudge device arrange circuit is connected; The output that reference comparison voltages arranges circuit is connected with the input of Delta-Sigma type DAC-circuit, the output of FPGA; The output of Delta-Sigma type DAC-circuit is connected with the input of filter.

Beneficial effect:

The utility model can reduce costs easily, alleviate circuit weight, and especially taking remote measurement to Multi-channel monitoring amount can miniaturized, lightweight, also alleviates the complexity of circuit, and low-power consumption, lightweight.

Accompanying drawing explanation

Fig. 1 is circuit block diagram of the present utility model.

Fig. 2 is the structured flowchart of FPGA internal build Delta-Sigma type DAC in the utility model device.

Wherein, 101-differential envelope detector circuit, 102-timer circuit, 103-monobit digital sample circuit, 104-logic judging circuit, 105-reference comparison voltages arranges circuit, 106-Delta-Sigma type DAC-circuit, 107-filter.

Embodiment

To develop simultaneously embodiment below in conjunction with accompanying drawing, the utility model is described in detail.

The utility model provides a kind of device utilizing FPGA to form gradual approaching A/D converter, as shown in Figure 1, be made up of monolithic FPGA, filter 107, wherein, comprise differential envelope detector circuit 101 in monolithic FPGA, timer circuit 102, monobit digital sample circuit 103, logic judging circuit 104, reference comparison voltages arrange circuit 105, Delta-Sigma type DAC-circuit 106.

Treat that the signals such as the temperature of remote measurement, voltage, electric current are connected to the end in the same way of the differential envelope detector circuit 101 of monolithic FPGA, filter 107 is RC filter circuit, and the reference comparison voltages that its filtering exports is connected to the backward end of differential envelope detector circuit 101.Treat that telemetered signal and reference comparison voltages compare on differential envelope detector circuit 101, the data flow forming single-bit exports monobit digital sample circuit 103 to.

The input of monobit digital sample circuit 103 is connected with the output of the output of differential envelope detector circuit 101, timer circuit 102, the output valve of monobit digital sample circuit 103 sampling should be carried out differential envelope detector circuit 101 when timer circuit 102 timing is overflowed, and output valve is transferred to logic judging circuit 104.

Wherein, logic judging circuit 104 comprises summer and multilevel iudge device, wherein the input of summer is connected with the output of monobit digital sample circuit 103, multi collect is done to the output valve of single-bit sample circuit 103 and collection result is accumulated, to add up and export multilevel iudge device to, multilevel iudge device will add up and compare judgement with the setting threshold self stored, determine that this quantized result is 0 or 1: when Cumulate Sum exceedes setting threshold, as 200, then determine that this single-bit transformation result is 1, otherwise be 0, and quantized result is exported to reference comparison voltages circuit 105 is set.

Reference comparison voltages value arranges the input of circuit 105 and is connected with the output of the multilevel iudge device of logic judging circuit 104, by this quantized result, the next comparing voltage value size of Approach by inchmeal, comparing voltage value is exported to Delta-Sigma type DAC, meanwhile, comparing voltage value also exports as the quantized result of FPGA.The rule that arranges that reference comparison voltages value arranges circuit 105 is: suppose that N bit width register is for preserving transformation result, initial setting N bit width register value is the half of reference voltage level full scale, namely the highest order of N bit width register is 1, other positions are 0, if highest order quantized value is 0, then think that signal input range is less than reference comparison voltages, the corresponding highest order of the register for preserving N bit width result should be set to 0, and can not get 1; If highest order quantized value is 1, then think that signal input range is greater than reference comparison voltages, the result that the corresponding highest order of the register for preserving N result is preset as 1 can retain.Then change to a time high position to do and quantize, first set a secondary high position for N bit register as 1, repeat one and take turns collection and compare.With this repeatedly, whole position has all been quantized.

The output that input and the reference comparison voltages of Delta-Sigma type DAC-circuit 106 arrange circuit 105 is connected, the output valve arranging circuit 105 with reference to comparative voltage is converted to analog output to filter 107, forms the backward end that required reference comparison voltages exports differential envelope detector circuit 101 to after filter 107 filtering.Delta-sigma type DAC-circuit 106 realizes the reference comparison voltages analogue value and exports, and its structured flowchart as shown in Figure 2.Carry out △ accumulation to the signed number certificate that the signless DAC data in N position and the N+2 position △ of input export, forming N+2 position has symbol Cumulate Sum.The signed number that should and export with N+2 position ∑ register is again accumulated according to doing ∑, and exporting N+2 position has symbol Cumulate Sum.Subsequently, ∑ Cumulate Sum is carried out one-level by register and deposits rear output.Final DAC gets this grade of register data highest order and exports, and device circuit 107 obtains required analog voltage after filtering, is fed back to the backward end of FPGA differential envelope detector circuit 101, thus forms reference comparison voltages.The N position quantized result of measured signal just can be obtained by arranging N reference comparison voltages.

Xilinx company aerospace level FPGA XQR2V3000 achieves 8,6 tunnel without ADC digital telemetry scheme, can digitlization be carried out for voltage, temperature and electric current.

The program relatively easily can be transplanted in other FPGA and realize, and the Delta-Sigma type DAC of its inside can directly adopt PWM mode to realize.

The utility model is expanded convenient, and FPGA many high-speed-differentials can be utilized to compare port, and periphery adds many group RC analog filters, is detected can complete multichannel expansion requirement by timesharing; Or realize Port Multiplier structure in FPGA inside, multiplexing FPGA other logical circuits inner form multichannel expansion.

In sum, these are only preferred embodiment of the present utility model, be not intended to limit protection range of the present utility model.All within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.

Claims

1. the device utilizing FPGA to form gradual approaching A/D converter, it is characterized in that, comprise monolithic FPGA and filter (107), wherein, comprise differential envelope detector circuit (101) in monolithic FPGA, timer circuit (102), monobit digital sample circuit (103), logic judging circuit (104), reference comparison voltages arrange circuit (105), Delta-Sigma type DAC-circuit (106); Wherein, logic judging circuit (104) comprises summer and multilevel iudge device; It is shift register that described reference comparison voltages arranges circuit;

Wherein, the termination in the same way of differential envelope detector circuit (101) treats telemetered signal, the reference comparison voltages that its reverse termination filter (107) exports, its output is connected with the input of monobit digital sample circuit (103); The input of monobit digital sample circuit (103) is also connected with timer circuit (102), and its output is connected with the input of the summer of logic judging circuit (104); The output of summer is connected with the input of multilevel iudge device, and the input that output and the reference comparison voltages of multilevel iudge device arrange circuit (105) is connected; The output that reference comparison voltages arranges circuit (105) is connected with the input of Delta-Sigma type DAC-circuit (106), the output of FPGA; The output of Delta-Sigma type DAC-circuit (106) is connected with the input of filter.