CN103684440B - Clock pulse and data recovery circuit and clock pulse and data recovery method - Google Patents
Clock pulse and data recovery circuit and clock pulse and data recovery method Download PDFInfo
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- CN103684440B CN103684440B CN201210323865.2A CN201210323865A CN103684440B CN 103684440 B CN103684440 B CN 103684440B CN 201210323865 A CN201210323865 A CN 201210323865A CN 103684440 B CN103684440 B CN 103684440B
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Abstract
The invention discloses a kind of clock pulse and data recovery circuit, comprising a sequence data input, for receiving a sequence data；One refers to clock input, and clock pulse is referred to for receiving one；One control circuit, for the clock pulse and data recovery circuit optionally are set in into one of multiple stages；One detection circuit, produces one second adjustment signal when operating in a clock pulse with the data recovery stage with data recovery circuit for the adjustment of generation one first signal when clock pulse and data recovery circuit operate in a Frequency Locking stage, and the clock pulse；And a controllable oscillator, for producing a recovered clock according to the first adjustment signal in the Frequency Locking stage, and in the clock pulse and data recovery stage the recovered clock produced according to the second adjustment signal.
Description
Technical field
The present invention is relevant to clock pulse and data recovery circuit, the clock pulse and data recovery circuit of espespecially a kind of multi-mode
(multi-mode clock and data recovery circuit) and associated method.
Background technology
In a communication system, receiving terminal needs to use clock pulse correctly to sample the letter received with data recovery circuit
Number, significantly raised with data volume however as the clock pulse of the system specification, and some systems, such as passive type fiberoptical networking
(passive optical network, PON) and gigabit passive type fiberoptical networking (Gigabit-capable passive
Optical network, GPON) require that receiving terminal completes the reply of clock pulse and data within the short time, it is existing to reach requirement
Some practices are that a voltage-controlled oscillator is used in a phase-locked loop come locking frequency to provide receiving terminal one local clock pulse,
And set a lock controlled oscillator to carry out quick lock in phase in addition, the lock controlled oscillator by with the voltage-controlled oscillator identical
Control voltage is controlled, and in Frequency Locking followed by locking phase at once.
Although two oscillators are controlled by identical control voltage, probably due to technique or other factors in practice
Influence and produce the mismatch in frequency each other, and make follow-up data recovery more difficult, or in extreme situation (for example
Consecutive identical bit (Consecutive Identical Digits, CIDs), that is, receive continuous compared with long number purpose 0 or
Continuous 1 sequence data) bit error rate (bit error rate, BER) is increased.
The content of the invention
The purpose of the present invention solves the above problems disclosing a kind of clock pulse and data recovery circuit and associated method.
Embodiments in accordance with the present invention, disclose a kind of clock pulse and data recovery circuit.The clock pulse and data recovery circuit bag
Containing a sequence data input, one with reference to clock input, a control circuit, a detection circuit and a controllable vibration
Device.The sequence data input is used for receiving a sequence data.This refers to clock pulse with reference to clock input for receiving one.The control
Circuit processed is used for producing a control signal that the clock pulse and data recovery circuit optionally are set in into multiple stages wherein
One of.The detection circuit is used for when the clock pulse and data recovery circuit operate in a Frequency Locking stage, depending at least on the ginseng
Clock pulse is examined to produce one first adjustment signal, and the clock pulse operates in a clock pulse and data recovery stage with data recovery circuit
When, one second adjustment signal is produced depending at least on the sequence data.The controllable oscillator is used for returning in the clock pulse and data
When compound circuit operates in the Frequency Locking stage, a recovered clock is produced according to the first adjustment signal, and the clock pulse with
When data recovery circuit operates in the clock pulse with the data recovery stage, the recovered clock is produced according to the second adjustment signal.
Embodiments in accordance with the present invention, separately disclose a kind of clock pulse and data recovery method.The clock pulse and data recovery method
Include：Receive a sequence data；Receive one and refer to clock pulse；When operating in a Frequency Locking stage, depending at least on the reference
Clock pulse produces a reply using a controllable oscillator to produce one first adjustment signal according to the first adjustment signal
Clock pulse；And when operating in a clock pulse with the data recovery stage, one second adjustment letter is produced depending at least on the sequence data
Number, and produce the recovered clock according to the second adjustment signal using the controllable oscillator.
In an embodiment, the controllable oscillator is a lock controlled oscillator.The clock pulse can divide three with data recovery circuit
The individual stage is respectively completed Frequency Locking, fast phase locking and clock pulse and data recovery, and its mode operated shares the lock
Controlled oscillator and the partial detection circuit, and switch using the control circuit circuit of common sparing to three phases
One of them.
In another embodiment, the controllable oscillator is a lock controlled oscillator.The clock pulse can divide with data recovery circuit
Three phases are locked and clock pulse and data recovery to be respectively completed Frequency Locking, set time fast phase, its side operated
Formula is to share the lock controlled oscillator and the partial detection circuit, and switches the circuit of common sparing using the control circuit
One of to three phases.
In another embodiment, it is a lock controlled oscillator that the controllable oscillator, which is not limited,.The clock pulse and data recovery electricity
Road can be respectively completed Frequency Locking and clock pulse and data recovery in two stages, and its mode operated is to share this can control
Oscillator and the partial detection circuit, and switched using the control circuit circuit of common sparing to two stages its
One of.
In the present invention, because phase-locked loop circuit and clock pulse and weakened phase restoring loop circuit share same controllable vibration
Device (such as lock controlled oscillator), therefore compared to the way of conventionally used two lock controlled oscillators, embodiments of the disclosure of the present invention
Unmatched risk each other and therefore caused ill effect may be occurred by eliminating two lock controlled oscillators.In addition, sharing
Detection circuit and oscillator can also reduce the hardware cost in implementation.
Brief description of the drawings
Fig. 1 is the schematic diagram of the first embodiment of clock pulse of the present invention and data recovery circuit.
Fig. 2 is the clock pulse and the timing diagram of multiple operational phases of data recovery circuit shown in Fig. 1.
Fig. 3 is the schematic diagram of the second embodiment of clock pulse of the present invention and data recovery circuit.
Fig. 4 is the schematic diagram of the 3rd embodiment of clock pulse of the present invention and data recovery circuit.
Wherein, description of reference numerals is as follows：
100th, 300,400 clock pulses and data recovery circuit；
102 sequence data inputs；
104 refer to clock input；
106th, 202,404 control circuit；
108 detection circuits；
110 lock controlled oscillators；
112 phase-locked loop lock detecting circuits；
114 clock pulse data recovery lock detecting circuits；
116th, 204,406 controller；
118 detection modules；
120 charge pumps；
122 loop filters；
123 frequency eliminators；
124 phase frequencies detect circuit；
126 phase detecting circuits；
128 multiplexers；
402 controllable oscillators.
Embodiment
In specification and apply for a patent and used some vocabulary among right requirement and censure specific element.Art
Middle technical staff is, it is to be appreciated that manufacturer may call same element with different nouns.This specification and application are special
Sharp right is come not in the way of the difference of title is used as differentiation element with the difference of element functionally
It is used as the criterion of differentiation.It is an open use in the "comprising" of specification in the whole text and follow-up claim mentioned in
Language, therefore " include but be not limited to " should be construed to.In addition, " coupling " one word directly and is indirectly electrically connected comprising any herein
Means.Therefore, if a first device is coupled to a second device described in text, representing the first device can directly be electrically connected
It is electrically connected indirectly to the second device in the second device, or by other devices or connection means.
Fig. 1 is refer to, Fig. 1 is the schematic diagram of the first embodiment of clock pulse of the present invention and data recovery circuit.The present embodiment
In, clock pulse includes a sequence data input 102, one with reference to clock input 104, a control with data recovery circuit 100
The detection lock controlled oscillator of circuit 108 and one of circuit 106, one (gated oscillator) 110.Sequence data input 102
A sequence data DIN (data to be decoded that the receiver of such as previous stage is received) is received, and is respectively coupled to control electricity
Road 106, detection circuit 108 and lock controlled oscillator 110.A reference clock pulse CLKREF is received with reference to clock input 104 (for example
Clock pulse produced by the quartz (controlled) oscillator of local side), and be respectively coupled to control circuit 106 and detect circuit 108.As schemed
Show, the input of control circuit 106 is respectively coupled to shake with reference to clock input 104, sequence data input 102 and lock control
The output end of device 110 is swung, and controls the output end of circuit 106 to be then respectively coupled to input and the lock control of detection circuit 108
The input of oscillator 110.Control circuit 106 includes a phase-locked loop lock detecting circuit (PLL locking
Detector) 112, a period of time arteries and veins data recovery lock detecting circuit (CDR locking detector) 114 and a controller
116。
The input of detection circuit 108 is respectively coupled to reference to clock input 104, sequence data input 102, control
The output end of circuit 106 and the output end of lock controlled oscillator 110, and detect the output end of circuit 108 and be then coupled to lock control and shake
Swing the input of device 110.As illustrated, detection circuit 108 includes a detection module 118, a charge pump 120, primary Ioops filter
The frequency eliminator 123 of ripple device 122 and one, wherein detection module 118 include phase frequency detection circuit 124, a phase-detection
The multiplexer 128 of circuit 126 and one.In addition, the input of lock controlled oscillator 110 is respectively coupled to sequence data input
102nd, the output end of control circuit 106 and the output end of detection circuit 108, and the output end of lock controlled oscillator 110 is then distinguished
It is coupled to the input of control circuit 106 and detects the input of circuit 108.
Fig. 2 is the clock pulse and the timing diagram of multiple operational phases of data recovery circuit shown in Fig. 1.It should be noted that this
Operation of the clock pulse disclosed with carrying out multi-mode among data recovery circuit using same set of hardware is invented, is described in detail as follows.
Three patterns in first embodiment of the invention are respectively a Frequency Locking stage, a PGC demodulation stage and a clock pulse and number
According to recovery stage.Performed by the Frequency Locking stage is phase-locked loop operation, in this stage, local side (that is, receiving terminal)
A reception clock pulse can be produced, performed by the follow-up PGC demodulation stage is quick lock in operation, in this stage, lock control vibration
Device 110 can rapidly adjust the phase of the reception clock pulse.Finally, performed by clock pulse and data recovery stage it is clock pulse and data
Circuit operation is replied, in this stage, the phase-locked loop in Frequency Locking stage can be by appropriate switching and configuration is formed again
For clock pulse and data recovery loop.
Furthermore, it is understood that when clock pulse and data recovery circuit 100 were operated in the Frequency Locking stage, (i.e. clock pulse is returned with data
The initial operational condition of compound circuit 100) when can be considered as a phase-locked loop circuit, under the Frequency Locking stage, detect circuit
Multiplexer 128, charge pump 120 and loop filter 122 in 108 is by one exported from control circuit 106
Control signal SCTRL control and phase frequency can be detected circuit by the configuration of dynamic adjustment itself, such as multiplexer 128
A first detection signal SD1 produced by 124 is exported to charge pump 120.In general, one produced by lock controlled oscillator 110
Recovered clock CLKRCV frequency can be higher than the frequency with reference to clock pulse CLKREF, and therefore, frequency eliminator 123 can be based on a predetermined value
By frequency elimination recovered clock CLKRCV to produce a feedback clock pulse CLKFB, and phase frequency detection circuit 124 is for that will feed back
Clock pulse CLKFB comes out with the difference reaction with reference to clock pulse CLKREF, and charge pump 120 is produced one first charge pump output letter
Number SC1 is exported to loop filter 122.In addition, whether frequency eliminator 123 can be chosen to implement (optional), and phase frequency
Rate detection circuit 124 is for being come out recovered clock CLKRCV with referring to clock pulse CLKREF difference reaction, and making charge pump
120 produce the first charge pump output signal SC1 to export to loop filter 122.Summary, phase frequency detection circuit
124 can be according to (direct with reference to recovered clock CLKRCV or by feeding back clock pulse with reference to clock pulse CLKREF and recovered clock CLKRCV
CLKFB and indirect reference recovered clock CLKRCV) produce first detection signal SD1.
Loop filter 122 is coupled between charge pump 120 and lock controlled oscillator 110, and can be considered a low pass filter,
Its purposes is mainly to reduce charge pump output signal SC1 high frequency noise components, and one first that loop filter 122 is exported
Adjustment signal SLF1 is the output signal for detecting circuit 108 in the Frequency Locking stage.In the Frequency Locking stage, lock control
Oscillator 110 is only a controllable oscillator, and can dynamically change exported reply according to the first adjustment signal SLF1
Clock pulse CLKRCV frequency.(phase-locked loop output frequency is locked in required when lock-out state is presented in phase-locked loop
Frequency), the one first lock detecting signal SL1 for controlling the phase-locked loop lock detecting circuit 112 in circuit 106 to export will be such as figure
1 is upgraded to by 0 shown in 2, represents that phase-locked loop lock detecting circuit 112 judges that frequency now is locked, and controller 116 is exported
The control signal SCTRL output of circuit 106 (that is, control) change can be made simultaneously accordingly to control to detect circuit 108
With gate oscillator 110, in other words, the Frequency Locking stage has completed and has entered the follow-up PGC demodulation stage.
When clock pulse and data recovery circuit 100 are operated in the PGC demodulation stage (i.e. clock pulse in first embodiment of the invention
With second mode of operation of data recovery circuit 100) when, the control signal SCTRL that control circuit 106 is exported can suspend inspection
The action of slowdown monitoring circuit 108, and the phase rapidly lock sequence number for the recovered clock CLKRCV that lock controlled oscillator 110 is exported
According to DIN phase, when now controlling the clock pulse data recovery lock detecting circuit 114 in circuit 106 dynamically can check reply
Relativeness between arteries and veins CLKRCV and sequence data DIN, has been locked once clock pulse data recovery lock detecting circuit 114 is assert
Into its one second lock detecting signal SL2 exported will be upgraded to 1 by 0 as shown in Figure 2, and the control that controller 116 is exported is believed
Number SCTRL (that is, output of control circuit 106) can make change simultaneously accordingly to control detection circuit 108 and gate to shake
Device 110 is swung, in other words, the PGC demodulation stage has completed and entered the follow-up clock pulse and data recovery stage.
When clock pulse and data recovery circuit 100 are operated in the clock pulse and data recovery stage (i.e. first embodiment of the invention
3rd mode of operation of middle clock pulse and data recovery circuit 100) when can be considered as a clock pulse and data recovery circuit, at this
Under arteries and veins and data recovery stage, multiplexer 128, charge pump 120 and loop filter 122 in detection circuit 108 by
To the configuration from the control of a control signal SCTRL that control circuit 106 is exported and dynamic adjustment itself, such as multichannel is answered
One second detection signal SD2 produced by phase detecting circuit 126 can be exported with device 128 to charge pump 120, it should be noted that
It is, as it was previously stated, the frequency of the recovered clock CLKRCV produced by lock controlled oscillator 110 can be higher than the frequency with reference to clock pulse CLKREF
Rate, therefore, frequency eliminator 123 can produce feedback clock pulse based on a predetermined value to recovered clock CLKRCV progress frequency eliminations
CLKFB, and phase detecting circuit 126 is used for coming out the difference reaction for feeding back clock pulse CLKFB and sequence data DIN, and make
Charge pump 120 produces one second charge pump output signal SC2 to export to loop filter 122, similarly, in other application or
In implementation, whether frequency eliminator 123 can be chosen to implement, therefore, and phase detecting circuit 126 is for by recovered clock
CLKRCV and sequence data DIN difference reaction come out, and it is next charge pump 120 is produced the second charge pump output signal SC2
Export to loop filter 122.Sum it up, phase detecting circuit 124 can be according to sequence data DIN and recovered clock CLKRCV
(directly with reference to recovered clock CLKRCV or by feeding back clock pulse CLKFB and indirect reference recovered clock CLKRCV) produces second
Detect signal SD2.Loop filter 122 can be considered a low pass filter, and its purposes is mainly to reduce charge pump output signal SC2
High frequency noise components, now loop filter 122 exported one second adjustment signal SLF2 be detection circuit 108 when
Arteries and veins and the output signal in data recovery stage.In the clock pulse and the data recovery stage, lock controlled oscillator 110 acts as this
The Frequency Locking stage and as a simple controllable oscillator, and can be according to the second adjustment signal SLF2 to dynamically change
The recovered clock CLKRCV of output frequency.Due to clock pulse and data recovery circuit 100 terminate in the PGC demodulation stage when
The locking for having completed phase is waited, therefore in the ensuing clock pulse and data recovery stage, clock pulse and data recovery loop
Can stably it follow the trail of and lock sequence data DIN.
In some systems, such as gigabit passive type fiberoptical networking, in PGC demodulation stage (i.e. above-mentioned phase
Locked stage) under sequential column data DIN be one continuous 0,1 conversion adjustment sequence (training sequence), and require
Clock pulse will complete PGC demodulation with data recovery circuit within 25 bit times.Because lock controlled oscillator just has originally
There is the characteristic of quick lock in, locking in general can be completed in a bit time, therefore disclosed one second is real
Apply in example, can further remove the clock pulse data recovery lock detecting circuit 114 in first embodiment of the invention, coupled system rule
Model and make into using the locking time fixed, and after the locking time Jing Guo the fixation, automatically by PGC demodulation rank
Section switches to clock pulse and data recovery stage.
Fig. 3 is refer to, Fig. 3 is the schematic diagram of the second embodiment of clock pulse of the present invention and data recovery circuit.The present embodiment
In, clock pulse includes a control circuit 202 with above-mentioned sequence data input 102, with reference to clock pulse with data recovery circuit 300
Input 104, detection circuit 108 and lock controlled oscillator 110.Clock pulse and data recovery circuit 300 and clock pulse and data recovery
The difference of circuit 100 is to control circuit 202 to include a controller 204 and foregoing phase-locked loop lock detecting circuit
112, and clock pulse data recovery lock detecting circuit 114 is not included.
Frequency Locking in the operation and first embodiment of the invention in the Frequency Locking stage in second embodiment of the invention
The operation in stage is identical, and after the Frequency Locking stage is terminated, clock pulse can equally enter a phase with data recovery circuit 300
Position locked stage, and the set time in PGC demodulation stage one (such as 25 bit time) is rested on, for example, controller
204 can be used a counter when having met the set time, actively send control signal SCTRL to control clock pulse to return with data
Compound circuit 300 switches to a clock pulse and data recovery stage by the PGC demodulation stage.However, controlling phase using counter
Locked stage is only example with clock pulse and the switching in data recovery stage, and the restrictive condition of non-invention is any to reach class
Like the design of function, belong to the scope that the present invention is covered.In addition, the clock pulse and data recovery in second embodiment of the invention
Clock pulse in stage and first embodiment of the invention is identical with the data recovery stage.The function of controller 204 and operation class
Function and the operation of controller 110 are similar to, difference is that controller 204 can voluntarily control clock pulse and number after a preset time
Clock pulse and data recovery stage are switched to by the PGC demodulation stage according to reflex circuit 300, locked without reference to clock pulse data recovery
The second lock detecting signal SL2 that detection circuit 114 is provided.Those skilled in the art, it should be appreciated that clock pulse shown in Fig. 3 with
The details of operation of data recovery circuit 300, therefore omit and carefully state.
Fig. 4 is refer to, Fig. 4 is the schematic diagram of the 3rd embodiment of clock pulse of the present invention and data recovery circuit.The present embodiment
In, clock pulse includes a controllable control circuit 404 of oscillator 402, one and above-mentioned sequence data with data recovery circuit 400
Input 102, with reference to clock input 104, detection circuit 108 and controllable oscillator 402.In the present embodiment, it can control
Oscillator 402 is not necessarily lock controlled oscillator, and controls circuit 404 to be locked comprising a controller 406 and above-mentioned phase-locked loop
Detect circuit 112.
Due to the clock pulse in first and second embodiment and data recovery stage (i.e. clock pulse and data recovery pattern) tool
There is the function of PGC demodulation, simply PGC demodulation speed in an initial condition is fast not as lock controlled oscillator, and general
If system in without the strict data recovery speed of specification, it is not absolutely required to use lock controlled oscillator in practice, implying that can
To be directly entered the pattern of clock pulse and data recovery circuit after Frequency Locking.For example, with controllable damping in 3rd embodiment
Swing device 402 and replace lock controlled oscillator 110 in the present invention first and second embodiment, and the Frequency Locking in the present embodiment
The operation in stage is identical with the operation in the Frequency Locking stage in the present invention first and second embodiment, and is terminating to be somebody's turn to do
After the Frequency Locking stage, controller 406 can according to the first lock detecting signal SL1 of phase-locked loop lock detecting circuit 112 come
Control clock pulse and data recovery circuit 400 are directly entered a clock pulse and data recovery stage, and the clock pulse and data recovery stage
Operation and of the invention first and second embodiment in clock pulse it is identical with the operation in data recovery stage.This area skill
Art personnel should be appreciated that the details of operation of the clock pulse and data recovery circuit 400 shown in Fig. 4, therefore omit and carefully state.
It note that the charge pump 120 in above-described embodiment separately can dynamically adjust charge pump according to control signal SCTRL
Configuration.For example, compared to the Frequency Locking stage, charge pump 120 has different circuit frameworks in clock pulse from the data recovery stage
Or there is different element characteristics (such as different resistance values and/or capacitance) under same circuit framework.Similarly,
Loop filter 122 in above-described embodiment also can dynamically adjust the configuration of loop filter, example according to control signal SCTRL
Such as, compared to the Frequency Locking stage, loop filter 122 can have in clock pulse and data recovery stage different circuit framework or
Person has different element characteristics (such as different resistance values and/or capacitance) under same circuit framework.
Moral embodiment of the present invention is the foregoing is only, all equivalent changes done according to scope of the present invention patent are with repairing
Decorations, should all belong to the covering scope of the claims in the present invention.
Claims (13)
1. a kind of clock pulse and data recovery circuit, include：
One sequence data input, for receiving a sequence data；
One refers to clock input, and clock pulse is referred to for receiving one；
One control circuit, optionally a frequency is set in for producing a control signal by the clock pulse and data recovery circuit
Locked stage, a PGC demodulation stage or one of a clock pulse and data recovery stage；
One detection circuit, for when the clock pulse and data recovery circuit operate in a Frequency Locking stage, depending at least on the ginseng
Clock pulse is examined to produce one first adjustment signal, and a clock pulse and data recovery rank are operated in the clock pulse and data recovery circuit
Duan Shi, one second adjustment signal is produced depending at least on the sequence data；And
One controllable oscillator, for when the clock pulse and data recovery circuit operate in the Frequency Locking stage, according to this
One adjustment signal operates in the clock pulse and data recovery rank to produce a recovered clock, and in the clock pulse and data recovery circuit
Duan Shi, the recovered clock is produced according to the second adjustment signal；
The input of the wherein control circuit be respectively coupled to this with reference to clock input, the sequence data input and this can
Control the output end of oscillator, the output end of the control circuit is respectively coupled to the input of the detection circuit and this is controllable
The input of oscillator；
Wherein the control circuit is included：
One phase-locked loop lock detecting circuit, for producing one first locking inspection with reference to clock pulse and the recovered clock according to this
Survey signal；And
One controller, is coupled to the phase-locked loop lock detecting circuit, for producing this according to first lock detecting signal
Control signal, to control the clock pulse and data recovery circuit to switch to a PGC demodulation stage by the Frequency Locking stage；
Wherein when the recovered clock refers to the Frequency Locking of clock pulse with this, the control signal of the control circuit output can be made simultaneously
Go out to change accordingly to control the detection circuit and the controllable oscillator, suspend the action of the detection circuit and make this can
The recovered clock that control oscillator is exported locks the phase of the sequence data；
Wherein the controllable oscillator is a lock controlled oscillator, and when the clock pulse and data recovery circuit operate in the phase
During locked stage, the lock controlled oscillator receives the sequence data and makes the phase of the recovered clock according to the sequence data with being somebody's turn to do
The Phase synchronization of sequence data.
2. clock pulse as claimed in claim 1 and data recovery circuit, wherein the control circuit are additionally comprised：
A period of time arteries and veins data recovery lock detecting circuit, for producing one second lock according to the sequence data and the recovered clock
Regular inspection surveys signal；
Wherein the controller is another produces the control signal according to second lock detecting signal, to control the clock pulse to be returned with data
Compound circuit switches to the clock pulse and data recovery stage by the PGC demodulation stage.
3. clock pulse as claimed in claim 1 and data recovery circuit, wherein the detection circuit include：
One detection module, for when the clock pulse and data recovery circuit operate in the Frequency Locking stage, when being referred to according to this
Arteries and veins produces a first detection signal with the recovered clock, and operates in the clock pulse and number in the clock pulse and data recovery circuit
During according to recovery stage, one second detection signal is produced according to the sequence data and the recovered clock；
One charge pump, is coupled to the detection module, for operating in the Frequency Locking stage in the clock pulse and data recovery circuit
When, one first charge pump output signal is produced according to the first detection signal, and grasp in the clock pulse and data recovery circuit
When making in the clock pulse with the data recovery stage, one second charge pump output signal is produced according to the second detection signal；And
Loop filter, is coupled between the charge pump and the controllable oscillator, in the clock pulse and data recovery
Circuit operation produces the first adjustment signal according to first charge pump output signal when Frequency Locking stage, and
When the clock pulse and data recovery circuit operate in the clock pulse with the data recovery stage, come according to second charge pump output signal
Produce the second adjustment signal.
4. clock pulse as claimed in claim 3 and data recovery circuit, the wherein charge pump carry out dynamic further accordance with the control signal
Adjust a configuration of the charge pump.
5. clock pulse as claimed in claim 3 and data recovery circuit, the wherein loop filter come further accordance with the control signal
Dynamic adjusts a configuration of the loop filter.
6. clock pulse as claimed in claim 3 and data recovery circuit, the wherein detection module include：
One phase frequency detects circuit, for producing the first detection signal with reference to clock pulse and the recovered clock according to this；
One phase detecting circuit, for producing the second detection signal according to the sequence data and the recovered clock；And
One multiplexer, is coupled to phase frequency detection circuit and the phase detecting circuit, in the clock pulse and data
When reflex circuit operates in the Frequency Locking stage, the first detection signal is exported to the charge pump, and in the clock pulse and number
When operating in the clock pulse with the data recovery stage according to reflex circuit, the second detection signal is exported to the charge pump.
7. clock pulse as claimed in claim 1 and data recovery circuit, wherein the phase-locked loop lock detecting circuit, also for root
According to this lock detecting signal is produced with reference to clock pulse and the recovered clock；And
The controller, is coupled to the phase-locked loop lock detecting circuit, also to produce the control according to the lock detecting signal
Signal processed, to control the clock pulse and data recovery circuit to switch to the clock pulse and data recovery stage by the Frequency Locking stage.
8. a kind of clock pulse and data recovery method, include：
Receive a sequence data；
Receive one and refer to clock pulse；
When operating in a Frequency Locking stage, adjusted using a detection circuit depending at least on this with reference to clock pulse to produce one first
Signal, and produce a recovered clock according to the first adjustment signal using a controllable oscillator；And
When operating in a clock pulse and data recovery stage, one the is produced depending at least on the sequence data using the detection circuit
Two adjustment signals, and produce the recovered clock according to the second adjustment signal using the controllable oscillator；
When the recovered clock refers to the Frequency Locking of clock pulse with this, the control signal of a control circuit output can make simultaneously to be changed
Become accordingly to control the detection circuit and the controllable oscillator, suspend the action of the detection circuit and can control this
The recovered clock that oscillator is exported locks the phase of the sequence data；
One first lock detecting signal is produced with reference to clock pulse and the recovered clock according to this；
Control to switch to a PGC demodulation stage by the Frequency Locking stage according to first lock detecting signal；
Wherein the controllable oscillator additionally comprises for a lock controlled oscillator, and this method：
When operating in the PGC demodulation stage, the sequence data is received using the lock controlled oscillator and according at least to the sequence
Data are so that the phase and the Phase synchronization of the sequence data of the recovered clock.
9. clock pulse as claimed in claim 8 and data recovery method, are additionally comprised：
One second lock detecting signal is produced according to the sequence data and the recovered clock；And
Control to switch to the clock pulse and data recovery stage by the PGC demodulation stage according to second lock detecting signal.
10. clock pulse as claimed in claim 8 and data recovery method, wherein at least according to this with reference to clock pulse come produce this first
The step of adjustment signal, includes：
According to this first detection signal is produced with reference to clock pulse and the recovered clock；
One first charge pump output signal is produced according to the first detection signal using a charge pump；And
The first adjustment signal is produced according to first charge pump output signal using loop filter；And
The step of the second adjustment signal is produced depending at least on the sequence data includes：
One second detection signal is produced according to the sequence data and the recovered clock；
Using the charge pump one second charge pump output signal is produced according to the second detection signal；And
The second adjustment signal is produced according to second charge pump output signal using the loop filter.
11. clock pulse as claimed in claim 10 and data recovery method, are additionally comprised：
Dynamic adjusts a configuration of the charge pump.
12. clock pulse as claimed in claim 10 and data recovery method, are additionally comprised：
Dynamic adjusts a configuration of the loop filter.
13. clock pulse as claimed in claim 8 and data recovery method, are additionally comprised：
One lock detecting signal is produced with reference to clock pulse and the recovered clock according to this；And
Control to switch to the clock pulse and data recovery stage by the Frequency Locking stage according to the lock detecting signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210323865.2A CN103684440B (en) | 2012-09-04 | 2012-09-04 | Clock pulse and data recovery circuit and clock pulse and data recovery method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210323865.2A CN103684440B (en) | 2012-09-04 | 2012-09-04 | Clock pulse and data recovery circuit and clock pulse and data recovery method |
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| CN103684440A CN103684440A (en) | 2014-03-26 |
| CN103684440B true CN103684440B (en) | 2017-10-27 |
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|---|---|---|---|---|
| TWI533608B (en) * | 2014-06-30 | 2016-05-11 | 友達光電股份有限公司 | Data receiver and data receiving method thereof |
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