CN103680383A - Display driver integrated circuit, display system and display data processing method - Google Patents
Display driver integrated circuit, display system and display data processing method Download PDFInfo
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Abstract
A display driver integrated circuit comprises: a distributor configured for outputting and displaying data; a plurality of first-in-first-out (FIFO) memories configured to receive display data from the distributor according to an outside clock and to output the display data according to an inner clock; a plurality of pattern memories configured to receive the display data from the FIFO memories.
Description
The cross reference of related application
The application requires to be submitted on September 24th, 2012 right of priority of No. 10-2012-0105823rd, the korean patent application of Korea S Department of Intellectual Property, and its open integral body is by reference incorporated into this.
Technical field
The present invention's design relates to display-driver Ics, comprises display system and the data display processing method thereof of this display-driver Ics.
Background technology
Along with comprising the appearance of smart mobile phone of the super-resolution display apparatus module of HDTV (HDTV) type, may need to use organic light emitting display (OLED) and/or low temperature polycrystalline silicon liquid crystal display (LTPS-LCD) technology, widescreen XGA (Extended Graphics Array) (WXGA) (800x1280) or the super-resolution mobile display driver IC (DDI) of full HD type (1080x1920).When super-resolution mobile display is driven, consider the current drain, heat and the burden that reduce application processor (AP), DDI may necessitate for the various solutions that drive for low-power.
In addition the data volume of transmitting between DDI and cmos image sensor (CIS) and mobile AP by HSSI High-Speed Serial Interface (HSSI), can increase to tackle the super-resolution such as full HD.Therefore, may exist for the needs with the DDI of high-speed driving ability.
Summary of the invention
The one exemplary embodiment of the present invention's design provides a kind of display-driver Ics (DDI), comprising: divider, and it is configured to output display data; A plurality of first in first out (FIFO) storer, it is configured to according to external clock from divider reception demonstration data and in response to internal clocking output display data; With a plurality of graphic memories, it is configured to receive and show data from FIFO storer.
The frequency of internal clocking is higher than the frequency of external clock.
Divider receives and shows data with first frequency.
Demonstration data are exported from divider with second frequency, and wherein second frequency is equal to or higher than divided by the first frequency after the quantity of FIFO storer.
Demonstration data are with the 3rd frequency from the output of FIFO storer, and wherein the 3rd frequency is higher than second frequency and lower than first frequency.
Demonstration data are with the 3rd frequency from the output of FIFO storer, and wherein the 3rd frequency equals the frequency of internal clocking.
The quantity of FIFO storer equals the quantity of graphic memory.
Divider receives and shows data via HSSI High-Speed Serial Interface.
Divider receives demonstration data with the frequency of 125MHz.
DDI also comprises the oscillator that is configured to generate internal clocking.
The one exemplary embodiment of the present invention's design provides DDI, comprising: divider, and it is configured to output display data; A plurality of FIFO storeies, it is configured to receive and show data and output display data from divider; With a plurality of graphic memories, it is configured in response to internal clocking from FIFO storer reception demonstration data and in response to internal clocking output display data.
Show that the data based enable signal of writing that is positioned at the rising edge of internal clocking is received at graphic memory.
Show that the data based scan enable signals that is positioned at the negative edge of internal clocking exports from graphic memory.
DDI also comprises and is configured to control the time schedule controller write enable signal and scan enable signals.
At graphic memory, receive and show that data frequency used is with identical from graphic memory output display data frequency used.
Show that data based external clock is received by FIFO storer, and demonstration data are exported from FIFO storer in response to internal clocking.
The frequency of internal clocking is higher than the frequency of external clock.
Graphic memory does not comprise arbitration circuit.
DDI also comprises the oscillator that is configured to generate internal clocking.
Each of graphic memory has corresponding FIFO storer.
The one exemplary embodiment of the present invention's design provides DDI, comprising: divider, and it is configured to output display data; A plurality of FIFO storeies, it is configured to receive and show data from divider; With a plurality of graphic memories, it is configured to receive and show data from FIFO storer, and wherein every a pair of the and corresponding graphic memory of FIFO storer centering is to sharing data line.
FIFO storer receive to show data with first frequency from divider, and with second frequency via data line output display data, wherein second frequency is higher than first frequency.
FIFO storer receives and shows data from divider according to external clock, and in response to internal clocking output display data.
Graphic memory receives and shows data from FIFO storer in response to internal clocking.
The one exemplary embodiment of the present invention's design provides the data processing method of DDI, comprising: according to external clock, the demonstration data from divider are write to a plurality of FIFO storeies; In response to internal clocking, the demonstration data from FIFO storer are write to a plurality of graphic memories; And in response to internal clocking by the demonstration data scanning of graphic memory to view data processing block.
Accompanying drawing explanation
By reference to accompanying drawing, describe the one exemplary embodiment of the present invention's design in detail, the above and further feature of the present invention's design will become clearer.
Fig. 1 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.
Fig. 2 is the figure that the packet of the one exemplary embodiment of design according to the present invention is shown.
Fig. 3 is the display timing generator figure of the one exemplary embodiment of design according to the present invention.
Fig. 4 A is the figure that the input of mobile industry processor interface (MIPI) data of the one exemplary embodiment of design according to the present invention is shown.
Fig. 4 B is the figure that the input of the MIPI data of the one exemplary embodiment of design according to the present invention is shown.
Fig. 5 is the diagram that the display-driver Ics (DDI) of the one exemplary embodiment of design according to the present invention is shown.
Fig. 6 is the one exemplary embodiment of the design according to the present invention, and the figure of the write operation of each graphic memory in Fig. 5 and the sequential of scan operation is shown.
Fig. 7 is the figure that the sequential of the data when carrying out the interweaving of one exemplary embodiment of the design according to the present invention is shown.
Fig. 8 A is the figure interweaving that the divider of the one exemplary embodiment of design according to the present invention is shown.
Fig. 8 B is the figure interweaving that the divider of the one exemplary embodiment of design according to the present invention is shown.
Fig. 9 A is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.
Fig. 9 B is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.
Figure 10 is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.
Figure 11 is the block diagram that the mobile DDI of the one exemplary embodiment of design according to the present invention is shown.
Figure 12 is the process flow diagram that the data display processing method of the one exemplary embodiment of design according to the present invention is shown.
Figure 13 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.
Figure 14 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.
Embodiment
After this, with reference to accompanying drawing, describe the one exemplary embodiment of the present invention's design in detail.Yet the present invention design can be with various form specific implementation, and should not be understood to be limited in the embodiment setting forth here.Run through drawing and description, similar reference number can refer to similar element.
Fig. 1 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 1, display system 10 can comprise application processor (following, can be called " AP ") 12, display-driver Ics (following, can to become " DDI ") 14 and display panel 16.
AP12 can control the overall operation of display system 10.AP12 can be in response to clock ECLK input and output packet, and wherein each packet has demonstration data.Here, packet can comprise show data, horizontal-drive signal Hsync, vertical synchronizing signal Vsync, data enable signal DE, etc.
DDI14 can receive packet from AP12 by mobile interface, and can export horizontal-drive signal Hsync, vertical synchronizing signal Vsync, data enable signal DE, demonstration data RGB data, clock PCLK.Here, described mobile interface can be HSSI High-Speed Serial Interface, such as the advanced difference signaling (CMADS) of mobile industry processor interface (MIPI), mobile display digital interface (MDDI), compact display port (CDP), mobile pixel link (MPL), current-mode, etc.In one exemplary embodiment below, suppose that DDI14 carries out interface operation according to MIPI.
DDI14 can comprise the graphic memory (for example, graphics random access storer (GRAM)) for HSSI High-Speed Serial Interface.Here, GRAM can be used for reducing current drain, heat and the burden of AP12.GRAM can be configured to write the demonstration data from AP12 input, and by scan operation, exports the data that write.In an exemplary embodiment, GRAM can be dual-port dynamic RAM (DRAM).
DDI14 can be configured to not comprise the graphic memory for HSSI High-Speed Serial Interface.In this case, DDI14 can divide into groups so that output display data by buffered data.In one exemplary embodiment below, suppose that DDI14 is used GRAM.
By comprising the DDI14 that uses GRAM, display system 10 can be for high-speed interface.
Fig. 2 is the figure that the packet of the one exemplary embodiment of design according to the present invention is shown.In Fig. 2, packet can be to be presented at the data on display panel 16 by horizontal direction.Packet is divided into groups and horizontal forward position (HFP) grouping along (HBP) grouping, horizontal anomalous movement (HACT) after can comprising horizontal velocity action (HSA) grouping, level.Yet the packet of the present invention's design is not limited to this.
DDI14(is with reference to figure 1) can receive the packet that will show by horizontal direction to export data enable signal DE, horizontal-drive signal Hsync, RGB data D[23:0] and clock PCLK.Here, clock PCLK can be with reference to figure 1 from AP12() the clock ECLK(that provides is with reference to figure 1).
In Fig. 2, show the packet showing by horizontal direction.Yet, can be with the packet showing by horizontal direction is identical or basic identical by the packet showing by vertical direction.
Fig. 3 is the display timing generator figure of the one exemplary embodiment of design according to the present invention.With reference to figure 3, the frame showing in Fig. 2 can be illustrated.
In the horizontal direction, frame can comprise after horizontal velocity based on horizontal-drive signal Hsync action (HSA), level along (HBP), horizontal anomalous movement (HACT) and horizontal forward position (HFP).
In vertical direction, frame can comprise vertical speed action (VSA), vertical rear edge (VBP), vertical movable (VACT) and vertical forward position (VFP) based on vertical synchronizing signal Vsync.
The display timing generator value of above-mentioned frame can be according to display panel 16(with reference to figure 1) resolution and difference.
For convenience, tentation data grouping according to MIPI at AP12 with DDI14(with reference to figure 1) between transmit.
Fig. 4 A is the figure that the input of the MIPI data of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 4A, show the example that wherein shows that data based 4 passage MIPI are transfused to.Use 4 passage MIPI, packet MIPI DATA[7:0], MIPI DATA[15:8], MIPI DATA[23:16] and MIPI DATA[31:24] can be with the frequency of 1Gbps from AP12(with reference to figure 1) be transferred to DDI14.In other words, if 1Gbps is 4 passages based on described MIPI by byte conversion, can uses the external clock MIPI CLK of 125MHz to receive and show data.Can be at each byte clock, in other words, every 125MHz(=8ns), input 32 and show data.In addition, every three clock MIPI CLK(for example, the ECLK in Fig. 1) can receive four pixel datas.Here, pixel data can be formed by the blue data of the red data of a byte, the green data of a byte and a byte.
For example, in Fig. 4 A, PD[47:24] pixel data 1 comprise R, G, the B of the dark-coloured shade in the first period of MIPI CLK, PD[47:24] pixel data 2 comprise the first period of MIPI CLK and R, G, the B of the shallow light tone shade in the second period, PD[47:24] pixel data 3 comprise the second period of MIPICLK and R, G, the B of the more shallow light tone shade in the 3rd period, and PD[23:0] pixel data 4 comprise R, G, the B of the minimum shade in the 3rd period of MIPI CLK.
According to the present invention, the packet of the MIPI data of the one exemplary embodiment of design is not limited to according to 4 passage MIPI inputs.According to the present invention, the packet of the MIPI data of the one exemplary embodiment of design can be according to the MIPI input of at least one passage.
Fig. 4 B is the figure that the input of the MIPI data of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 4B, show the example that wherein shows that data based 3 passage MIPI are transfused to.
In Fig. 4 B, can be at each byte clock, in other words, and every 125MHz(=8ns), input 24 and show data.In addition, every three clock MIPI CLK(for example, the ECLK in Fig. 1) can receive three pixel datas.For example, in Fig. 4 B, PD[23:0] pixel data 1 comprise R, G, the B in the first period of MIPI CLK, PD[23:0] pixel data 2 comprise R, G, the B in the second period of MIPI CLK, and PD[23:0] pixel data 3 comprise R, G, the B in the 3rd period of MIPI CLK.
Fig. 5 is the diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.According to the present invention, the DDI100 of the one exemplary embodiment of design can comprise that divider 120, a plurality of first in first out (FIFO) storer 141 to 14N(N are to be greater than 2 integer) and a plurality of graphic memory 161 to 16N.
24 demonstration data that each in FIFO storer 141 to 14N can interweave according to external clock MIPI CLK storage.Each in FIFO storer 141 to 14N can show data (or, pixel data) in response to 24 of internal clocking OSC CLK outputs.Here, the frequency of internal clocking OSC CLK can be lower than the frequency of external clock MIPI CLK.Therefore, each in FIFO storer 141 to 14N can be used as asynchronous FIFO memory.
The demonstration data that each in FIFO storer 141 to 14N can be used second frequency fb storage to interweave, and the demonstration data of using the 3rd frequency f c output to store.Here, the 3rd frequency f c can be lower than first frequency fa and higher than second frequency fb.In other words, can be faster than the speed that demonstration data is write to FIFO storer 141 to 14N from the speed of FIFO storer 141 to 14N reading displayed data.This can meet a condition: before the shown data of FIFO storer 141 to 14N are filled up, the demonstration data of storing are drawn out of from FIFO storer 141 to 14N.
In an exemplary embodiment, each in FIFO storer 141 to 14N can be passed through trigger, static RAM (SRAM) or dual-port SRAM realization.
In an exemplary embodiment, each in graphic memory 161 to 16N can realize by DRAM or dual-port DRAM.
As mentioned above, each in graphic memory 161 to 16N can be carried out write operation and scan operation in response to internal clocking OSCCLK.The clock zone of graphic memory 161 to 16N can be synthetic by internal clocking OSC CLK.
Each in graphic memory 161 to 16N can be configured to that enable pass crosses that one dimension/two-dimensional address arranges to the access of write operation or the access to scan operation.
Fig. 6 is the one exemplary embodiment of the design according to the present invention, illustrate in the graphic memory in Fig. 5 each write operation and the figure of the sequential of scan operation.With reference to figure 6, can carry out write operation and scan operation in response to internal clocking OSCCLK.For example, can carry out write operation in response to the rising edge of internal clocking OSC CLK, and can carry out scan operation in response to the negative edge of internal clocking OSC CLK.As shown in Figure 6, after having carried out three write operations, can carry out single pass operation.
The in the situation that of general figures storer, arbitration circuit can be used for carrying out write operation and scan operation in particular address, or is used for carrying out the write/scanning/read operation of routine when scan command and read command are inputted simultaneously.Because arbitration circuit write clock and scan clock is limited, the highest frequency of general figures storer may be limited by arbitration circuit.Because each general figures storer comprises himself arbitration circuit, so the size of general figures storer may increase.In addition, in order to drive the super-resolution display of widescreen XGA (Extended Graphics Array) (WXGA) type, every frame can provide 4M bit or larger demonstration data (for example, 1Gbps/ passage) to DDI.Yet general figures storer can not use its highest operating frequency to process and process 4M bit or larger demonstration data in every frame.
On the other hand, as shown in Figure 6, according to the present invention, the DDI100(of the one exemplary embodiment of design is with reference to figure 5) can remove for showing the read operation of data.For example, the data that the DDI100 of the one exemplary embodiment of design can change by scan operation rather than read operation in response to the read request transmission of external host according to the present invention.The DDI100 of the one exemplary embodiment of conceiving according to the present invention also can remove the highest operating frequency of restriction and affect the arbitration circuit of the size of graphic memory.
As shown in Figure 5, according to the present invention, the DDI100 of one exemplary embodiment of design can be configured to come drive pattern storer 161 to arrive 16N with the unified internal clocking OSC CLK that is used as writing clock and scan clock.Thereby the high speed that graphic memory 161 to 16N can be used the highest operating frequency to process and input in order to drive super-resolution display shows data.
Fig. 7 is the figure that the data time sequence when carrying out the interweaving of one exemplary embodiment of the design according to the present invention is shown.With reference to figure 7, according to 4 passage MIPI(of the high-speed serial interface in the super-resolution display as WXGA type (corresponding to full HD (HD) type of display) for example show, at the 1Gbps of 125MHz) the sequential of input data.8 interleaving technologies can be used to the frequency condition that meets input data.In other words, as shown in Figure 7, externally six of clock MIPI CLK cycles during can to divider 120 provide eight pixel datas (for example, PD[47:24] and PD[23:0] pixel data 1-8).Here, a pixel data can be formed by 24 bit data.
According to the present invention, the DDI100(of the one exemplary embodiment of design is with reference to figure 5) can eliminate the arbitration circuit that traditional graphic memory is used with FIFO storer 141 to 148.In the one exemplary embodiment of the present invention's design, each in graphic memory 161 to 16N can be used the internal clocking OSC CLK storage pixel data that generate from the oscillator of DDI100, and without using external clock MIPICLK.In other words, each in graphic memory 161 to 16N can operate in response to internal clocking OSCCLK rather than for example, for the clock of input/output operations (, write operation and scan operation).
Fig. 8 A is the figure interweaving that the divider of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 8A, divider 120 can be carried out 8 and interweave.Interweave for 8, can use 32 storage blocks.32 storage blocks 0 to 31 can be divided into eight group GRAM1 to GRAM8, and GRAM1 comprises four storage blocks to each in GRAM8.Here, described 32 storage blocks can realize by least one or more graphic memory.
The divider 120 of the one exemplary embodiment of conceiving according to the present invention is not limited to carry out 8 and interweaves.According to the present invention, the divider 120 of one exemplary embodiment of design can be carried out N and interweaves, and in N interweaves, a plurality of storage blocks are divided into N group and described N group is sequentially accessed.
Fig. 8 B is the figure interweaving that the divider of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 8B, a plurality of graphic memory GRAM1 can comprise a plurality of storage blocks 0 to N-1 to each in GRAMN, and divider 120 is every N time can be according to graded access block once.
Fig. 9 A is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.With reference to figure 9A, DDI200 can comprise MIPI wrapper (wrapper) 212, burst converter (slice converter) 214, divider 220, oscillator 230, FIFO storer 241 to 248, graphic memory 261 to 268, time schedule controller 270, scanning monitor 272, the first data combiner 281 and the second data combiner 282 and view data processing block 290.
Each in FIFO storer 241 to 248 can frequency of utilization fb(>=fa/8) (for example, 20.8MHz) carry out write operation so that 24 of interweaving of memory allocator 220 show data.Each in FIFO storer 241 to 248 can be used higher than the frequency of 20.8MHz and carry out read operation so that the data that output is stored.In write operation, graphic memory 261 to 268 can show data from 24 of 241 to 248 outputs of FIFO storer respectively in response to internal clocking OSC CLK storage.Here, the frequency f c of internal clocking OSC CLK can be higher than 20.9MHz.In other words, the writing rate of each in graphic memory 261 to 268 can be higher than 20.9MHz.
Each in graphic memory 261 to 268 can comprise a plurality of storage blocks.The signal that graphic memory 261 to 268 can be shared such as data-signal, command signal, address signal etc.For example, the first graphic memory 261 can comprise four storage blocks 0,8,16 and 24, and described four storage blocks 0,8,16 and 24 can be shared signal.
In scan operation, each in graphic memory 261 to 268 can show data in response to 24 of internal clocking OSC CLK outputs.Time schedule controller 270 can generate for control graphic memory 261 to 268 each write operation or the signal of scan operation.Time schedule controller 270 can be transfused to internal clocking OSC CLK.
In an exemplary embodiment, for each the frequency f d of scan operation of graphic memory 261 to 268, can be determined, made can not to generate the image fade relevant with frequency f c for write operation.
Scanning monitor 272 can be controlled in response to the control signal from time schedule controller 270 scan operation of graphic memory 261 to 268.
Each in the first data combiner 281 and the second data combiner 282 can merge respectively 24 demonstration data of two graphic memory outputs from graphic memory 261 to 268 to form 2 pixel datas.View data processing block 290 can be stored from 2 pixel datas of the first data combiner 281 and the second data combiner 282 outputs.View data processing block 290 can be content-based auto brightness controller or the displacement latch of Source drive piece.2 pixel datas of storage can be for showing.
According to the present invention, the DDI200 of the one exemplary embodiment of design can be to showing that data execution 8 interweaves, to interweaved demonstration data are stored in graphic memory 261 to 268 by FIFO storer 241 to 248.
In addition, according to the present invention, the DDI of the one exemplary embodiment of design can be configured to comprise line shared between FIFO storer and graphic memory.
Fig. 9 B is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.Fig. 9 B is similar to Fig. 9 A, except FIFO storer for example, for example, is shared outside data line (, 261,262) the every a pair of and corresponding graphic memory in (, 241,242).
In Fig. 9 A and Fig. 9 B, illustrated and described the example that wherein view data processing block 290 is processed demonstration data as 2 pixel datas.Yet the one exemplary embodiment of the present invention's design is not limited to this.View data processing block 290 can be processed demonstration data as 4 pixel datas.
Figure 10 is the block diagram that the DDI of the one exemplary embodiment of design according to the present invention is shown.With reference to Figure 10, DDI300 can comprise MIPI wrapper 312, burst converter 314, divider 320, oscillator 330, FIFO storer 341 to 348, graphic memory 361 to 368, time schedule controller 370, scanning monitor 372 and view data processing block 390.It is identical or basic identical with the DDI200 in Fig. 9 A or Fig. 9 B that DDI300 in Figure 10 can be configured to, the first data combiner 281 in Fig. 9 A or Fig. 9 B and the second data combiner 282 be removed and view data processing block 390 using demonstration data as 4 pixel datas are processed.Therefore, to further describing of DDI300, will be omitted.
Figure 11 is the block diagram that the mobile DDI of the one exemplary embodiment of design according to the present invention is shown.With reference to Figure 11, mobile DDI400 can comprise MIPI wrapper 412, bus controller 415, address counter 416, divider 420, oscillator 430, FIFO storer 441 to 448, graphic memory 461 to 468, time schedule controller 470, scanning monitor 472 and view data processing block 490.In mobile DDI400, the burst converter 314 in Fig. 9 A or Fig. 9 B can be by bus controller 415 and address counter 416(for example, and 414) realize.
Each in FIFO storer 441 to 448 can be in response to writing enable signal WEN OPADD WAD and 1 byte data D0 to D7.Here, writing enable signal WEN can use as the rising edge of the internal clocking OSC CLK described in Fig. 6.Address WAD can be the value of the storage block of the corresponding GRAM of indication.
Each in graphic memory 461 to 468 can be in response to scan enable signals SEN, and the storage block corresponding with address SAD carried out to scan operation, and can be in response to the data DO_1[23:0 of output enable signal OEN output scanning] to DO_4[23:0].Here, scan enable signals SEN can be used the negative edge of internal clocking OSC CLK as shown in Figure 6.
Scanning monitor 472 can generate scan enable signals SEN, address SAD and output enable signal OEN in response to clock counter signal CLKCNT and thread count signal LINECNT.
Scanning monitor 472 can be processed enable signal IP_DE, horizontal-drive signal IP_Hsync, vertical synchronizing signal IP_Vsync and the first demonstration data I P_DATA0 and the second demonstration data I P_DATA1 by output image data.Here first shows that data I P_DATA0 and second shows that data I P_DATA1 can be the data from graphic memory 461 to 468 scannings.
View data processing block 490 can be processed enable signal IP_DE in response to view data the first demonstration data I P_DATA0 and second is shown to data I P_DATA1 processes as 2 pixel datas.
According to the present invention, the mobile DDI400 of the one exemplary embodiment of design can pass through graphic memory 461 to 468 high speed processing data, and wherein graphic memory 461 to 468 is configured to be carried out write operation and carried out scan operation by 4 interleaving technologies by 8 interleaving technologies.
Figure 12 is the process flow diagram that the data display processing method of the one exemplary embodiment of design according to the present invention is shown.Below, with reference to Fig. 1, to Figure 12, data display processing method is described.
At operation S110, by FIFO storer 2n(n, being greater than 2 integer) the demonstration data that interweave can be stored in graphic memory.At operation S120, can be by the demonstration data of storing in n interleaving technology scanning patter storer.At operation S130, it is processed that the demonstration data that scan can be used as predetermined pixel data.
Use described data display processing method, can come high speed processing to show data by carry out write operation and scan operation with interleaving technology simultaneously.
According to the present invention, the DDI of the one exemplary embodiment of design can not comprise the arbitration circuit that limits the size increase of storing the highest operating frequency of the graphic memory that shows data and causing graphic memory.
The DDI of the one exemplary embodiment that use is conceived according to the present invention, by adding FIFO storer, no matter the highest operating frequency of DDI can increase, and WXGA(800x1280) full type of display and HD(1080x1920 or 1920x1080) increase of the frequency of the input data of the super-resolution display of type of display.
The DDI of the one exemplary embodiment that use is conceived according to the present invention, likely by the input data of FIFO interleaved memory graphic memory, and likely arranges each storage block to such an extent that be suitable for the required chip size in physical layout aspect.
According to the present invention, the DDI of the one exemplary embodiment of design can have 8 interleave circuits and FIFO storer with relatively low speed drive by clock zone is changed into, thus the electric current that reduces to consume in display operation.
The one exemplary embodiment of the present invention's design for example can be not limited to DDI(, MIPI digital command collection (DCS) command mode).The one exemplary embodiment of the present invention design can be applied in main frame (for example, application processor) wherein and comprise for the frame buffer of storing image data with for the treatment of the structure of the time schedule controller of view data.The one exemplary embodiment of the present invention design can be applied on the armamentarium that comprises the graphic memory that is configured to the view data that interlaced video data and processing interweave.
Figure 13 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.With reference to Figure 13, display system 1000 can comprise display-driver Ics 1100, display panel 1200, touch screen controller 1300, touch-screen 1400, image processor 1500 and console controller 1600.
In display system 1000, display-driver Ics 1100 can be configured to provide demonstration data to display panel 1200, and touch screen controller 1300 can be connected to the touch-screen 1400 overlapping with display panel 1200 and be configured to receive sense datas from touch-screen 1400.Display-driver Ics 1100 can be configured to carry out data display processing method described referring to figs. 1 to Figure 12, the one exemplary embodiment of design according to the present invention.Console controller 1600 can be application processor or graphics card.
According to the present invention, the display system 1000 of the one exemplary embodiment of design (for example can be applied in mobile phone, Galaxy S, Galaxy Note, iPhone etc.), tablet personal computer (PC) (for example, Galaxy Tab, iPad etc.), etc.
Figure 14 is the block diagram that the display system of the one exemplary embodiment of design according to the present invention is shown.With reference to Figure 14, display system 2000 can comprise application processor 2100, display-driver Ics 2200 and panel 2300.It is identical with display panel 16 or basic identical with the application processor 12 in Fig. 1 that each in application processor 2100 and panel 2300 can be configured to.
Display-driver Ics 2200 can comprise logical block 2210, divider 2220, Source drive piece 2230, power module 2240 and graphic memory GRAM1～GRAM N.Logical block 2210 can be controlled all operations were of display-driver Ics 2200.It is identical or basic identical with the divider 120 in Fig. 8 B that divider 2220 can be configured to.Source drive piece 2230 can receive and show data and transmit this demonstration data to panel 2300 from graphic memory GRAM1～GRAM N.Power module 2240 can receive electric power supply and generate and the grayscale voltage that shows that data are corresponding.
According to the present invention, the data display processing method of one exemplary embodiment of design can be stored in by interconnective at least one the microchip/integrated circuit of mainboard, hardware logic and memory devices, and can be by the software that moved by microprocessor or firmware, ASIC(special IC), FPGA(field programmable gate array) or its combination realize.
Although the one exemplary embodiment with reference to the present invention's design illustrates and has described design of the present invention particularly, those of ordinary skills are clear, can carry out the change in various forms and details here and do not depart from the spirit and scope by the defined the present invention's design of claims.
Claims (25)
1. a display-driver Ics DDI, comprising:
Divider, it is configured to output display data;
A plurality of fifo fifo storeies, it is configured to according to external clock from divider reception demonstration data and in response to internal clocking output display data; With
A plurality of graphic memories, it is configured to receive and show data from FIFO storer.
2. DDI as claimed in claim 1, wherein the frequency of internal clocking is higher than the frequency of external clock.
3. DDI as claimed in claim 1, wherein said divider receives and shows data with first frequency.
4. DDI as claimed in claim 3, wherein said demonstration data are exported from divider with second frequency, and wherein second frequency is equal to or higher than divided by the first frequency after the quantity of FIFO storer.
5. DDI as claimed in claim 4, wherein said demonstration data are with the 3rd frequency from the output of FIFO storer, and wherein the 3rd frequency is higher than second frequency and lower than first frequency.
6. DDI as claimed in claim 4, wherein said demonstration data are with the 3rd frequency from the output of FIFO storer, and wherein the 3rd frequency equals the frequency of internal clocking.
7. DDI as claimed in claim 1, wherein the quantity of FIFO storer equals the quantity of graphic memory.
8. DDI as claimed in claim 1, wherein said divider receives and shows data via HSSI High-Speed Serial Interface.
9. DDI as claimed in claim 1, wherein said divider receives and shows data with the frequency of 125MHz.
10. DDI as claimed in claim 1, also comprises the oscillator that is configured to generate internal clocking.
11. 1 kinds of display-driver Ics DDI, comprising:
Divider, it is configured to output display data;
A plurality of fifo fifo storeies, it is configured to receive and show data and output display data from divider; With
A plurality of graphic memories, it is configured in response to internal clocking from FIFO storer reception demonstration data and in response to internal clocking output display data.
12. DDI as claimed in claim 11, the data based enable signal of writing that is positioned at the rising edge of internal clocking of wherein said demonstration is received at graphic memory.
13. DDI as claimed in claim 12, the data based scan enable signals that is positioned at the negative edge of internal clocking of wherein said demonstration is exported from graphic memory.
14. DDI as claimed in claim 13, also comprise and are configured to control the time schedule controller of writing enable signal and scan enable signals.
15. DDI as claimed in claim 11, wherein receive and show that data frequency used is with identical from graphic memory output display data frequency used at graphic memory.
16. DDI as claimed in claim 11, the data based external clock of wherein said demonstration is received by FIFO storer, and described demonstration data are exported from FIFO storer in response to internal clocking.
17. DDI as claimed in claim 16, wherein the frequency of internal clocking is higher than the frequency of external clock.
18. DDI as claimed in claim 11, wherein said graphic memory does not comprise arbitration circuit.
19. DDI as claimed in claim 11, also comprise the oscillator that is configured to generate internal clocking.
20. DDI as claimed in claim 11, each of wherein said graphic memory has corresponding FIFO storer.
21. 1 kinds of display-driver Ics DDI, comprising:
Divider, it is configured to output display data;
A plurality of fifo fifo storeies, it is configured to receive and show data from divider; With
A plurality of graphic memories, it is configured to receive and show data from FIFO storer,
Wherein the every a pair of and corresponding graphic memory of FIFO storer centering is to sharing data line.
22. DDI as claimed in claim 21, wherein said FIFO storer receive to show data with first frequency from divider, and with second frequency via data line output display data, wherein second frequency is higher than first frequency.
23. DDI as claimed in claim 21, wherein said FIFO storer receives and shows data from divider according to external clock, and in response to internal clocking output display data.
24. DDI as claimed in claim 21, wherein said graphic memory receives and shows data from FIFO storer in response to internal clocking.
The data processing method of 25. 1 kinds of display-driver Ics, comprising:
According to external clock, the demonstration data from divider are write to a plurality of fifo fifo storeies;
In response to internal clocking, the demonstration data from FIFO storer are write to a plurality of graphic memories; And
In response to internal clocking by the demonstration data scanning of graphic memory to view data processing block.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2012-0105823 | 2012-09-24 | ||
| KR1020120105823A KR101987160B1 (en) | 2012-09-24 | 2012-09-24 | Display driver integrated circuit, display system having the same, and display data processing method thereof |
| US13/785,832 US9240165B2 (en) | 2012-09-24 | 2013-03-05 | Display driver integrated circuit including first-in-first-out (FIFO) memories configured to receive display data from a distributor and output the display data to graphics memories a display system having the same, and a display data processing method thereof |
| US13/785,832 | 2013-03-05 |
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| CN103680383B CN103680383B (en) | 2018-09-11 |
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