CN103680383B - Display-driver Ics, display system and its data display processing method - Google Patents

Abstract

Provide a kind of display-driver Ics comprising：Distributor is configured as output display data；Multiple first in first out（FIFO）Memory is configured as receiving display data from distributor according to external clock and exports display data in response to internal clocking；With multiple graphic memories, it is configured as receiving display data from FIFO memory.

Description

Display-driver Ics, display system and its data display processing method

Cross reference to related applications

This application claims the South Korea patent application 10-2012- for being submitted to Korean Intellectual Property Office on 24th in September in 2012 No. 0105823 priority, it is open to be incorporated by reference in its entirety.

Technical field

Present inventive concept be related to display-driver Ics including the display-driver Ics display system, And its data display processing method.

Background technology

With including high-definition television（HDTV）The appearance of the smart mobile phone of the super-resolution display apparatus module of type, can It can need to use organic light emitting display（OLED）And/or low-temperature polysilicon liquid crystal on silicon displays（LTPS-LCD）Technology, widescreen Extended graphics array（WXGA）（800x1280）Or full HD types（1080x1920）Super-resolution move display driver collection At circuit（DDI）.When super-resolution mobile display is driven, it is contemplated that reduce application processor（AP）Electric current disappear Consumption, heat and burden, DDI may necessitate for the various solutions driven for low-power.

In addition, passing through HSSI High-Speed Serial Interface（HSSI）In DDI and cmos image sensor（CIS）It is transmitted between mobile AP Data volume be increased to cope with the super-resolution of such as full HD.Accordingly, it is possible in the presence of for high-speed driving energy The needs of the DDI of power.

Invention content

The exemplary embodiment of present inventive concept provides a kind of display-driver Ics（DDI）, including：Distribution Device is configured as output display data；Multiple first in first out（FIFO）Memory, be configured as according to external clock from point Orchestration receives display data and exports display data in response to internal clocking；With multiple graphic memories, be configured as from FIFO memory receives display data.

The frequency of internal clocking is higher than the frequency of external clock.

Distributor receives display data with first frequency.

Display data is exported with second frequency from distributor, and wherein second frequency is equal to or higher than divided by FIFO memory First frequency after quantity.

Display data is exported with third frequency from FIFO memory, and wherein third frequency is higher than second frequency and less than the One frequency.

Display data is exported with third frequency from FIFO memory, and wherein third frequency is equal to the frequency of internal clocking.

The quantity of FIFO memory is equal to the quantity of graphic memory.

Distributor receives display data via HSSI High-Speed Serial Interface.

Distributor is with the frequency reception display data of 125MHz.

DDI further includes the oscillator for being configurable to generate internal clocking.

The exemplary embodiment of present inventive concept provides DDI, including：Distributor is configured as output display data； Multiple FIFO memories are configured as receiving display data from distributor and export display data；It is stored with multiple figures Device is configured to respond to internal clocking and receives display data from FIFO memory and export display in response to internal clocking Data.

Display data is received according to the write enable signal of the rising edge of internally positioned clock in graphic memory.

Display data is exported according to the scan enable signal of the failing edge of internally positioned clock from graphic memory.

DDI further includes the sequence controller for being configured as control write enable signal and scan enable signal.

Graphic memory receive display data used in frequency with from graphic memory output display data used in frequency Rate is identical.

Display data is received according to external clock by FIFO memory, and display data in response to internal clocking from FIFO Memory exports.

The frequency of internal clocking is higher than the frequency of external clock.

Graphic memory does not include arbitration circuit.

DDI further includes the oscillator for being configurable to generate internal clocking.

Each of graphic memory is with corresponding FIFO memory.

The exemplary embodiment of present inventive concept provides DDI, including：Distributor is configured as output display data； Multiple FIFO memories are configured as receiving display data from distributor；With multiple graphic memories, be configured as from FIFO memory reception display data, wherein every a pair of FIFO memory centering are with corresponding graphic memory to shared data Line.

FIFO memory receives display data with first frequency from distributor, and is exported via data line with second frequency Display data, wherein second frequency are higher than first frequency.

FIFO memory receives display data according to external clock from distributor, and exports and show in response to internal clocking Data.

Graphic memory receives display data in response to internal clocking from FIFO memory.

The exemplary embodiment of present inventive concept provides the data processing method of DDI, including：In the future according to external clock The multiple FIFO memories of display data writing from distributor；In response to internal clocking by the display data from FIFO memory Multiple graphic memories are written；And the display data of graphic memory is scanned to image real time transfer in response to internal clocking Block.

Description of the drawings

By reference to the attached drawing exemplary embodiment that present inventive concept is described in detail, the above and other spy of present inventive concept Sign will become clearer.

Fig. 1 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.

Fig. 2 is the figure for the packet for showing the exemplary embodiment according to present inventive concept.

Fig. 3 is the display sequence diagram according to the exemplary embodiment of present inventive concept.

Fig. 4 A are the mobile industry processor interfaces for showing the exemplary embodiment according to present inventive concept（MIPI）Data Input figure.

Fig. 4 B are the figures for the input for showing the MIPI data according to the exemplary embodiment of present inventive concept.

Fig. 5 is the display-driver Ics for showing the exemplary embodiment according to present inventive concept（DDI）Diagram.

Fig. 6 is the exemplary embodiment according to present inventive concept, show each graphic memory in Fig. 5 write operation and The figure of the sequential of scan operation.

Fig. 7 is the figure for the sequential for showing the data when executing the intertexture according to the exemplary embodiment of present inventive concept.

Fig. 8 A are the figures of the intertexture for the distributor for showing the exemplary embodiment according to present inventive concept.

Fig. 8 B are the figures of the intertexture for the distributor for showing the exemplary embodiment according to present inventive concept.

Fig. 9 A are the block diagrams for the DDI for showing the exemplary embodiment according to present inventive concept.

Fig. 9 B are the block diagrams for the DDI for showing the exemplary embodiment according to present inventive concept.

Figure 10 is the block diagram for the DDI for showing the exemplary embodiment according to present inventive concept.

Figure 11 is the block diagram for the mobile DDI for showing the exemplary embodiment according to present inventive concept.

Figure 12 is the flow chart for the data display processing method for showing the exemplary embodiment according to present inventive concept.

Figure 13 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.

Figure 14 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.

Specific implementation mode

Hereafter, the exemplary embodiment of present inventive concept will be described in detail with reference to the attached drawings.However, present inventive concept can be with A variety of different form specific implementations, and be not construed as being limited in embodiments set forth here.Through attached drawing and say Bright book, similar reference label may refer to similar element.

Fig. 1 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.With reference to figure 1, display system System 10 may include application processor（Hereinafter, being properly termed as " AP "）12, display-driver Ics（Hereinafter, can become “DDI”）14 and display panel 16.

AP12 can control the overall operation of display system 10.AP12 can output and input data in response to clock ECLK Grouping, wherein each packet has display data.Here, packet may include display data, horizontal synchronizing signal Hsync, vertical synchronizing signal Vsync, data enable signal DE, etc..

DDI14 can receive packet by mobile interface from AP12, and can be with output level synchronizing signal Hsync, vertical synchronizing signal Vsync, data enable signal DE, display data RGB data, clock PCLK.Here, the movement Interface can be HSSI High-Speed Serial Interface, such as mobile industry processor interface（MIPI）, mobile display digital interface（MDDI）, it is tight Gather type display port（CDP）, mobile pixel link（MPL）, the advanced difference signaling of current-mode（CMADS）, etc..Following In exemplary embodiment, it is assumed that DDI14 carries out interface operation according to MIPI.

DDI14 may include the graphic memory for HSSI High-Speed Serial Interface（For example, graphics random access memory （GRAM））.Here, GRAM can be used for reducing the current drain, heat and burden of AP12.GRAM can be configured as write-in The display data inputted from AP12, and pass through the data of scan operation output write-in.In an exemplary embodiment, GRAM can be with It is dual-port dynamic random access memory（DRAM）.

It does not include graphic memory for HSSI High-Speed Serial Interface that DDI14, which can be configured as,.In this case, DDI14 can be grouped with buffered data to export display data.In following exemplary embodiment, it is assumed that DDI14 is used GRAM。

Display panel 16 can press frame display data under the control of DDI14（For example, display data）.Display panel 16 can To be organic light emitting display（OLED）Panel, liquid crystal display（LCD）Panel, Plasmia indicating panel（PDP）, electrophoresis showed face Plate or Electrowetting display panel.However, display panel 16 is without being limited thereto.

By including the DDI14 using GRAM, display system 10 can be used for high-speed interface.

Fig. 2 is the figure for the packet for showing the exemplary embodiment according to present inventive concept.In fig. 2, packet Can be the data being shown in by horizontal direction on display panel 16.Packet may include horizontal velocity action（HSA）Point Edge after group, level（HBP）Grouping, horizontal anomalous movement（HACT）Grouping and horizontal forward position（HFP）Grouping.However, present inventive concept Packet is without being limited thereto.

DDI14（With reference to figure 1）Can receive will be by the packet that horizontal direction is shown so as to the enabled letter of output data Number DE, horizontal synchronizing signal Hsync, RGB data D [23:0] and clock PCLK.Here, clock PCLK can be from AP12（Ginseng Examine Fig. 1）The clock ECLK of offer（With reference to figure 1）.

In fig. 2 it is shown that the packet that will be shown by horizontal direction.However, the data that will be shown in a vertical direction Grouping can be identical or essentially identical with the packet that will be shown by horizontal direction.

Fig. 3 is the display sequence diagram according to the exemplary embodiment of present inventive concept.With reference to figure 3, the frame shown in Fig. 2 can To be shown.

In the horizontal direction, frame may include the horizontal velocity action based on horizontal synchronizing signal Hsync（HSA）, it is horizontal Edge afterwards（HBP）, horizontal anomalous movement（HACT）With horizontal forward position（HFP）.

In vertical direction, frame may include the vertical speed action based on vertical synchronizing signal Vsync（VSA）, it is vertical Edge afterwards（VBP）, Vertical movements（VACT）And vertical front porch（VFP）.

The display timing values of above-mentioned frame can be according to display panel 16（With reference to figure 1）Resolution ratio and it is different.

For convenience, it is assumed that packet is according to MIPI in AP12 and DDI14（With reference to figure 1）Between transmit.

Fig. 4 A are the figures for the input for showing the MIPI data according to the exemplary embodiment of present inventive concept.With reference to figure 4A, It is shown in which the example that display data is entered according to 4 channel MIPI.Use 4 channel MIPI, packet MIPI DATA [7:0]、MIPI DATA[15:8]、MIPI DATA[23:16] and MIPI DATA [31:24] can with the frequency of 1Gbps from AP12（With reference to figure 1）It is transferred to DDI14.In other words, if 1Gbps is 4 channels based on the MIPI by byte conversion , then the external clock MIPI CLK of 125MHz can be used to receive display data.It can be in each byte clock, in other words It says, per 125MHz（=8ns）, input 32 display datas.In addition, every three clock MIPI CLK（For example, the ECLK in Fig. 1） Four pixel datas can be received.Here, pixel data can by the red data of a byte, byte green data, It is formed with the blue data of a byte.

For example, in Figure 4 A, PD [47:24] pixel data 1 includes the dark shade in the first period of MIPI CLK R, G, B, PD [47:24] pixel data 2 includes the shallow light tone shade in the first time period and the second time period of MIPI CLK R, G, B, PD [47:The R of more shallow light tone shade in the second period and third period of the pixel data 3 24] including MIPICLK, G, B, and PD [23:0] pixel data 4 includes R, G, B of the minimum shade in the third period of MIPI CLK.

It is not limited to according to the packet of the MIPI data of the exemplary embodiment of present inventive concept defeated according to 4 channel MIPI Enter.It can be according to the MIPI at least one channel according to the packet of the MIPI data of the exemplary embodiment of present inventive concept Input.

Fig. 4 B are the figures for the input for showing the MIPI data according to the exemplary embodiment of present inventive concept.With reference to figure 4B, It is shown in which the example that display data is entered according to 3 channel MIPI.

It in figure 4b, can be in each byte clock, in other words, per 125MHz（=8ns）, input 24 display numbers According to.In addition, every three clock MIPI CLK（For example, the ECLK in Fig. 1）Three pixel datas can be received.For example, in figure 4b, PD[23:0] pixel data 1 includes R, G, B in the first period of MIPI CLK, PD [23:0] pixel data 2 includes R, G, B in the second period of MIPI CLK, and PD [23:R in the third period of pixel data 3 0] including MIPI CLK, G、B。

Fig. 5 is the diagram for the DDI for showing the exemplary embodiment according to present inventive concept.According to the demonstration of present inventive concept The DDI100 of property embodiment may include distributor 120, multiple first in first out（FIFO）Memory 141 arrives 14N（N is greater than 2 Integer）And multiple graphic memories 161 arrive 16N.

Distributor 120 can receive 24 display datas in response to external clock MIPI CLK（Alternatively, pixel data）, with Just it is N the display data of input to be interweaved（Hereinafter, being properly termed as " N intertextures "）.Here, it can be wherein adjacent show that N, which interweaves, Registration is according to the technology being stored in N number of different physical region to be accessed from many places.Interleaving technology is disclosed in the U.S. Patent application publication the 2011/0157200th, it is open to be incorporated by reference in its entirety.

Distributor 120 can be not limited to receive 24 display datas.Distributor 120 can be configured as M displays of reception Data（M is greater than 2 integer）.In an exemplary embodiment, distributor 120 can by cache memory or directly Memory accesses（DMA）It realizes.

Distributor 120 can use first frequency fa to receive display data, and second frequency fb outputs can be used to hand over The display data knitted.Here, first frequency fa can be the frequency of external clock MIPI CLK, and second frequency fb can be equal to Or higher than the frequency fa/N by being obtained first frequency fa divided by N.

FIFO memory 141 is shown to 24 that each in 14N can interweave according to external clock MIPI CLK storages Registration evidence.FIFO memory 141 can export 24 display datas to each in 14N in response to internal clocking OSC CLK （Alternatively, pixel data）.Here, the frequency of internal clocking OSC CLK can be less than the frequency of external clock MIPI CLK.Cause This, FIFO memory 141 may be used as asynchronous FIFO memory to each in 14N.

FIFO memory 141 can use the display data that second frequency fb storages interweave to each in 14N, and Stored display data is exported using third frequency fc.Here, third frequency fc can be less than first frequency fa and be higher than Second frequency fb.In other words, the speed for display data being read from FIFO memory 141 to 14N can be than writing display data Enter FIFO memory 141 and arrives the speed of 14N faster.This can meet a condition：It is shown to 14N in FIFO memory 141 Before data are filled up, the display data that is stored from FIFO memory 141 to 14N in be extracted.

In an exemplary embodiment, FIFO memory 141 can pass through trigger, static random to each in 14N Access memory（SRAM）Or dual-port SRAM is realized.

Graphic memory 161 to 16N can in response to internal clocking OSC CLK storage respectively from FIFO memory 141 to 24 display datas of 14N outputs.Graphic memory 161 can be swept to each in 16N in response to internal clocking OSC CLK Retouch 24 stored display datas.

In an exemplary embodiment, graphic memory 161 can pass through DRAM or dual-port to each in 16N DRAM is realized.

As described above, graphic memory 161 can write behaviour to each in 16N in response to internal clocking OSCCLK execution Work and scan operation.The clock domain of graphic memory 161 to 16N can be synthesized by internal clocking OSC CLK.

Graphic memory 161 can be configured as enabled pair by one-dimensional/two-dimensional address arrangement to each in 16N The access of write operation or access to scan operation.

Fig. 6 is the exemplary embodiment according to present inventive concept, shows writing for each in the graphic memory in Fig. 5 The figure of the sequential of operation and scan operation.With reference to figure 6, write operation can be executed in response to internal clocking OSCCLK and scanning is grasped Make.For example, write operation can be executed in response to the rising edge of internal clocking OSC CLK, and can be in response to internal clocking OSC The failing edge of CLK executes scan operation.As shown in Figure 6, after performing write operation three times, single pass behaviour can be executed Make.

In the case of general figures memory, arbitration circuit can be used for executing write operation in particular address and scanning is grasped Make, or conventional/read operation is write/scan for being executed when scan command and read command are inputted simultaneously.Because of arbitration electricity Write that clock and scan clock are limited, and the highest frequency of general figures memory may be limited by arbitration circuit in road.Due to each General figures memory includes the arbitration circuit of its own, therefore the size of general figures memory may increase.In addition, in order to Drive Wide Extended Graphics Array（WXGA）The super-resolution display of type, per frame can to DDI provide 4M bits or The display data of bigger（For example, the channels 1Gbps/）.However, general figures memory can not use at its highest operating frequency Manage the display data that 4M bits or bigger are handled in every frame.

On the other hand, as shown in Figure 6, according to the DDI100 of the exemplary embodiment of present inventive concept（With reference to figure 5）It can To remove the read operation for display data.For example, can be responded according to the DDI100 of the exemplary embodiment of present inventive concept In the data that the read request transmission of external host passes through scan operation rather than read operation conversion.According to the demonstration of present inventive concept Property embodiment DDI100 can also remove limitation highest operating frequency and influence graphic memory size arbitration circuit.

As shown in Figure 5, according to the DDI100 of the exemplary embodiment of present inventive concept can be configured as use by with The unified internal clocking OSC CLK for writing clock and scan clock carry out drive pattern memory 161 to 16N.Thus, figure storage Device 161 can be handled the high speed inputted to drive super-resolution display to 16N using highest operating frequency and show number According to.

Fig. 7 is the figure for showing the data time sequence when executing the intertexture according to the exemplary embodiment of present inventive concept.Ginseng Fig. 7 is examined, is shown according to the super-resolution display as WXGA types（Corresponding to full HD（HD）Type of display）In High-speed serial interface 4 channel MIPI（For example, in the 1Gbps of 125MHz）Input data sequential.8 interleaving technologies It can be used to meet the frequency condition of input data.In other words, as shown in Figure 7, external clock MIPI CLK's Eight pixel datas can be provided during six periods to distributor 120（For example, PD [47:24] and PD [23:0] pixel number According to 1-8）.Here, a pixel data can be formed by 24 data.

Distributor 120 can interweave during six periods of external clock MIPI CLK will be respectively stored in eight Eight pixel datas in a FIFO memory 141 to 148.Each in FIFO memory 141 to 148 can be when internal Stored pixel data is exported during a cycle of clock OSC CLK.In other words, in FIFO memory 141 to 148 The writing rate fb of each can be about 48ns.The reading rate fc of each in FIFO memory 141 to 148 can be than writing Speed fb is faster.For example, the reading rate of each in FIFO memory 141 to 148 can be about 30ns.Here, FIFO The reading rate fc of each in memory 141 to 148 can be that graphic memory 161 arrives 16N（With reference to figure 5）In each Writing rate.

According to the DDI100 of the exemplary embodiment of present inventive concept（With reference to figure 5）It can be arrived using FIFO memory 141 148 eliminate arbitration circuit used in traditional graphic memory.In the exemplary embodiment of present inventive concept, figure is deposited Reservoir 161 can use the internal clocking OSC CLK storage pixel numbers generated from the oscillator of DDI100 to each in 16N According to without using external clock MIPICLK.In other words, graphic memory 161 can be in response to each in 16N Internal clocking OSCCLK rather than be used for input/output operations（For example, write operation and scan operation）Clock operate.

Fig. 8 A are the figures of the intertexture for the distributor for showing the exemplary embodiment according to present inventive concept.With reference to figure 8A, divide Orchestration 120 can execute 8 intertextures.Interweave for 8,32 memory blocks can be used.32 memory blocks 0 to 31 can be divided into Each in eight groups GRAM1 to GRAM8, GRAM1 to GRAM8 includes four memory blocks.Here, 32 memory blocks can To be realized by least one or more graphic memory.

Distributor 120 can be by being sequentially performed access operation from the 0th memory block to the 31st memory block（For example, Write operation）To execute 8 intertextures.

It is not limited to execute 8 intertextures according to the distributor 120 of the exemplary embodiment of present inventive concept.According to present inventive concept The distributor 120 of exemplary embodiment can execute N intertextures, multiple memory blocks are divided into N groups and described in N intertextures N groups are sequentially accessed.

Fig. 8 B are the figures of the intertexture for the distributor for showing the exemplary embodiment according to present inventive concept.It is more with reference to figure 8B Each in a graphic memory GRAM1 to GRAMN may include that multiple memory blocks 0 arrive N-1, and distributor 120 is per n times It can be according to primary to graded access block.

Fig. 9 A are the block diagrams for the DDI for showing the exemplary embodiment according to present inventive concept.With reference to figure 9A, DDI200 can be with Including MIPI wrappers（wrapper）212, fragment converter（slice converter）214, distributor 220, oscillator 230, FIFO memory 241 to 248, graphic memory 261 to 268, sequence controller 270, scanning monitor 272, first count According to combiner 281 and the second data combiner 282 and image real time transfer block 290.

MIPI wrappers 212 can receive display data according to HSSI High-Speed Serial Interface, and can be in response to external clock MIPI CLK export 32 display datas.Here, the frequency fa of external clock MIPI CLK can be about 125MHz.

Fragment converter 214 can receive the display data exported from MIPI wrappers 212, and can be in response to outside The display data of input is converted to 48 display datas by clock MIPI CLK（For example, 2 pixel datas）.

Distributor 220 can receive 48 display datas from fragment converter 214 and interweave to execute N.For the side of description Just, it is assumed that distributor 220 executes 8 and interweaves.

Oscillator 230 can generate internal clocking OSC CLK.

Each in FIFO memory 241 to 248 can be with frequency of use fb（≥fa/8）（For example, 20.8MHz）It executes 24 display datas that write operation is interweaved so as to memory allocator 220.Each in FIFO memory 241 to 248 can be with Read operation is executed using the frequency higher than 20.8MHz to output the stored data.In write operation, graphic memory 261 It can be in response to internal clocking OSC CLK storages respectively from 24 display datas of the output of FIFO memory 241 to 248 to 268. Here, the frequency fc of internal clocking OSC CLK can be higher than 20.9MHz.In other words, every in graphic memory 261 to 268 One writing rate can be higher than 20.9MHz.

Each in graphic memory 261 to 268 may include multiple memory blocks.Graphic memory 261 to 268 can be with The signal of shared such as data-signal, command signal, address signal etc..For example, the first graphic memory 261 may include four A memory block 0,8,16 and 24, and four memory blocks 0,8,16 and 24 can share signal.

In a scanning operation, each in graphic memory 261 to 268 can be defeated in response to internal clocking OSC CLK Go out 24 display datas.Sequence controller 270 can generate writing for each in control pattern memory 261 to 268 The signal of operation or scan operation.Sequence controller 270 can be entered internal clocking OSC CLK.

In an exemplary embodiment, the frequency fd for being used for the scan operation of each in graphic memory 261 to 268 can To be determined so that image fade related with the frequency fc of write operation is used for will not be generated.

Scanning monitor 272 can be arrived in response to the control signal control pattern memory 261 from sequence controller 270 268 scan operation.

Each in first data combiner 281 and the second data combiner 282 can merge respectively from figure storage 24 display datas of two graphic memories output in device 261 to 268 are to form 2 pixel datas.Image real time transfer Block 290 can store 2 pixel datas exported from the first data combiner 281 and the second data combiner 282.At image data Reason block 290 can be the displacement latch of auto brightness controller or Source drive block based on content.2 pixel numbers of storage According to being displayed for.

8 can be executed according to the DDI200 of the exemplary embodiment of present inventive concept to display data to interweave, will pass through The display data to be interweaved is stored in graphic memory 261 to 268 by FIFO memory 241 to 248.

In addition, can be configured as including FIFO memory and figure according to the DDI of the exemplary embodiment of present inventive concept The line shared between shape memory.

Fig. 9 B are the block diagrams for the DDI for showing the exemplary embodiment according to present inventive concept.Fig. 9 B are similar to Fig. 9 A, in addition to FIFO memory pair（For example, 241,242）In per a pair of and corresponding graphic memory pair（For example, 261,262）Shared number Except line.

In Fig. 9 A and Fig. 9 B, wherein image real time transfer block 290 has shown and described using display data as 2 pixel numbers According to the example handled.However, one exemplary embodiment not limited to this for present inventive concept.Image real time transfer block 290 can be with It is handled display data as 4 pixel datas.

Figure 10 is the block diagram for the DDI for showing the exemplary embodiment according to present inventive concept.With reference to figure 10, DDI300 can be with It is deposited including MIPI wrappers 312, fragment converter 314, distributor 320, oscillator 330, FIFO memory 341 to 348, figure Reservoir 361 to 368, sequence controller 370, scanning monitor 372 and image real time transfer block 390.DDI300 in Figure 10 can It is identical or essentially identical with the DDI200 in Fig. 9 A or Fig. 9 B to be configured as, in addition to the first data in Fig. 9 A or Fig. 9 B merge Device 281 and the second data combiner 282 be removed and image real time transfer block 390 using display data as 4 pixel datas into Except row processing.Therefore, further describing for DDI300 will be omitted.

Figure 11 is the block diagram for the mobile DDI for showing the exemplary embodiment according to present inventive concept.It is mobile with reference to figure 11 DDI400 may include MIPI wrappers 412, bus control unit 415, address counter 416, distributor 420, oscillator 430, At FIFO memory 441 to 448, graphic memory 461 to 468, sequence controller 470, scanning monitor 472 and image data Manage block 490.In mobile DDI400, the fragment converter 314 in Fig. 9 A or Fig. 9 B can pass through bus control unit 415 and address Counter 416（For example, 414）It realizes.

Bus control unit 415 can receive display data from MIPI wrappers 412, and in response to data enable signal DE [1:0] and clock PCLK output pixel datas PD [47:0].Here, clock PCLK can be external clock MIPI CLK.

Address counter 416 can receive clock PCLK and data enable signal DE [1:0] so as to output address DAD1 and DAD2。

Distributor 420 can receive address D AD1 and DAD2 from address counter 416, and be connect from bus control unit 415 Time receiving clock PCLK, data enable signal DE [1:0] and pixel data PD [47:It 0], and can be by pixel data PD [47:0] Real-time storage is in FIFO memory corresponding with address D AD1 and DAD2 441 to 448.In other words, distributor 420 can be with To pixel data PD [47:0]（For example, 2 pixel datas）It executes 8 to interweave, so as to the pixel data PD [47 that will be interweaved:0] it deposits Storage is in FIFO memory 441 to 448.

Each in FIFO memory 441 to 448 can be in response to write enable signal WEN output address WAD and 1 byte Data D0 to D7.Here, write enable signal WEN can use the rising edge of internal clocking OSC CLK as depicted in figure. Address WAD can be the value for the memory block for indicating corresponding GRAM.

Each in graphic memory 461 to 468 can be pair opposite with address SAD in response to scan enable signal SEN The memory block answered executes scan operation, and can be in response to the data DO_1 [23 of output enable signal OEN output scannings:0] To DO_4 [23:0].Here, scan enable signal SEN can use the decline of internal clocking OSC CLK as shown in Figure 6 Edge.

Sequence controller 470 can generate clock counter signal CLKCNT and line counter signals LINECNT.

Scanning monitor 472 can be generated in response to clock counter signal CLKCNT and line counter signals LINECNT Scan enable signal SEN, address SAD and output enable signal OEN.

Scanning monitor 472 can export image real time transfer enable signal IP_DE, horizontal synchronizing signal IP_Hsync, Vertical synchronizing signal IP_Vsync and the first display data IP_DATA0 and the second display data IP_DATA1.Here first Display data IP_DATA0 and the second display data IP_DATA1 can be the data scanned from graphic memory 461 to 468.

Image real time transfer block 490 can be in response to image real time transfer enable signal IP_DE by the first display data IP_ DATA0 and the second display data IP_DATA1 are handled as 2 pixel datas.

It can be high by graphic memory 461 to 468 according to the mobile DDI400 of the exemplary embodiment of present inventive concept Speed processing data, wherein graphic memory 461 to 468 are configured as executing write operation by 8 interleaving technologies and by 4 intertexture skills Art executes scan operation.

Figure 12 is the flow chart for the data display processing method for showing the exemplary embodiment according to present inventive concept.Under Face will describe data display processing method referring to figs. 1 to Figure 12.

In operation S110, pass through FIFO memory 2n（N is greater than 2 integer）The display data of intertexture can be stored in In graphic memory.It, can be by the display data that is stored in n interleaving technology scanning patter memories in operation S120.It is grasping Make S130, the display data scanned can be handled as scheduled pixel data.

Using the data display processing method, can write operation and scan operation be performed simultaneously by using interleaving technology Carry out high speed processing display data.

Can not include the figure storage of limitation storage display data according to the DDI of the exemplary embodiment of present inventive concept The highest operating frequency of device and cause the increased arbitration circuit of the size of graphic memory.

Using the DDI according to the exemplary embodiment of present inventive concept, passes through and add FIFO memory, the highest behaviour of DDI Working frequency can increase, but regardless of WXGA（800x1280）Type of display and full HD（1080x1920 or 1920x1080）It is aobvious Show the increase of the frequency of the input data of the super-resolution display of device type.

Use the DDI according to the exemplary embodiment of present inventive concept, it is possible to deposit by FIFO memory intertexture figure The input data of reservoir, and it is possible to be arranged to each memory block to be suitable for the chip size needed for physical layout aspect.

According to the DDI of the exemplary embodiment of present inventive concept can by by clock domain be changed to have 8 interleave circuits and FIFO memory drives at relatively lower speeds, to reducing the electric current consumed in display operation.

The exemplary embodiment of present inventive concept can be not limited to DDI（For example, MIPI digital command collection（DCS）Order mould Formula）.The exemplary embodiment of present inventive concept can apply host wherein（For example, application processor）Including being used for storage figure The structure of sequence controller as the frame buffer of data and for handling image data.The exemplary implementation of present inventive concept Example can be applied in the complete of the graphic memory including being configured as interlaced video data and the interweaved image data of processing In portion's equipment.

Figure 13 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.With reference to figure 13, display System 1000 may include display-driver Ics 1100, display panel 1200, touch screen controller 1300, touch screen 1400, image processor 1500 and host controller 1600.

In display system 1000, display-driver Ics 1100 can be configured as to be provided to display panel 1200 Display data, and touch screen controller 1300 can be connected to the touch screen 1400 Chong Die with display panel 1200 and be configured To receive sensing data from touch screen 1400.Display-driver Ics 1100 can be configured as execution referring to figs. 1 to figure The data display processing method of 12 exemplary embodiments described, according to present inventive concept.Host controller 1600 can be with It is application processor or graphics card.

It can be applied in mobile phone according to the display system 1000 of the exemplary embodiment of present inventive concept（For example, Galaxy S, Galaxy Note, iPhone etc.）, tablet personal computer（PC）（For example, Galaxy Tab, iPad etc. Deng）, etc..

Figure 14 is the block diagram for the display system for showing the exemplary embodiment according to present inventive concept.With reference to figure 14, display System 2000 may include application processor 2100, display-driver Ics 2200 and panel 2300.Application processor 2100 and panel 2300 in each can be configured as in Fig. 1 application processor 12 and display panel 16 is identical or base This is identical.

Display-driver Ics 2200 may include logical block 2210, distributor 2220, Source drive block 2230, electricity Source block 2240 and graphic memory GRAM1~GRAM N.Logical block 2210 can control display-driver Ics 2200 All operationss.Distributor 2220 can be configured as identical or essentially identical with the distributor 120 in Fig. 8 B.Source drive block 2230 can receive display data from graphic memory GRAM1~GRAM N and transmit the display data to panel 2300.Electricity Source block 2240 can receive supply of electric power and generate grayscale voltage corresponding with display data.

It can be stored according to the data display processing method of the exemplary embodiment of present inventive concept mutual by mainboard In at least one microchip/integrated circuit, hardware logic and the memory devices that connect, and can be by being transported by microprocessor Capable software or firmware, ASIC（Application-specific integrated circuit）、FPGA（Field programmable gate array）Or a combination thereof is realized.

Although the exemplary embodiment by reference to present inventive concept is particularly shown and described present inventive concept, ability Domain those of ordinary skill will be clear that the change that can herein carry out on various forms and details is wanted without departing from by appended right The spirit and scope of present inventive concept defined in asking.

Claims (8)

1. a kind of display-driver Ics DDI, including：

Distributor is configured as receiving display data with the first frequency of external clock, and interweave the display data, and in addition The second frequency of portion's clock exports interleaved display data；

Multiple fifo fifo memories are configured as receiving from distributor with the second frequency of external clock interleaved Display data and third rate-adaptive pacemaker display data with internal clocking；With

Multiple graphic memories are configured as receiving interleaved display data from FIFO memory,

Wherein second frequency is equal to or higher than the frequency obtained by the quantity of first frequency divided by interleaved display data, with And

Wherein third frequency higher than second frequency and is less than first frequency.

2. DDI as described in claim 1, wherein every a pair of FIFO memory centering are with corresponding graphic memory to shared Data line.

3. DDI as described in claim 1, wherein second frequency be equal to or higher than divided by the quantity of FIFO memory after One frequency.

4. DDI as described in claim 1, the wherein quantity of FIFO memory are equal to the quantity of graphic memory.

5. DDI as described in claim 1, wherein the distributor receives display data via HSSI High-Speed Serial Interface.

6. DDI as described in claim 1, wherein the distributor is with the frequency reception display data of 125MHz.

7. DDI as described in claim 1 further includes the oscillator for being configurable to generate internal clocking.

8. a kind of data processing method of display-driver Ics, including：

Display data, and the display data that interweaves are received with the first frequency of external clock；

Interleaved display data writing according to the distributor of second frequency self-supporting in the future interleaving technology of external clock is more A fifo fifo memory；

The multiple figures of interleaved display data writing from FIFO memory are deposited in response to the third frequency of internal clocking Reservoir；And

The interleaved display data of graphic memory is scanned to image real time transfer block in response to internal clocking,

Wherein second frequency is equal to or higher than the frequency obtained by the quantity of first frequency divided by interleaved display data,

Wherein third frequency higher than second frequency and is less than first frequency.