CN102768819B - OLED (organic light emitting diode) real-time display driving control system and control method thereof - Google Patents
OLED (organic light emitting diode) real-time display driving control system and control method thereof Download PDFInfo
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Abstract
The invention relates to an OLED (organic light emitting diode) real-time display driving control system which comprises a video decoding module, a video processor and a video memory. Video signals are inputted through an input end of the video decoding module, an output end of the video decoding module is connected with the video processor which is connected with the video memory, an output end of the video processor is connected with an OLED display module, an FPGA (field programmable gate array) serves as the video processor, and an SRAM (static random access memory) serves as the video memory. The control method of the OLED real-time display driving control system includes four portions of video decoding module initialization, video acquisition, video storage and video displaying, and the four portions are in cooperative operation under the control of the video processor to finally realize real-time display of video images on the OLED display module. The FPGA is used as the video processor while the SRAM is used as the video memory, data processing speed can be greatly increased by the aid of the control method, and the OLED real-time display driving control system has real-time processing and video image information storing capacities to enable the OLED to play dynamic video images in real time.
Description
Technical field
The present invention relates to a kind ofly carry out for controlling OLED display device the control method that the driving control system that shows in real time and this system adopt.
Background technology
OLED(organic electroluminescent LED) be a kind of electroluminescent display device, produce luminescent effect by the current drives organic material that flows through screen, so belong to the light-emitting component of current drives.OLED technology is a kind of novel flat panel display, compare with the flat panel display LCD of current main flow, the advantages such as OLED technology has that energy consumption is little, visible angle is large, volume is little, fast response time, all solid state, wide working temperature environment, be used widely in number demonstration field at present, and along with constantly improving of theoretical research and updating of manufacturing process, there is greatly replacement LCD technology to become the trend of flat pannel display mainstream technology.
Traditional OLED display driver control program adopts single-chip microcomputer as microprocessor, adopts flash as image information memory.The data processing speed of single-chip microcomputer and the read or write speed of flash are all difficult to meet video image processing requirements at a high speed, and this just causes the OLED can only repeat playing in the time of displaying video image, cannot carry out real-time dynamic play.
Summary of the invention
The object of this invention is to provide a kind of control method that the driving control system that shows in real time and this system adopt of can driving OLED carrying out.
For achieving the above object, the technical solution used in the present invention is:
The real-time display drive control system of a kind of OLED, realize in real time and showing for driving OLED display module, it comprises video decode module, video processor, video memory, vision signal is inputted by the input end of described video decode module, the output terminal of described video decode module is connected with described video processor, described video memory is connected with described video processor, the output terminal of described video processor is connected with described OLED display module, described video processor adopts FPGA, and described video memory adopts SRAM.
Preferably, described video memory comprises two video storage modules, and described video storage module is connected with described video processor respectively.
A control method for the real-time display drive control system of above-mentioned OLED, it comprises
(1) video decode module initialization: in the time that the real-time display drive control system of described OLED starts, described video processor carries out initial configuration to each register in described video decode module;
(2) video acquisition: when after described video decode module initialization configuration successful, if described video decode module detects vision signal at its input end, described decoding video signal is processed backward described video processor output digit signals and several synchronous reference signals by described video decode module, and described video processor gathers the image information of every two field picture in described digital signal;
Described synchronous reference signal comprises parity field marking signal, field synchronization reference signal, row synchronous reference signal, pixel clock; Video decode module described in setting inputs in the digital signal of described video processor, and the resolution of every two field picture is m × n; In the time gathering the image information of a two field picture, the high level interval of described parity field marking signal and low level interval odd field and the even field of a corresponding two field picture respectively, in described odd field or described even field, in the time that described field synchronization reference signal is high level, the view data of n valid pixel in m/2 pixel column in the odd field described in described video processor gathers or described even field, each pixel column; In the valid interval of the high level of each described field synchronization reference signal, described row synchronous reference signal has the valid interval of m/2 high level, and in the valid interval of the high level of each described row synchronous reference signal, comprise n described pixel clock, at the rising edge of each described pixel clock, described video processor gathers the view data of each valid pixel;
(3) video storage: the image information that described video processor is collected writes taking frame as unit in described video memory; The resolution that writes every two field picture of described video memory is a × b(a≤m, b≤n);
Storage space in described video memory is divided into at least a storage sets, in each described storage sets, comprises at least b storage unit; Write enable signal when effective when described video memory, the view data of the valid pixel in every two field picture writes in the storage unit of described video memory, when described video memory write enable signal when invalid, described video processor is prepared the view data of next valid pixel that is about to write and the address of corresponding storage unit in described video memory;
Described address comprises the group address of the storage sets of locating storage unit place, the element address of storage unit position in the storage sets at its place, location; Described group address comprises the high address being produced by effective linage-counter and the low order address being produced through phase inverter by described parity field marking signal, in the valid interval of described field synchronization reference signal, described effective linage-counter starts counting at the rising edge of described row synchronous reference signal, and zero clearing after the full a/2 number of meter; Described element address is produced by valid pixel counter, and in the valid interval of described row synchronous reference signal, described valid pixel counter starts counting at the rising edge of described pixel clock, and zero clearing after the full b number of meter;
(4) video shows: after the driving chip of the OLED display module inside to described is configured, described video processor reads the image information in described video memory and exports to described OLED display module and dynamically shows.
Preferably, in described video decode module initialization process, described video processor carries out initial configuration by iic bus to the register in described video decode module, when each described register is carried out to initial configuration, first described video processor sends the address that sends described video decode module after start signal, described video decode module detects when address that described video processor sends is identical with himself address, described video decode module sends the first answer signal, described video processor receives the address of transmitting the register that needs access after the first described answer signal, behind the address of the register described in described video decode module receives, send the second answer signal, described video processor transmits the data that need to be written to described register after receiving the second described answer signal, described video decode module transmits the 3rd answer signal after receiving described data, described video processor sends the transmission of position of rest end data after receiving described trisponder.
Preferably, in described video acquisition process, adopt state machine to carry out overall control to this process; Under original state, in the time that described state machine detects that described parity field marking signal is low level, it enters the second state; Under the second described state, in the time that described state machine detects that described parity field marking signal is high level, it enters the third state; Under the described third state, in the time that described state machine detects that described field synchronization reference signal is high level, it enters the 4th state; Under the 4th described state, in the time that described row synchronous reference signal is high level, described image information is gathered, in the time that described state machine detects that described field synchronization reference signal is low level, it enters the 5th state; Under the 5th described state, in the time that described state machine detects that described field synchronization reference signal is high level, it enters the 6th state; Under the 6th described state, in the time that described row synchronous reference signal is high level, described image information is gathered, in the time that described state machine detects that described field synchronization reference signal is low level, it gets back to described original state.
Preferably, (a < m in the time that the resolution of every two field picture in the digital signal of the video processor described in the video decode module by described transfers to is greater than the resolution that is write the every two field picture in described video memory by described video processor, when b < n), the enable signal of writing of controlling described video memory is that the x frequency division (x is positive integer) of described pixel clock makes the resolution of the image described in every frame be reduced to a ' × b ' by m × n, wherein a '=(m/x), b '=(n/x); If a ' > a, when b ' > b, extract in the capable pixel column of front a, the capable pixel column of this of every two field picture before b valid pixel realize the reduction of image resolution ratio.
Preferably, in the time that the described video memory in the real-time display drive control system of described OLED comprises the video storage module described in two, the image information of adjacent two two field pictures alternately deposits in the video storage module described in two, and alternately from the video storage module described in two, reads described image information.
Preferably, driving chip to described OLED display module inside is configured, and comprises and specifies the image of data transmission format and the transmission bit wide of OLED display module, the image demonstration start address of specifying directions X and termination address, appointment Y-direction to show start address and termination address.
Because technique scheme is used, the present invention compared with prior art has following advantages: the present invention adopts FPGA as video processor, adopt SRAM as video memory, and combination controlling method, can greatly improve data processing speed, possess the ability of real-time processing and store video images information, make OLED can play in real time dynamic video image.
Brief description of the drawings
Accompanying drawing 1 is the system framework figure of the real-time display drive control system of OLED of the present invention.
Accompanying drawing 2 is the process flow diagram of video processor initial configuration video decode module register in the control method of the real-time display drive control system of OLED of the present invention.
Accompanying drawing 3 is the graph of a relation of valid pixel and row synchronous reference signal in the control method of the real-time display drive control system of OLED of the present invention.
Accompanying drawing 4 is the graph of a relation of valid pixel and pixel clock signal in the control method of the real-time display drive control system of OLED of the present invention.
Accompanying drawing 5 is the view of state machine in the control method of the real-time display drive control system of OLED of the present invention.
In the control method that accompanying drawing 6 is the real-time display drive control system of OLED of the present invention, write SRAM sequential chart.
Accompanying drawing 7 is the logic diagram of the writing address signal generator of video memory in the control method of the real-time display drive control system of OLED of the present invention.
Accompanying drawing 8 is the flow for displaying figure of OLED display module in the control method of the real-time display drive control system of OLED of the present invention.
Embodiment
Below in conjunction with embodiment shown in the drawings, the invention will be further described.
Embodiment mono-: the real-time display drive control system of a kind of OLED, realize in real time and showing for driving OLED display module.Shown in accompanying drawing 1.It comprises video decode module, video processor, video memory, vision signal is inputted by the input end of video decode module, the output terminal of video decode module is connected with video processor, video memory is connected with video processor, the output terminal of video processor is connected with OLED display module, video processor adopts FPGA, and video memory adopts SRAM.Video memory comprises two video storage modules, and video storage module is independently SRAM of phase, and video storage module is connected with video processor FPGA respectively.
The control method of the real-time display drive control system of above-mentioned OLED specifically comprises that video decode module initialization, video acquisition, video storage, video show four major parts, each several part co-ordination under the control of video processor FPGA, finally realizes video image and shows in real time on OLED display module.
(1) video decode module initialization: in the time of the real-time display drive control system electrifying startup of OLED, video processor FPGA carries out initial configuration to each register in video decode module.
Decoder module adopts SAA7111A chip, and its inside comprises 32 registers, and the various functions of this chip is all by these 32 register controls.In video decode module initialization process, video processor FPGA carries out initial configuration by iic bus to the register in video decode module, and video processor FPGA is as main equipment, and video decode module is as from equipment.Iic bus is made up of data line SDA and clock line SCL, and under mode standard, message transmission rate is 100kbit/s.When each register is carried out to initial configuration, shown in accompanying drawing 2, first video processor FPGA sends start signal, then the address that sends video decode module (comprises 7 bit address codes and a W/R, here be 0x48H), in the time that video decode module detects that address that video processor FPGA sends is identical with himself address, video decode module sends the first responsion signal Ack; Video processor FPGA receives the address of transmitting the register that needs access after the first responsion signal Ack, and video decode module sends the second answer signal after receiving the address of register; Video processor FPGA transmits the data that need to be written to register after receiving the second answer signal, video decode module transmits the 3rd answer signal after receiving data, video processor FPGA receives the 3rd answer signal and represents transmission success, then sends the transmission of position of rest end data.
(2) video acquisition: when after video decode module initialization configuration successful, video decode module enters duty.If video decode module detects the analog video signal of PAL-system at its input end, after video decode module is processed by its inner AD conversion and decoding, to digital signal and several synchronous reference signals of video processor FPGA output rgb format.In order accurately to extract the image information of every two field picture, synchronous reference signal comprises parity field marking signal RTS0, field synchronization reference signal VREF, row synchronous reference signal HREF, pixel clock LLC2, and wherein, the frequency of pixel clock LLC2 is 13.5MHz.
Set video decode module and input in the digital signal of video processor FPGA, the resolution of every two field picture is m × n, in the present embodiment, and taking resolution as 576 × 720 as example.Video processor FPGA gathers the image information of every two field picture in digital signal.In the time gathering the image information of a two field picture, shown in accompanying drawing 3 and accompanying drawing 4, the high level interval of parity field marking signal RTS0 and low level interval odd field and the even field of a corresponding two field picture respectively, its rising edge represents the beginning of a two field picture.In odd field or even field, when synchronous reference signal VREF is high level then and there, video processor FPGA gathers the view data of n valid pixel (being 720 valid pixels of every row) in m/2 the pixel column (i.e. 288 pixel columns) in odd field or even field, each pixel column, and the low level corresponding fields black-out intervals of field synchronization reference signal VREF.Specifically, in the valid interval of the high level of each field synchronization reference signal VREF, row synchronous reference signal HREF has the valid interval of m/2 (288) high level, m/2 (288) pixel column in corresponding odd field or even field respectively, and the low level corresponding row black-out intervals of row synchronous reference signal HREF.While is in the valid interval of the high level of each row synchronous reference signal HREF, comprise n (720) pixel clock, at the rising edge of each pixel clock, video processor FPGA gathers the view data of each valid pixel, thereby gathers the image information of each two field picture.
In above-mentioned image acquisition process, the most important thing is accurately to determine beginning and the finish time of each frame image information, therefore, adopt state machine to carry out overall control to this process.Shown in accompanying drawing 5, under original state, in the time that state machine detects that parity field marking signal RTS0 is low level (RTS0=0), it enters the second state; Under the second state, when detecting parity field marking signal RTS0, state machine while being high level (RTS0=1), represents that a new two field picture starts, it enters the third state; Under the third state, in the time that state machine detects that field synchronization reference signal VREF is high level (VREF=1), represent the first field picture data at hand, it enters the 4th state; Under the 4th state, the synchronous reference signal HREF that is expert at gathers image information while being high level (HREF=1), in the time that state machine detects that field synchronization reference signal VREF is low level (VREF=0), represent the first field picture ED, it enters the 5th state; Under the 5th state, in the time that state machine detects that field synchronization reference signal VREF is high level (VREF=1), indicate the second field picture data at hand, it enters the 6th state; Under the 6th state, the synchronous reference signal HREF that is expert at gathers image information while being high level (HREF=1), in the time that state machine detects that field synchronization reference signal VREF is low level (VREF=0), represent the second field picture ED, it gets back to original state, prepares for detecting next frame image information.Can know accurately beginning and the finish time of a two field picture by these six states, for the accurate reproduction of later image ready.
(3) video storage: the image information that video processor FPGA is collected writes in video memory SRAM taking frame as unit.The resolution that setting writes every two field picture of video memory SRAM is a × b(a≤m, b≤n).In the present embodiment, adopt the OLED display module of lining by line scan that resolution is 128 × 160, therefore, the resolution that writes every two field picture of video memory SRAM is 128 × 160.Now, in the time of data writing, need carry out resolution decreasing processing to each two field picture.
Shown in accompanying drawing 6, A[14:0] be the address wire of video memory SRAM, DATA[15:0] be the data line of video memory SRAM.Video memory SRAM is writing the rising edge sampled data DATA[15:0 of enable signal WE], therefore video processor FPGA is ready to data and its corresponding address at the negative edge of writing enable signal WE.The x frequency division that enable signal WE is pixel clock LLC2 (x is positive integer) of writing of controlling video memory SRAM makes the resolution of every two field picture be reduced to a ' × b ' by m × n, wherein a '=(m/x), b '=(n/x).In the present embodiment, writing enable signal WE is four frequency divisions of pixel clock LLC2, and every four pixels are got a pixel, and on this basis, every four pixel columns are got a pixel column, the resolution of image can be reduced to 255 × 180 by 576 × 720.The image resolution ratio now obtaining is still greater than the resolution of OLED display module, therefore, need further reduce resolution processes.Now, b valid pixel before extracting in the capable pixel column of front a, the capable pixel column of this of every two field picture, extract front 160 valid pixels of front 128 pixel columns of each two field picture, each pixel column, be further the resolution 128 × 160 of OLED display module the decrease resolution of image, realize the reduction of image resolution ratio.
While writing SRAM, because the view data of the digital signal of video decode module output adopts interleaved mode, the pixel behavior the 0th of odd field scanning, 2,4,6,, 126 row, the pixel behavior the 1st of even field scanning, 3,5,7,, 127 row, and the OLED that native system adopts is progressive-scan format, so will go interlacing processing to the view data of interlacing, to adapt to the requirement of OLED display module, this just should be noted that the generting machanism of writing fashionable address signal.
Storage space in video memory SRAM is divided into at least a storage sets, in each storage sets, comprises at least b storage unit.Write enable signal WE when effective as video memory SRAM, the view data of the valid pixel in every two field picture writes in the storage unit of video memory SRAM successively, when video memory SRAM write enable signal WE when invalid, video processor FPGA prepares the view data of next valid pixel that is about to write and the address of corresponding storage unit in video memory SRAM.
Address comprises the group address of the storage sets of locating storage unit place, the element address of storage unit position in the storage sets at its place, location, and wherein group address is the high position in address, and element address is the low level in address.Shown in accompanying drawing 7, group address comprises the high address being produced by effective linage-counter and the low order address being produced through phase inverter by parity field marking signal RTS0.In the valid interval (VREF=1) of synchronous reference signal VREF on the scene, be effectively the expert at rising edge of synchronous reference signal HREF of linage-counter starts counting, and zero clearing after the full a/2 number of meter.Like this, in conjunction with field synchronization reference signal VREF through phase inverter and the low order address that produces, just can ensure in institute's write data bits during odd field in storage space the 0th, 2,4,6, (a-2) in individual storage group, and during even field institute's write data bits in storage space the 1st, 3,5,7 ..., (a-1) in individual storage group.And element address is produced by valid pixel counter, in the valid interval (HREF=1) of the synchronous reference signal HREF that is expert at, valid pixel counter starts counting at the rising edge of pixel clock LLC2, and zero clearing after the full b number of meter.
In conjunction with the present embodiment, video memory SRAM employing capacity is the chip that 256k × 16Bit, access maximal rate are 100MHz.And the size of the image that OLED display module shows is 20k × 16 Bit.In video memory SRAM, take out the storage space of 32k, be divided into 128 storage sets, and each storage sets is distributed 256 storage unit.When storage, a storage sets of the corresponding video memory SRAM of the one-row pixels of OLED display module.Realize the conversion being interlaced to line by line, as long as 64 row view data of strange field interval collection are deposited in to the 0th, 2 successively, 4 ..., 126 groups of storage sets, 64 row view data of even field interval collection are deposited in to the 1st successively, 3,5 ... in 127 groups of storage sets, like this, in video memory SRAM, the view data of 0-127 group storage sets is capable with regard to the 0-127 of a corresponding two field picture, has formed a complete progressive scanning picture.256 storage unit in every group of storage sets have only taken 160, although some waste, through such processing, has been simplified de-interlaced circuit structure greatly.
Storage unit is by address wire A[14:0] position wherein A[14:8] be group address, the storage sets at storage unit place, location, A[7:0] be element address, the position of location storage unit in the storage sets at its place.When synchronous reference signal VREF on the scene is high level (VREF=1), effectively the be expert at rising edge of synchronous reference signal HREF of linage-counter starts counting, and produce high 6 A[14:9 in the writing address signal of video memory SRAM], when full 64 pixels of meter, effectively linage-counter zero clearing.When the synchronous reference signal HREF that is expert at is high level (HREF=1), valid pixel counter starts counting at the rising edge of pixel clock LLC2, and produce the least-significant byte A[7:0 in the writing address signal of video memory SRAM], when full 160 pixels of meter, valid pixel counter O reset.Using the anti-phase parity field marking signal RTS0 rear A[8 as video memory SRAM writing address signal], the storage unit that has ensured the data of writing during odd field is positioned at the 0th, 2,4 ... in 126 groups of storage sets, during even field, the storage unit of the data of writing is positioned at the 1st, 3, and 5,, in 127 groups of storage sets.
In order to solve the conflict that view data after treatment is write to video storage module and obtains view data from video storage module, the video memory SRAM of native system adopts two physically two adjacent two field pictures of SRAM video storage module stores independently.These two video storage modules are alternately in being write and the state of being read, and the image information of adjacent two two field pictures alternately deposits in two modules, and alternately by reading image information in two image processing modules.Specific implementation process is as follows: first video storage module is stored up the first two field picture at the first image frame grabber cycle memory, within the second image frame grabber cycle, export the first two field picture, at the 3rd image frame grabber cycle memory storage the 3rd two field picture, within the 4th image frame grabber cycle, export the 3rd two field picture, the rest may be inferred.And second video storage module just started working in the time that the second two field picture arrives, store up the second two field picture at the second image frame grabber cycle memory, within the 3rd image frame grabber cycle, export the second two field picture, at the 4th image frame grabber cycle memory storage the 4th two field picture, within the 5th image frame grabber cycle, export the 4th two field picture, the rest may be inferred.So just realize two frame handover mechanisms, although just shown after image time delay one frame that this method makes to gather, can not omit any frame image information.
(4) video shows: OLED display module adopts chromatic display, and its inside carries driving chip, makes the interface of itself and video processor FPGA comparatively simple.First the driving chip of OLED display module inside is configured, comprises and specify the image of data transmission format and the transmission bit wide of OLED display module, the image demonstration start address of specifying directions X and termination address, appointment Y-direction to show start address and termination address.After configuration, video processor FPGA reads the image information in video memory SRAM and exports to OLED display module and dynamically shows, its flow process is referring to shown in accompanying drawing 8.
The real-time display drive control system of above-mentioned OLED and control method tool thereof have the following advantages:
(1) simple in structure, cost is low, easy to implement.
For acquisition and display how to realize analog video signal, traditional scheme uses simulation resolution element in a large number, not only comparatively complicated, and is difficult to debugging.The present invention adopts integrated circuit (IC) design, and peripheral analog device is few, and volume is little, simple in structure.The design of employing universal elements, components and parts used are easy to buying, and cost is low, easy to implement.
(2) use flexibly, amendment is convenient.
Can require to customize corresponding software according to user, for example, will change image display mode, can be by Configuration brightness of image, contrast, picture amplitude, the isoparametric adjusting of display direction of amendment video decoding chip and OLED.
(3) real-time online of having realized vision signal is play.
Because FPGA is hardware circuit work, its job specification is similar to the multithreading operation in programming, to all parallel carrying out of the processing of data, has the ability of processing High-speed video images data.The present invention has realized vision signal real-time acquisition and display, makes the OLED display module can be with the Speed display image of 25 frames per second, picture clear and smooth.
Above-described embodiment is only explanation technical conceive of the present invention and feature, and its object is to allow person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, within all should being encompassed in protection scope of the present invention.
Claims (7)
1. the real-time display drive control system of OLED, realize in real time and showing for driving OLED display module, it comprises video decode module, video processor, video memory, vision signal is inputted by the input end of described video decode module, the output terminal of described video decode module is connected with described video processor, described video memory is connected with described video processor, the output terminal of described video processor is connected with described OLED display module, it is characterized in that: described video processor adopts FPGA, described video memory adopts SRAM, described OLED display module is the OLED display module of lining by line scan,
The control method that the real-time display drive control system of described OLED adopts comprises:
(1) video decode module initialization: in the time that the real-time display drive control system of described OLED starts, described video processor carries out initial configuration to each register in described video decode module;
(2) video acquisition: when after described video decode module initialization configuration successful, if described video decode module detects vision signal at its input end, described decoding video signal is processed backward described video processor output digit signals and several synchronous reference signals by described video decode module, and described video processor gathers the image information of every two field picture in described digital signal;
Described synchronous reference signal comprises parity field marking signal, field synchronization reference signal, row synchronous reference signal, pixel clock; Video decode module described in setting inputs in the digital signal of described video processor, and the resolution of every two field picture is m × n; In the time gathering the image information of a two field picture, the high level interval of described parity field marking signal and low level interval odd field and the even field of a corresponding two field picture respectively, in described odd field or described even field, in the time that described field synchronization reference signal is high level, the view data of n valid pixel in m/2 pixel column in the odd field described in described video processor gathers or described even field, each pixel column; In the valid interval of the high level of each described field synchronization reference signal, described row synchronous reference signal has the valid interval of m/2 high level, and in the valid interval of the high level of each described row synchronous reference signal, comprise n described pixel clock, at the rising edge of each described pixel clock, described video processor gathers the view data of each valid pixel;
(3) video storage: the image information that described video processor is collected writes taking frame as unit in described video memory; The resolution that writes every two field picture of described video memory is a × b(a≤m, b≤n);
Storage space in described video memory is divided into at least a storage sets, in each described storage sets, comprises at least b storage unit; Write enable signal when effective when described video memory, the view data of the valid pixel in every two field picture writes in the storage unit of described video memory, when described video memory write enable signal when invalid, described video processor is prepared the view data of next valid pixel that is about to write and the address of corresponding storage unit in described video memory;
Described address comprises the group address of the storage sets of locating storage unit place, the element address of storage unit position in the storage sets at its place, location; Described group address comprises the high address being produced by effective linage-counter and the low order address being produced through phase inverter by described parity field marking signal, in the valid interval of described field synchronization reference signal, described effective linage-counter starts counting at the rising edge of described row synchronous reference signal, and zero clearing after the full a/2 number of meter; Described element address is produced by valid pixel counter, and in the valid interval of described row synchronous reference signal, described valid pixel counter starts counting at the rising edge of described pixel clock, and zero clearing after the full b number of meter;
(4) video shows: after the driving chip of the OLED display module inside to described is configured, described video processor reads the image information in described video memory and exports to described OLED display module and dynamically shows.
2. the real-time display drive control system of OLED according to claim 1, is characterized in that: described video memory comprises two video storage modules, and described video storage module is connected with described video processor respectively.
3. the real-time display drive control system of OLED according to claim 1, it is characterized in that: in described video decode module initialization process, described video processor carries out initial configuration by iic bus to the register in described video decode module, when each described register is carried out to initial configuration, first described video processor sends the address that sends described video decode module after start signal, described video decode module detects when address that described video processor sends is identical with himself address, described video decode module sends the first answer signal, described video processor receives the address of transmitting the register that needs access after the first described answer signal, behind the address of the register described in described video decode module receives, send the second answer signal, described video processor transmits the data that need to be written to described register after receiving the second described answer signal, described video decode module transmits the 3rd answer signal after receiving described data, described video processor sends the transmission of position of rest end data after receiving the 3rd described answer signal.
4. the real-time display drive control system of OLED according to claim 1, is characterized in that: in described video acquisition process, adopt state machine to carry out overall control to this process; Under original state, in the time that described state machine detects that described parity field marking signal is low level, it enters the second state; Under the second described state, in the time that described state machine detects that described parity field marking signal is high level, it enters the third state; Under the described third state, in the time that described state machine detects that described field synchronization reference signal is high level, it enters the 4th state; Under the 4th described state, in the time that described row synchronous reference signal is high level, described image information is gathered, in the time that described state machine detects that described field synchronization reference signal is low level, it enters the 5th state; Under the 5th described state, in the time that described state machine detects that described field synchronization reference signal is high level, it enters the 6th state; Under the 6th described state, in the time that described row synchronous reference signal is high level, described image information is gathered, in the time that described state machine detects that described field synchronization reference signal is low level, it gets back to described original state.
5. the real-time display drive control system of OLED according to claim 1, it is characterized in that: (a < m in the time that the resolution of every two field picture in the digital signal of the video processor described in the video decode module by described transfers to is greater than the resolution that is write the every two field picture in described video memory by described video processor, when b < n), the enable signal of writing of controlling described video memory is that the x frequency division (x is positive integer) of described pixel clock makes the resolution of the image described in every frame be reduced to a ' × b ' by m × n, wherein a '=(m/x), b '=(n/x), if a ' > a, when b ' > b, extract in the capable pixel column of front a, the capable pixel column of this of every two field picture before b valid pixel realize the reduction of image resolution ratio.
6. the real-time display drive control system of OLED according to claim 2, it is characterized in that: in the time that the described video memory in the real-time display drive control system of described OLED comprises the video storage module described in two, the image information of adjacent two two field pictures alternately deposits in the video storage module described in two, and alternately from the video storage module described in two, reads described image information.
7. the real-time display drive control system of OLED according to claim 1, it is characterized in that: the driving chip to described OLED display module inside is configured, comprise and specify the image of data transmission format and the transmission bit wide of OLED display module, the image demonstration start address of specifying directions X and termination address, appointment Y-direction to show start address and termination address.
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| CN103065587B (en) * | 2012-12-28 | 2016-01-20 | 富顺光电科技股份有限公司 | A kind of LED synchronous display controlling system without sending card |
| CN103472748B (en) * | 2013-09-04 | 2017-01-18 | 上海顺久电子科技有限公司 | Verification system and method of sequential control circuit |
| FR3048293B1 (en) * | 2016-02-29 | 2018-07-06 | Sagemcom Broadband Sas | METHOD FOR PROGRAMMING AN ANIMATION DURING THE STARTING PHASE OF AN ELECTRONIC DEVICE AND ASSOCIATED ELECTRONIC DEVICE |
| CN106556407A (en) * | 2016-11-22 | 2017-04-05 | 天津驰华科技有限公司 | A kind of nearest gas station's travel route prompt system under oil mass detection |
| CN106934758B (en) * | 2017-03-01 | 2019-08-27 | 南京大学 | A kind of three-dimensional image video real time integrating method and system based on FPGA |
| CN106961570A (en) * | 2017-03-20 | 2017-07-18 | 中航华东光电有限公司 | The de-interlaced system of vision signal and processing method based on FPGA |
| CN113132651B (en) * | 2020-01-15 | 2023-04-11 | 西安诺瓦星云科技股份有限公司 | Image processing method and device and display control system |
| CN111757036A (en) * | 2020-07-08 | 2020-10-09 | 深圳市洲明科技股份有限公司 | Horizontal mirror image display method and device based on FPGA |
| CN112153447B (en) * | 2020-09-27 | 2022-06-14 | 海信视像科技股份有限公司 | Display device and sound and picture synchronous control method |
| CN112565679A (en) * | 2020-11-03 | 2021-03-26 | 合肥工业大学 | Monitoring method and monitoring device based on machine vision |
| CN112967666B (en) * | 2021-02-24 | 2022-07-15 | 南京磊积科技有限公司 | LED display screen control device and control method capable of realizing random pixel arrangement |
| CN116778857B (en) * | 2023-08-22 | 2023-11-07 | 联士光电（深圳）有限公司 | Input signal polarity self-adapting circuit in micro display panel |
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| CN1987972B (en) * | 2005-12-23 | 2010-12-29 | 上海广电电子股份有限公司 | Video frequency driving system and its method for organic light emitting diode display screen |
| CN1988432B (en) * | 2006-12-27 | 2010-05-19 | 中国科学院上海光学精密机械研究所 | Full-digital space optical communication array signal diversity receiving system |
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Effective date of registration: 20180813 Address after: 233030 2016 Tang He road, Bengbu, Anhui Patentee after: Huadong Photoelectric Integrated Device Research Institute Address before: 215163 No. 89 Longshan Road, hi tech Zone, Suzhou, Jiangsu Patentee before: China North Industries Group Corporation No.214 Research Institute Suzhou R&D Center |