CN103472748B - Verification system and method of sequential control circuit - Google Patents
Verification system and method of sequential control circuit Download PDFInfo
- Publication number
- CN103472748B CN103472748B CN201310398070.2A CN201310398070A CN103472748B CN 103472748 B CN103472748 B CN 103472748B CN 201310398070 A CN201310398070 A CN 201310398070A CN 103472748 B CN103472748 B CN 103472748B
- Authority
- CN
- China
- Prior art keywords
- control circuit
- sequential control
- iic bus
- functional module
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a verification system and method of a sequential control circuit. The verification system of the sequential control circuit comprises a field-programmable gate array which is used for setting up the sequential control circuit to be verified and an IIC bus controller. The IIC bus controller is connected to the sequential control circuit and is used for receiving testing instructions from an IIC bus debugging interface and analyzing the testing instructions, and reading-writing operation instructions generated by analyzing are sent to the sequential control circuit. The sequential control circuit receives and executes the reading-writing operation instructions. The verification system further comprises the IIC bus debugging interface which is connected to the IIC bus controller, and the IIC bus debugging interface receives the input testing instructions and transmits the testing instructions to the IIC bus controller. According to the sequential control circuit verification mode based on the field-programmable gate array, the IIC bus controller of hardware is achieved, soft supporting is of no need, a CPU module is of no need, and a quick and convenient debugging method is achieved.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of checking system of sequential control circuit and
A kind of verification method of sequential control circuit.
Background technology
Sequential control circuit (tcon) is the important module in display device, be drive circuit in display device (for example
Source driving circuit, gate drive circuit and vcom Polarity Control) timing control signal is provided, and view data is processed
(frc, od etc.), thus realize simulating the display control of rgb signal.Display floater due to different manufacturers, different series uses
Different source driving circuits and gate drive circuit, therefore corresponding timing control signal will be variant, and tcon chip needs to meet
The requirement of compatible polymorphic type display floater.
Before tcon chip is by flow, tcon function need to be verified.In the proof procedure of tcon chip, Ke Yitong
Cross the compatibility to verify tcon for the depositor debugging each module in tcon chip.In order to flexible regulation modules
Depositor is it is necessary to one kind conveniently debud mode.A lot of systems are had to adopt jtag interface debugging, this mode needs first
Want system to possess support the cpu of this debugging interface, in addition must have the debugger supporting this debugging interface and debug soft
Part, therefore has many restrictions；Another conventional debud mode is by uart interface debugging depositor, and this kind of mode needs
Hardware debugging acid simple (rs232-ttl keyset), the debugging interface selected also simple, and most system all can
Leave uart interface, but if necessary to debug the depositor of all modules of tcon chip internal, be necessary for being in tcon chip
The cpu in portion works together, and runs uart drive software, the initial stage verified in tcon, such as when individually verifying certain module, just
Cpu must be added, cpu be configured normal work simultaneously, also will write uart drive software, just can be debugged, this is undoubtedly
Workload and the difficulty of debugging can be increased, increase debug time.
Content of the invention
In order to solve above-mentioned technical problem, the present invention proposes a kind of checking system of new sequential control circuit and checking
Method, based on field-programmable gate array, realizes the iic bus control unit of hardware it is not necessary to software support is it is not required that embed
Cpu module, simplifies debugging process.
In view of this, according to an aspect of the present invention it is proposed that a kind of checking system of sequential control circuit, including existing
Field programmable gate array, for building sequential control circuit to be verified, described scene logic gate array is additionally operable to build iic total
Lane controller, described iic bus control unit connects to described sequential control circuit, is derived from iic bus debugging interface for receiving
Test instruction and described test instruction is parsed, the read-write operation instruction that generates of parsing is sent to described sequencing contro
Circuit；Described sequential control circuit is used for receiving and execute described read-write operation instruction；Described checking system also includes: described
Iic bus debugging interface, connects to described iic bus control unit, described test is simultaneously referred to by the described test instruction of receives input
Order is transmitted to described iic bus control unit.
Because field programmable gate array (fpga) is a kind of semidefinite inhibition and generation circuit, achievable combination logic function, may be used again
Realize the basic logic unit module of sequential logic function.Value in depositor determines this logic list in logical units for storage
Connecting mode between the logic function of unit and each module or between module and i/o, and finally determine what fpga was realized
Function, therefore, can build sequential control circuit and iic bus control unit (iic controller), so, institute using fpga
The sequential control circuit built and iic bus control unit are just made up of hardware completely, and the iic bus control unit built is not
Need internal processor it is not required that supporting software accordingly, at the chip checking initial stage, reaching upper computer software being capable of velocity modulation soon
The purpose of examination sequential control circuit, obtains data by the i2c Debugging interface of host computer it is not necessary to cpu executes software, works as tune
Die trial block changes, and only need to carry out slight variations it is not necessary to change debugging software in host computer interface setting, therefore reduce
The complexity of debugging, compared with the jtag interface and uart interface, more simple and fast.Secondly, iic bus is a kind of simple
Versabus, only two signals, implement signal, realize fairly simple, so, just can simplify whole checking system
Design architecture so that debugging process is more efficient and convenient, the debug time of timing controller is greatly reduced, also improves
The motility of debugging.
According to a further aspect in the invention it is also proposed that a kind of verification method of sequential control circuit, can be compiled using scene
Journey gate array builds sequential control circuit to be verified and iic bus control unit；Using iic bus debugging interface receives input
Test instruction is simultaneously transmitted described test instruction to described iic bus control unit；By described iic bus control unit to described survey
Examination instruction is parsed, and generates read-write operation instruction, receives for described sequential control circuit and execute.
Because field programmable gate array (fpga) is a kind of semidefinite inhibition and generation circuit, achievable combination logic function, may be used again
Realize the basic logic unit module of sequential logic function.Value in depositor determines this logic list in logical units for storage
Connecting mode between the logic function of unit and each module or between module and i/o, and finally determine what fpga was realized
Function, therefore, can build sequential control circuit and iic bus control unit (iic controller), so, institute using fpga
The sequential control circuit built and iic bus control unit are just made up of hardware completely, and the iic bus control unit built is not
Need internal processor it is not required that supporting software accordingly, at the chip checking initial stage, reaching upper computer software being capable of velocity modulation soon
The purpose of examination sequential control circuit, obtains data by the i2c Debugging interface of host computer it is not necessary to cpu executes software, works as tune
Die trial block changes, and only need to carry out slight variations it is not necessary to change debugging software in host computer interface setting, therefore reduce
The complexity of debugging, compared with the jtag interface and uart interface, more simple and fast.Secondly, iic bus is a kind of simple
Versabus, only two signals, implement signal, realize fairly simple, so, just can simplify whole checking system
Design architecture so that debugging process is more efficient and convenient, the debug time of timing controller is greatly reduced, also improves
The motility of debugging.
Brief description
Fig. 1 shows the schematic diagram of the checking system of sequential control circuit according to an embodiment of the invention；
Fig. 2 shows the circuit diagram that the fpga in Fig. 1 is built；
The flow chart that Fig. 3 shows the verification method of sequential control circuit according to an embodiment of the invention.
Specific embodiment
In order to be more clearly understood that the above objects, features and advantages of the present invention, below in conjunction with the accompanying drawings and specifically real
Mode of applying is further described in detail to the present invention.It should be noted that in the case of not conflicting, the enforcement of the application
Feature in example and embodiment can be mutually combined.
Elaborate a lot of details in the following description in order to fully understand the present invention, but, the present invention also may be used
To be implemented different from other modes described here using other, therefore, protection scope of the present invention is not described below
Specific embodiment restriction.
To describe the checking system of sequential control circuit according to an embodiment of the invention with reference to Fig. 1 and Fig. 2 in detail.
Fig. 1 shows the schematic diagram of the checking system of sequential control circuit according to an embodiment of the invention, and Fig. 2 shows in Fig. 1
The circuit diagram that fpga is built.
As shown in figure 1, the checking system of sequential control circuit according to an embodiment of the invention, two big portions can be included
Point, field programmable gate array 102 is total with checking circuit interface (alternatively referred to as tcon verifies circuit expansion board) 104, iic
Line debugging interface 1042 is arranged in checking circuit interface 104, wherein,
Field programmable gate array 102, be used for building sequential control circuit 1024 and iic bus control unit 1022(referring to
Fig. 2), sequential control circuit 1024 connects to iic bus control unit 1022, for receiving from iic bus control unit 1022
Read-write operation instructs, and executes the instruction of this read-write operation, and this iic bus control unit 1022 is used for receiving from the debugging of iic bus
The test instruction of interface 1042 simultaneously parses to this test instruction, and the read-write operation instruction that parsing is generated sends to sequential control
Circuit 1024 processed；Iic bus debugging interface 1042, connects to above-mentioned field programmable gate array 102, will be inputted by host computer 10
Test instruction send the iic bus control unit 1022 built to field programmable gate array 102, and by field programmable gate
The implementing result of the sequential control circuit 1024 that array 102 is built is transmitted to authentication unit (such as display screen 12), existing to determine
Whether the sequential control circuit 1024 that field programmable gate array 102 is built is correct.
Because field programmable gate array (fpga) 102 is a kind of semidefinite inhibition and generation circuit, achievable combination logic function, and
The basic logic unit module of achievable sequential logic function.Value in depositor determines this logic in logical units for storage
Connecting mode between the logic function of unit and each module or between module and i/o, and finally determine fpga and realized
Function, therefore, can be using fpga building sequential control circuit 1024 and iic bus control unit (iic controller)
1022, so, the sequential control circuit 1024 built and iic bus control unit 1022 are just made up of hardware completely, and institute
The iic bus control unit 1022 built does not need internal processor it is not required that supporting software accordingly, therefore with jtag interface
And uart interface compares, more simple and fast.So, the design architecture of whole checking system can just be simplified so that debugging process
More efficient and convenient, the debug time of timing controller is greatly reduced, also improves the motility of debugging.
As can be known from Fig. 1, checking circuit interface 104 can also include power module (i.e. power module) 1048, for for
Display screen 12, checking circuit interface 104 are powered.In addition, checking circuit interface 104 can also include: Low Voltage Differential Signal
Input interface 1044 and Low Voltage Differential Signal output interface (for example, mini-lvds output interface) 1046, are connected to iic bus
Between controller 1022 and display screen 12, by this Low Voltage Differential Signal input interface 1044, the viewdata signal inputting is passed
Transport to sequential control circuit 1024 to process, by this Miniature low voltage differential signal output interface 1046 by sequential control circuit 1024
The driving display signal transmission processing output is to display screen 12.Same to sequential control circuit inputting viewdata signal
When, can be configured by the value of the depositor in the functional module to sequential control circuit for the iic bus debugging interface, thus changing
Become the image procossing mode of sequential control circuit, for example, a two field picture is divided into left and right half screen image to swap display, or
The image of odd column and even column is carried out changing display, in this way, it is possible to realize the integrity authentication scheme of tcon function.Change speech
It, after tentatively putting up sequential control circuit and iic bus control unit, enter in the driveability to sequential control circuit
During row debugging, can input image data signal, and instruct by debugging interface input test, instruct in host computer 10 input test
After (comprising the instruction that depositor is configured), if the display effect of display screen falling flat, can adjust at scene
The sequential control circuit (i.e. adjustment test instruction, reconfigures to the depositor in fpga) that fpga is built, until reach
To Expected Results, thus can the sequential control circuit built of fast verification obtain preferable sequential control circuit.
Specifically, with reference to Fig. 1, in order to increase the bright degree of liquid crystal TV set display, preferably apparent color, it is right to need
The brightness of liquid crystal TV set display carries out gamma correction.These, be required for by carrying out to liquid crystal TV set display
The physical attribute of gamma(display) correct to complete, therefore checking circuit interface 104 can also include: gamma correction circuit
10410, for being corrected to the brightness of display screen.
With reference to Fig. 2, the sequential control circuit 1024 that field programmable gate array 102 is built has multiple functional modules, example
As video processing module, random access memory controller module etc., wherein video processing module may include module of overdriving again
(overdrive), the functional module such as scaler (scaler), data compression decompression, therefore field programmable gate array 102 is built
Iic bus control unit 1022 be additionally operable to by described read-write operation instruction send to sequential control circuit correspond to specify function
The functional module of module's address, to complete to the configuration corresponding to the depositor specifying register address in the corresponding function module,
Wherein it is intended that functional module address and specified register address are parsings, described test instruction obtains.
Described iic bus control unit 1022 is additionally operable to send read-write operation instruction and corresponds to described sequential control circuit
In the functional module of specified functional module address, read in described functional module corresponding to the depositor specifying register address
Value, and export the value of this depositor by iic bus debugging interface, to obtain the work state information of described functional module.
Wherein, each functional module in the sequential control circuit 1024 that field programmable gate array 102 is built passes through system
Bus (for example, apb bus) connects to iic bus control unit 1022.
In other words, tcon chip internal comprises much individual functional modules, " video processing module ", " the internal memory control in such as Fig. 2
Device module processed ", " module n " etc., each module has corresponding one group of depositor, can realize mould by configuring these depositors
The change of block function is it is also possible to read the feedback information that some of which status register obtains module working condition.
As can be seen that the present invention realizes a kind of hardware using few logical block in fpga from above-described embodiment
Iic controller(iic bus control unit), this module can receive the iic data that host computer is sent by debugging acid
Stream, and parsing of the data stream is out executed the read-write operation to certain functional module in sequential control circuit 1024, each function
Module has different address spaces, such as a1 during video processing module corresponding address, and random access memory controller module is correspondingly
Location is a2.
It should be noted that, iic universal serial bus typically has two holding wires, and one is two-way data wire sda, and another is
Clock line scl.Serial data line sda on all each equipment being connected to iic bus is all connected on the sda of bus, each equipment
Clock line scl is connected on the scl of bus, such as in sequential control circuit 1024, the data wire of each functional module is connected to iic
Data wire in bus, the clock of each functional module is all connected to the clock line scl of the data wire in iic bus.Sequencing contro
Each functional module in circuit 1024 passes through system bus, such as apb(advanced with iic bus control unit 1022
Peripheral bus) bus links together, as shown in Figure 2.Apb bus is the amba bus specification released by arm company
One kind, it has also become structure on a kind of popular industrial standard piece.Iic bus control unit 1022 by existing apb bus and when
Each module in sequence control circuit 1024 is connected, and is also based on simplifying the consideration of design, can accelerate debugging progress simultaneously.
Operationally, the test instruction that host computer sends over is parsed by iic controller, translates into and meets
The read-write operation of apb bus timing, thus complete the configuration to the depositor of each functional module in sequential control circuit 1024.Right
For host computer 10, by this iic bus control unit (iic controller) it is possible to each functional module is regarded as not
Same slave device, the different device address of each functional module distribution, functional module internal distribution
register address.Device address and register that host computer 10 is sent by iic controller
Address translates into the address in apb bus address space, when read-write operation being translated as Read-write Catrol in apb bus simultaneously
Sequence.
For example, host computer Debugging interface is communicated with the iic controller within fpga by iic bus, iic
The read write command of the depositor that host computer is sended over by controller parses, when being found according to device address
Corresponding function module in sequence control circuit, finds the correspondence in this corresponding function module according to register address and deposits
Device, thus configure to corresponding registers.
So-called master device refers to the transmission (sending enabling signal) of log-on data, sends clock signal and biography
The equipment of stop signal is sent, in the present embodiment, host computer is master device at the end of sending.By master device
The equipment looked for is referred to as slave device.
Therefore, if only verified to certain functional module in sequential control circuit 1024, by the survey after parsing
Examination instructs the functional module sending to specifying address, if necessary to verify to multiple functional modules simultaneously, will need same
When the address of the plurality of functional module is provided.In this way, it is possible to realize the debugging of individual feature module and multiple functional modules
Combined debugging, and unlike uart interface debugging mode, in independent certain functional module of checking, need built-in process
Device, also will write uart drive software it will be apparent that accelerating debugging speed, and reduces debugging complexity.
Therefore, before tcon chip flow, by the auxiliary based on fpga platform, realize hardware integration inside fpga total
Line traffic control module, adds the checking system of the present invention, can compare true, comprehensively tcon function is verified, and iic
Bus is a kind of simple versabus, only two signals, implements fairly simple.
Next combine the verification method according to the sequential control circuit of the present invention for Fig. 3 explanation.
As shown in figure 3, the verification method of sequential control circuit according to an embodiment of the invention, following walking can be included
Rapid: step 302, build sequential control circuit and iic bus control unit using field programmable gate array；Step 304, uses
The test instruction of iic bus debugging interface receives input is simultaneously transmitted test instruction to iic bus control unit；Step 306, passes through
Iic bus control unit parses to test instruction, generates read-write operation instruction, receives for sequential control circuit and execute, can
To be transmitted the implementing result of sequential control circuit to authentication unit by iic bus debugging interface, to determine field-programmable
Whether the sequential control circuit that gate array is built is correct.
Because field programmable gate array (fpga) is a kind of semidefinite inhibition and generation circuit, achievable combination logic function, may be used again
Realize the basic logic unit module of sequential logic function.Value in depositor determines this logic list in logical units for storage
Connecting mode between the logic function of unit and each module or between module and i/o, and finally determine what fpga was realized
Function, therefore, can build sequential control circuit and iic bus control unit (iic controller), so, institute using fpga
The sequential control circuit built and iic bus control unit are just made up of hardware completely, and the iic bus control unit built is not
Need internal processor it is not required that supporting software accordingly, at the chip checking initial stage, reaching upper computer software being capable of velocity modulation soon
The purpose of examination sequential control circuit, obtains data by the i2c Debugging interface of host computer it is not necessary to cpu executes software, works as tune
Die trial block changes, and only need to carry out slight variations it is not necessary to change debugging software in host computer interface setting, therefore reduce
The complexity of debugging, compared with the jtag interface and uart interface, more simple and fast.Secondly, iic bus is a kind of simple
Versabus, only two signals, implement signal, realize fairly simple, so, just can simplify whole checking system
Design architecture so that debugging process is more efficient and convenient, the debug time of timing controller is greatly reduced, also improves
The motility of debugging.
After tentatively putting up sequential control circuit and iic bus control unit, in the driving to sequential control circuit
When performance is debugged, can input image data signal, and instructed by debugging interface input test, input in host computer 10 and survey
After examination instruction (comprising the instruction that depositor is configured), if the display effect of display screen falling flat, can show
The sequential control circuit (i.e. adjustment test instruction, reconfigures to the depositor in fpga) that field adjustment fpga is built,
Till producing a desired effect, thus can the sequential control circuit built of fast verification obtain preferable sequencing contro
Circuit.
It is preferred that being sent out the instruction of described read-write operation by described iic bus control unit in any of the above-described technical scheme
Deliver in described sequential control circuit and correspond to the functional module specifying functional module address, to complete in described functional module
Corresponding to the configuration of the depositor specifying register address, wherein, described sequential control circuit is made up of n functional module, institute
State the integer that n is more than or equal to 1, described specified functional module address and described specified register address are to parse described test to refer to
Order obtains.Each functional module has corresponding address space, can be easy to position each functional module and in each functional module
Depositor configured, the independent debugging of achievable functional module or the combined debugging of multiple functional module.
It is preferred that being sent out the instruction of described read-write operation by described iic bus control unit in any of the above-described technical scheme
Deliver to and in described sequential control circuit, correspond to the functional module specifying functional module address, right in described functional module to read
Should be in the value of the depositor of specified register address；Export the value of described depositor by described iic bus debugging interface, to obtain
Take the work state information of described functional module.
It is preferred that being connected described n functional module to described using system bus in any of the above-described technical scheme
Iic bus control unit.
It is preferred that being inputted by the Low Voltage Differential Signal in described checking circuit interface in any of the above-described technical scheme
The viewdata signal of input is transmitted and processes to described sequential control circuit by interface, by micro- in described checking circuit interface
Described sequential control circuit is processed the driving display signal transmission of output to display screen by type Low Voltage Differential Signal output interface.?
During checking sequential control circuit, can be by viewdata signal to sequential control circuit, outputing signal to sequential control circuit
By the display effect observing display screen, display screen, can determine whether whether the sequential control circuit currently built is correct, if not just
Really, can be configured by the depositor in the logical block to field programmable gate array for the iic bus debugging interface, thus changing
Become function, complete the debugging to sequential control circuit.
In an embodiment according to the present invention, iic bus control unit is realized it is not necessary to software support completely by hardware, no
Need embedded cpu module, simplify adjustment method, simplified the design of fpga checking system, make the debugging of individual module and many
The combined debugging of individual module is more smooth, reduces debug time.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, made any repair
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of checking system of sequential control circuit, including field programmable gate array, for building sequential control to be verified
Circuit processed is it is characterised in that described scene logic gate array is additionally operable to build iic bus control unit, described iic bus control unit
Connect to described sequential control circuit, the test for receiving from iic bus debugging interface instructs and to described test instruction
Parsed, the read-write operation instruction that parsing is generated sends to described sequential control circuit；
Described sequential control circuit is used for receiving and execute described read-write operation instruction；
Described checking system also includes: described iic bus debugging interface, connects to described iic bus control unit, receives input
Described test instruction is simultaneously transmitted described test instruction to described iic bus control unit.
2. sequential control circuit according to claim 1 checking system it is characterised in that described sequential control circuit by
N functional module composition, described iic bus control unit will be right in described read-write operation instruction transmission extremely described sequential control circuit
Should be in the functional module of specified functional module address, to complete to specify register address to post to corresponding in described functional module
The configuration of storage, wherein, described n is the integer more than or equal to 1, described specified functional module address and described specified depositor ground
Location is that parsing described test instruction obtains.
3. sequential control circuit according to claim 1 and 2 checking system it is characterised in that described iic controller also
For the instruction of described read-write operation is sent to described sequential control circuit corresponding to the function mould specifying functional module address
Block, to read the value corresponding to the depositor specifying register address in described functional module；
Described iic bus debugging interface is additionally operable to export the value of described depositor.
4. the checking system of sequential control circuit according to claim 2 is it is characterised in that described n functional module is led to
Cross system bus to connect to described iic bus control unit.
5. the checking system of sequential control circuit according to claim 1 is it is characterised in that also include:
Low Voltage Differential Signal input interface and Low Voltage Differential Signal output interface, are connected to described iic bus control unit and display
Between screen, by described Low Voltage Differential Signal input interface, the viewdata signal of input is transmitted to described sequential control circuit
Process, the driving that described sequential control circuit processes output is shown by signal transmission by described Low Voltage Differential Signal output interface
To described display screen.
6. a kind of verification method of sequential control circuit is it is characterised in that include:
Build sequential control circuit to be verified and iic bus control unit using field programmable gate array；
Instructed using the test of iic bus debugging interface receives input and line traffic control total to described iic is transmitted in described test instruction
Device processed；
By described iic bus control unit, described test instruction is parsed, generate read-write operation instruction, for described sequential control
Circuit processed receives and executes.
7. the verification method of sequential control circuit according to claim 6 is it is characterised in that by the total line traffic control of described iic
Device processed sends to described sequential control circuit the instruction of described read-write operation corresponding to the function mould specifying functional module address
Block, to complete to the configuration corresponding to the depositor specifying register address in described functional module,
Wherein, described sequential control circuit is made up of n functional module, and described n is the integer more than or equal to 1, described specified work(
Energy module's address and described specified register address are that parsing described test instruction obtains.
8. the verification method of the sequential control circuit according to claim 6 or 7 is it is characterised in that by described iic bus
Controller sends to described sequential control circuit the instruction of described read-write operation corresponding to the function of specifying functional module address
Module, to read the value corresponding to the depositor specifying register address in described functional module；
Export the value of described depositor by described iic bus debugging interface.
9. the verification method of sequential control circuit according to claim 7 is it is characterised in that will be described using system bus
N functional module connects to described iic bus control unit.
10. sequential control circuit according to claim 6 verification method it is characterised in that debugging when, by low pressure
The viewdata signal of input is transmitted and processes to described sequential control circuit by differential signal input interface, is believed by low-voltage differential
Described sequential control circuit is processed the driving display signal transmission of output to display screen by number output interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310398070.2A CN103472748B (en) | 2013-09-04 | 2013-09-04 | Verification system and method of sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310398070.2A CN103472748B (en) | 2013-09-04 | 2013-09-04 | Verification system and method of sequential control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103472748A CN103472748A (en) | 2013-12-25 |
| CN103472748B true CN103472748B (en) | 2017-01-18 |
Family
ID=49797639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310398070.2A Active CN103472748B (en) | 2013-09-04 | 2013-09-04 | Verification system and method of sequential control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103472748B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942379B (en) * | 2014-04-14 | 2017-05-24 | 大连东软信息学院 | All-digital silicon controlled rectifier controller chip for three-phase alternating-current voltage regulation and rectification |
| CN104407956A (en) * | 2014-12-03 | 2015-03-11 | 天津大学 | IIC bus experimental facility debugged by serial port |
| CN104866423B (en) * | 2015-05-20 | 2018-04-20 | 中国科学院空间应用工程与技术中心 | The test method and system of a kind of software configuration item |
| CN105635721B (en) * | 2015-12-29 | 2018-07-13 | 深圳Tcl数字技术有限公司 | Eliminate the method and display terminal of display terminal three-dimensional crosstalk |
| CN107240371B (en) * | 2017-08-07 | 2019-06-21 | 四川长虹电器股份有限公司 | A kind of multi-screen ginseng driving data Correctness checking method of tconless screen |
| CN108414918B (en) * | 2018-02-26 | 2021-04-23 | Tcl华星光电技术有限公司 | Compatibility testing device and method |
| CN108346404B (en) * | 2018-03-05 | 2020-11-24 | 昆山龙腾光电股份有限公司 | Parameter debugging method for time schedule controller and screen driving circuit |
| CN109669872A (en) * | 2018-12-24 | 2019-04-23 | 郑州云海信息技术有限公司 | A kind of verification method and device |
| CN110223652B (en) * | 2019-06-10 | 2021-08-24 | 北海惠科光电技术有限公司 | Time schedule controller control method, time schedule controller and drive circuit |
| CN110060653B (en) * | 2019-06-10 | 2021-08-24 | 北海惠科光电技术有限公司 | Drive circuit control method and device and drive circuit |
| CN111027108B (en) * | 2019-08-13 | 2024-02-13 | 安天科技集团股份有限公司 | Sequential logic safety detection method and device for low-speed synchronous serial bus |
| CN110956913B (en) * | 2019-11-21 | 2022-07-26 | Tcl华星光电技术有限公司 | Time sequence controller verification system and time sequence controller verification method |
| CN112559275A (en) * | 2020-09-08 | 2021-03-26 | 中国银联股份有限公司 | Integrated circuit, method for maintenance debugging of an integrated circuit and interface circuit |
| CN113849433B (en) * | 2021-09-14 | 2023-05-23 | 深圳市昂科技术有限公司 | Execution method and device of bus controller, computer equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201374060Y (en) * | 2008-12-16 | 2009-12-30 | 康佳集团股份有限公司 | IIC bus expanded system structure |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102682684A (en) * | 2012-05-29 | 2012-09-19 | 东南大学 | Method for measuring quality of dynamic image of liquid crystal display |
| CN102768819A (en) * | 2012-07-17 | 2012-11-07 | 中国兵器工业集团第二一四研究所苏州研发中心 | OLED (organic light emitting diode) real-time display driving control system and control method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6883109B2 (en) * | 2001-07-30 | 2005-04-19 | Hewlett-Packard Development Company, L.P. | Method for accessing scan chains and updating EEPROM-resident FPGA code through a system management processor and JTAG bus |
-
2013
- 2013-09-04 CN CN201310398070.2A patent/CN103472748B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201374060Y (en) * | 2008-12-16 | 2009-12-30 | 康佳集团股份有限公司 | IIC bus expanded system structure |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102682684A (en) * | 2012-05-29 | 2012-09-19 | 东南大学 | Method for measuring quality of dynamic image of liquid crystal display |
| CN102768819A (en) * | 2012-07-17 | 2012-11-07 | 中国兵器工业集团第二一四研究所苏州研发中心 | OLED (organic light emitting diode) real-time display driving control system and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103472748A (en) | 2013-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103472748B (en) | Verification system and method of sequential control circuit | |
| US8195442B2 (en) | Use of hardware peripheral devices with software simulations | |
| CN103105684A (en) | Test method, device, system and test equipment of liquid crystal display module | |
| US20130050159A1 (en) | Gate driver and display device therewith | |
| JP2006189785A (en) | Gamma voltage generating apparatus and method of testing gamma voltage | |
| US8963937B2 (en) | Display controller driver and testing method thereof | |
| TW201725577A (en) | Driver and operation method thereof | |
| US20170261554A1 (en) | Methods and systems for generating functional test patterns for manufacture test | |
| CN103412841A (en) | Driver and driving method for CPCI (Compact Peripheral Component Interconnect) bus RS422 communication module under VxWorks operating system | |
| JP2007058596A (en) | Verification simulator and verification simulation method | |
| US20100082315A1 (en) | Interface between a verification environment and a hardware acceleration engine | |
| KR20160128538A (en) | Display device | |
| WO2012172976A1 (en) | Semiconductor integrated device, display device, and debugging method for semiconductor integrated device | |
| CN102110473B (en) | Method and system for programming and checking EDID (Extended Display Identification Data) of display device | |
| CN106657986A (en) | Testing device and testing method for HDMI interface | |
| US20070129920A1 (en) | Automated simulation testbench generation for serializer/deserializer datapath systems | |
| Navaneethan et al. | Image Display using FPGA with BRAM and VGA Interface for Multimedia Applications | |
| CN106055505B (en) | The transmission method of data in optical module and optical module | |
| US20050055190A1 (en) | Circuit operation verification device and method | |
| US8330746B2 (en) | Addressing method and structure for multiple chips and display system thereof | |
| KR20120140619A (en) | Column drivers with embedded high-speed video interface timing controller | |
| TWI539431B (en) | Method for source driving circuit and display device | |
| CN106448602A (en) | Medical display device | |
| TWI497481B (en) | Transmission method for display device | |
| JP4561533B2 (en) | Verification simulator and verification simulation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160729 Address after: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Applicant after: Qingdao Hisense Electric Co., Ltd. Address before: 266071 Shandong city of Qingdao province Jiangxi City Road No. 11 Applicant before: Qingdao Hisense Xinxin Technology Co., Ltd. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20161128 Address after: 201203 68 Pudong New Area Road, Shanghai, 7, building 2, Hua Tuo Applicant after: HUAYA MICROELECTRONICS (SHANGHAI) CO.,LTD. Address before: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Applicant before: Qingdao Hisense Electric Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |