CN110390909A - Synchronous control circuit for display - Google Patents
Synchronous control circuit for display Download PDFInfo
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- CN110390909A CN110390909A CN201810578438.6A CN201810578438A CN110390909A CN 110390909 A CN110390909 A CN 110390909A CN 201810578438 A CN201810578438 A CN 201810578438A CN 110390909 A CN110390909 A CN 110390909A
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- 230000001360 synchronised effect Effects 0.000 title claims abstract description 37
- 239000000872 buffer Substances 0.000 claims abstract description 121
- 230000005540 biological transmission Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000003139 buffering effect Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of synchronous control circuit for display, comprising: multiple buffers, wherein the buffer is to show data to store the multiple portions in the different data channel in a bridgt circuit；And a control circuit, the data to control each buffer are written and reading data.The control circuit is that the ready for data signal exported according to the specific buffers in the buffer shows one or more sequence controllers of data into a display with the part for controlling the buffer while output is stored, and allows one or more sequence controllers simultaneously on a display panel of the display whereby while scanning the different piece of same horizontal line.
Description
Technical field
The present invention relates to control circuit, in particular to a kind of synchronous control circuit for display.
Background technique
In traditional bridgt circuit, display data can be received by main control end, and be converted to mobile industry processor interface
Serial interface (the Display Serial of the display of (Mobile Industry Processor Interface, MIPI)
Interface, DSI) display data, and export to display panel sequence controller.However, traditional bridgt circuit is in benefit
Show that data to time of sequence controller and asynchronous, but have the time difference with different data channel translator unit.If different
When the time difference that the part of data channel shows data transmission to sequence controller is more than a predetermined threshold, sequence controller is connect
The part of each data channel received shows that data have nonsynchronous situation, this will lead to the display element in display panel not
It is correctly turned on, such as red, green or blue lines can be generated on a display panel, implied that lines tear (line
Tearing) the case where, generates.
Therefore, it is necessary to a kind of synchronous control circuits for display to solve the above problems.
Summary of the invention
The present invention is to provide a kind of synchronous control circuit for display, comprising: multiple buffers, wherein the buffering
Device is to show data to store the multiple portions in the different data channel in a bridgt circuit；And a control circuit,
Data to control each buffer are written and reading data.The control circuit is according to the specific buffering in the buffer
The ready for data signal that device is exported is to control the buffer while the part that is stored of output shows data to one aobvious
Show one or more sequence controllers in device, allows one or more sequence controllers simultaneously in a display surface of the display whereby
The different piece of same horizontal line is scanned on plate simultaneously.
Detailed description of the invention
Fig. 1 is the block diagram for showing the display system in an embodiment according to the present invention.
Fig. 2 is the functional-block diagram for showing the buffer in an embodiment according to the present invention.
Fig. 3 is the timing diagram for showing the synchronous control circuit in an embodiment according to the present invention.
Description of symbols:
100~display system；
110~main control end；
120~bridgt circuit；
125~synchronous control circuit；
121-122~buffer；
121A-121B, 122A-122B~buffer；
123~control circuit；
150,151,152~sequence controller；
160~display panel；
170~display；
CLK~clock pins CLK；
DATA_IN~data-out pin；
WRITE_EN~write-in enable pin；
READ_EN~reading enable pin；
DATA_RDY~data ready pin；
DATA_OUT~data output pins；
FIFO_EMPTY~vague and general data pin；
T1-t10~time；
MIPI_IN~display data signal；
Hs_d_en_o~receiving end high-speed data enable signal；
Capture_en~acquisition enable signal；
D_hs_rdy_o~transmission end (Tx) high-speed data enable signal；
Rd_data_vld~reading data valid signal；
Fifo00_empty, fifo01_empty~signal.
Specific embodiment
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, a preferred embodiment is cited below particularly, and match
Detailed description of the invention is closed, is described in detail below.
Fig. 1 is the block diagram for showing the display system in an embodiment according to the present invention.In one embodiment, display system
100 include a main control end 110, a bridgt circuit 120, buffer 121 and 122, one control circuit 123, time schedule controller
150 and a display panel 160.Main control end 110 may be, for example, a PC, and (can for example, be shown by a coffret
End (DisplayPort) interface) it will show that data (for example, RGB pixel data) is sent to bridgt circuit 120.Bridgt circuit
120 be by received display data be converted to the multiple portions of the serial interface of display of mobile industry processor interface of meeting
Divide display data, wherein each section shows that data are to be stored respectively in corresponding buffer, and pass through in MIPI DSI interface
Corresponding data channel (data lane) is to be respectively sent to sequence controller 150.For example, control circuit 123 and buffering
Device 121-122 is to can be described as a synchronous control circuit 125, and control circuit 123 is to control the data write-in of buffer 121 and 122
And it reads.It is with the electric connection of MIPI DSI interface, wherein MIPI between synchronous control circuit 125 and sequence controller 150
DSI interface includes a clock lane (clock lane) and one or more data channel.
Bridgt circuit 120 is that the part in buffer 121 and 122 is synchronously shown that data pass through MIPI DSI respectively and connect
Different data channel in mouthful is sent to sequence controller 150.Each data channel is, for example, with the communication of differential serial
The mode of (differential serial communication) carries out data transmission.For example, wherein data channel 00
And data channel 01 is to correspond respectively to buffer 121 and 122.
In one embodiment, bridgt circuit 120, buffer 121 and 122 and control circuit 123 can for example be led with an application
To integrated circuit (application-specific integrated circuit, ASIC) or a field programmable lock battle array
Column (Field-Programmable Gate Array, FPGA) are realized, but the present invention is not limited thereto.
Sequence controller 151 and 152 can control the display panel respectively 160 the display element of different zones timing, and
Sequence controller 151 and 152 is that the part in received different data channel is shown that data are shown in display panel
Corresponding display area in 160.In some embodiments, sequence controller 151 and 152 is to be integrated into single a timing control
Device 150.
In one embodiment, display panel 160 may be, for example, a liquid crystal (liquid crystal) display panel or one have
Machine light emitting diode (organic light-emitting diode) display panel, and sequence controller 151 and 152 be can be with
Display panel 160 is integrated into a display 170, a for example, head-mounted display (head-mounted display, HMD).
It is to be understood that for ease of description, the MIPI DSI interface in the display system 100 in Fig. 1 is with 2 numbers
It is illustrated according to channel, but the present invention is not limited thereto, such as bridgt circuit 120 uses greater number (such as 2 or more)
Data channel with respectively output par, c show data, then can configure corresponding buffer, such as data in each data channel
Channel 00 and data channel 01 are to correspond respectively to buffer 121 and 122.For example, if the resolution ratio of display panel 160 is cured
High (such as 4K or 8K resolution ratio), single data is coupled (link) and can not bear so big operand, therefore can will show
Data are divided into multiple portions and show data, and transmit corresponding part display data, and each data using multiple Data Associations
Being coupled includes multiple data channel, and the buffer of the corresponding synchronous control circuit in each channel and sequence controller can carry out accordingly
Synchronization and display processing.
Specifically, the MIPI DSI interface in the present invention is not limited to 2 data channel, visual display panel 160
Resolution ratio is to configure the Data Association and data channel of different number.
The timing of data is shown in the part in the different data channel that the transmission end (Tx) of traditional bridgt circuit is exported
Not necessarily synchronous.If the time sequence difference that the part in different data channel shows data transmission to sequence controller 150 is super
When crossing a predetermined threshold, the part of each data channel received by sequence controller 150 shows that data have nonsynchronous feelings
Condition, this will lead to the display element in display panel and is improperly turned on, such as can generate the line of red green or blue
Item on a display panel, the case where having implied that lines tearing generation.
Fig. 2 is the functional-block diagram for showing the buffer in an embodiment according to the present invention.In one embodiment, buffer
121 include buffer 121A-121B, and buffer 122 includes buffer 122A-122B, implies that buffer 121 and 122
Design as ping-pong buffers can be described as buffer group.Because synchronous control circuit 125 needs to be received by main control end 110 simultaneously
Show data, and by the corresponding part display data of each data channel synchronization output to sequence controller 151 and 152, therefore can
Data are carried out by one of buffer of ping-pong buffers (such as buffer 121A-121B or buffer 122A-122B)
Write-in, and data output is carried out by another buffer.A horizontal line is often changed, then the buffer of data write-in and data output
Role can also exchange, so can avoid the same buffer data output while have the case where data write-in.
By taking the picture of 4K resolution ratio as an example, resolution ratio is, for example, 4096x2160, and every horizontal line has 4096 pictures
Element.In this example, horizontal 1st~2048 pixel of odd number article can be stored in buffer 121A by bridgt circuit 120, and
Horizontal 2049th~4096 pixel of odd number article is stored in buffer 122A.Bridgt circuit 120 can be horizontal by even number item
1st~2048 pixel of line is stored in buffer 121B, and horizontal 2049th~4096 pixel of even number article is stored
In buffer 122B.
In one embodiment, buffer 121A-121B and 122A-122B for example can be respectively with a first in first out (First-
In First-out, FIFO) buffer realized, imply that buffer 121 and 122 can be real with first in first out ping-pong buffers institute
It is existing.The input/output pin of buffer 121A and 121B has shown that in Fig. 2, and the pin of buffer 121B is and buffer
121A is identical.
By taking buffer 121A as an example, the input pin of buffer 121A is for example including clock pins CLK, data-out pin
DATA_IN, write-in enable pin WRITE_EN, enable pin READ_EN is read.Output pin for example, data ready draws
Foot DATA_RDY, data output pins DATA_OUT, vague and general data pin FIFO_EMPTY.It is to be understood that in the present invention
The input/output pin of each buffer is not limited thereto.
For example, the input signal 21A of the clock pins CLK of buffer 121A is received from bridgt circuit 120
The clock signal of clock lane, the input signal 22A of data-out pin DATA_IN are from the corresponding of bridgt circuit 120
The display data of data channel.Input signal 23A and 24A are by control circuit 123 and corresponding control signal and index
(point) it carries out logical operation and obtains.
The fifo00_empty signal that the vague and general data pin FIFO_EMPTY of buffer 121A is exported indicates buffering
Whether valid data are also stored in device 121A.If so, then fifo00_empty signal is low logic state；If it is not, then fifo00_
Empty signal is high logic state.The data output pins DATA_OUT of buffer 121A is output display data d_lane00.
The data ready pin DATA_RDY of buffer 121A is output GPO_SYNC signal.
Similarly, input signal 21B~24B of buffer 121B and output signal fifo01_empty, d_lane01 and
GPO_SYNC signal is to can refer to buffer 121A.
When being intended to be written display data to buffer 121A, the enable pin WRITE_EN of buffer 121A need to be high logic
State implies that synchronous control circuit 125 need to switch to high-speed data mode (high speed data mode) first to receive and
From the data of bridgt circuit 120, such as receiving end (Rx) high-speed data enable signal hs_d_en_o is high logic state, and with
The relevant acquisition enable signal capture_en of buffer 121A need to be high logic state.When synchronous control circuit 125 will acquire
When enable signal capture_en is switched to low logic state, i.e. stopping data write-in, and change write-in index to be directed toward buffering
Device 121B.Because display data need to be written in the buffer 121A and 121B in ping-pong buffers in turn, so when being intended to be written next
When the display data of line, synchronous control circuit 125 can write data into buffer 121B.When being intended to that the display of next line is written down
When data, synchronous control circuit 125 can write data into buffer 121A, and so on.
When synchronous control circuit 125 is intended to read data from buffer 121A, last in synchronous control circuit 125
A buffer (need to be by the data ready pin DATA_RDY of buffer 122A) the GPO_SYNC signal exported in this example
High logic state, and transmission end high-speed data enable signal d_hs_rdy_o is high logic state.About buffer 121A and
The detailed operation of 121B will be described in detail in the embodiment of Fig. 3.
Fig. 3 is the timing diagram for showing the synchronous control circuit in an embodiment according to the present invention.As shown in figure 3, MIPI_IN
Signal is, for example, the display data signal from main control end.In time t0, MIPI_IN signal is that negative edge changes (high logic state
Convert to low logic state), synchronous control circuit 125 is by receiving end (Rx) high-speed data enable signal hs_d_en_o at this time
High logic state is changed into, and will acquire enable signal capture_en in time t1 and change into high logic state.Buffer
The write-in enable pin WRITE_EN of 121A is receiving end (Rx) high-speed data enable signal hs_d_en_o and obtains enable signal
Capture_en is carried out and lock (AND) operation, therefore data write-in, and buffer can be carried out to buffer 121A from time t1
The fifo00_empty signal of the vague and general pin FIFO_EMPTY output of the data of 121A can change into low logic by high logic state
State.It is noted that obtaining enable signal capture_en is according to the horizontal synchronizing signal from bridgt circuit 120
(horizontal sync signal) is determined, i.e. every horizontal horizontal synchronizing signal in display picture.
In time t2, synchronous control circuit 125 will acquire enable signal capture_en and change into low logic state.It is obtaining
When the negative edge of enable signal capture_en being taken to change, synchronous control circuit 125 is the write-in index (write for changing buffer
Pointer), i.e. the received next horizontal display data of institute can be written to buffer 121B.In time t1 between t2,
Display data from channel 00 are write buffer 121A, and the part that is stored buffer 121A show data can keep to
Time t4.
For example, in time t7, synchronous control circuit 125 is by transmission end (Tx) high-speed data enable signal d_hs_
Rdy_o changes into high logic state, and reading data valid signal rd_data_vld is also then changed into height in time t8 and is patrolled
The state of collecting.It implies that and starts to can read the data of buffer 121A in time t8, when time t4, the data of buffer 121A are empty
The fifo00_empty signal of weary pin FIFO_EMPTY output be changed to high logic state (i.e. in buffer 121A without times
What data).When fifo00_empty signal is in positive edge triggering, synchronous control circuit 125 is to change to read index (read
Pointer) with directed at buffer 121B.
Similarly, start in time t3 to time t5, the data of the data channel 00 from bridgt circuit 120 be written to
Buffer 121B.And start in time t3, the fifo01_ of the vague and general pin FIFO_EMPTY output of the data of buffer 121B
Empty signal is changed to low logic state (expression has started that data are written).
In time t9, synchronous control circuit 125 changes into transmission end (Tx) high-speed data enable signal d_hs_rdy_o
High logic state, and then high logic state is also changed by data valid signal rd_data_vld is read in time t10.Meaning
The data for starting to can read buffer 121B in time t8, when time t6, the vague and general pin of the data of buffer 121B
The fifo01_empty signal of FIFO_EMPTY output is changed to high logic state (i.e. without any number in buffer 121B
According to).When fifo01_empty signal is in positive edge triggering, synchronous control circuit 125 is to change to read index (read
Pointer) with directed at buffer 121A.
It is noted that the timing diagram in Fig. 3 is illustrated by taking buffer 121A and 121B as an example, buffer 122A
And 122B is controlled according to similar timing, difference is only that the data channel from bridgt circuit 120 is different, and
The GPO_SYNC signal that the data ready pin DATA_RDY of the last one buffer is exported can be with transmission end (Tx) high speed number
Passing through signal obtained by one and lock (AND gate) operation according to enable signal d_hs_rdy_o is rd_data_vld signal.
Because each buffer be designed in a manner of ping-pong buffers, therefore rd_data_vld signal can also with it is corresponding
The reading enable pin READ_EN of each buffer can be just input to after reading index progress logical operation.For ease of description, therefore
It is the reading enable pin READ_EN with rd_data_vld signal input buffer device 121A in Fig. 2.
It specifically, (is in the above-described embodiments (including the buffer 122A of buffer 122 because of the last one buffer
~122B)) it is the display data that storage shows a horizontal last part in data, because input data is to sweep in proper order
The mode taken aim at is transmitted and is stored, therefore the buffer before the last one buffer can first store completely corresponding part and show
Data.To each buffer energy synchronism output data, then after the data storage for needing the last one equal buffer, then by its
The GPO_SYNC signal that data ready pin DATA_RDY is exported changes into high logic state.If using more than two bufferings
Device can just change its data ready pin DATA_RDY institute after then the display data storage of equally the last one buffer such as need is full
The GPO_SYNC signal of output changes into high logic state.
Therefore, each buffer (such as buffer 121 and 122) in the present invention can be defeated by corresponding data channel synchronization
Data are to corresponding sequence controller (such as sequence controller 151 and 152) out, so that sequence controller 151 and 152 can be simultaneously
Corresponding horizontal line is scanned on starting display panel 160.
Though the present invention is disclosed as above with preferred embodiment, the range that however, it is not to limit the invention, any affiliated skill
Technical staff in art field, without departing from the spirit and scope of the invention, when a little variation and retouching, therefore this hair can be done
Bright protection scope is subject to view claim.
Claims (8)
1. a kind of synchronous control circuit for display, comprising:
Multiple buffers, wherein the buffer is multiple portions to store the different data channel in a bridgt circuit
Divide display data；And
One control circuit, the data to control each buffer are written and reading data；
Wherein the control circuit is the ready for data signal that is exported according to the specific buffers in the buffer to control
It makes the buffer while exporting the part stored and show one or more sequence controllers of data into a display, borrow
This allows one or more sequence controllers simultaneously on a display panel of the display while scanning the difference of same horizontal line
Part.
2. being used for the synchronous control circuit of display as described in claim 1, wherein the bridgt circuit is received from a master
Control end display data, and by institute it is received display data be converted to meet mobile industry processor interface display serially
The part of interface shows data.
3. being used for the synchronous control circuit of display as claimed in claim 2, wherein the synchronous control circuit is one or more with this
A sequence controller is to be electrically connected by MIPI DSI interface, and each section shows that data are corresponding by MIPI DSI interface
Each data channel to be exported simultaneously by each buffer to corresponding each sequence controller.
4. the synchronous control circuit of display is used for as claimed in claim 3, wherein each buffer is rattled by first in first out
Buffer is realized, and each buffer includes one first buffer and one second buffer.
5. the synchronous control circuit of display is used for as claimed in claim 4, wherein when what the specific buffers were exported is somebody's turn to do
Ready for data signal is high logic state, and a transmission end high-speed data enable signal of the synchronous control circuit is high logic shape
When state and a vague and general data pin of each buffer are low logic state, which is each buffer of control while exporting
Data are to corresponding each sequence controller.
6. the synchronous control circuit of display is used for as claimed in claim 4, wherein when a receiving end of the control circuit
(Rx) high-speed data enable signal changes into high logic state by low logic state, which is to obtain enable signal for one
High logic state is changed into, and the part in each channel from the bridgt circuit is shown that data are write according to the acquisition enable signal
Enter corresponding each buffer.
7. the synchronous control circuit of display is used for as claimed in claim 6, wherein one when the control circuit obtains enable
When signal changes into low logic state by high logic state, which is to change a write-in index of each buffer.
8. the synchronous control circuit of display is used for as claimed in claim 4, wherein when a vague and general data letter of each buffer
When number changing into high logic state by low logic state, which is to change the one of each buffer to read index.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107113705A TWI663591B (en) | 2018-04-23 | 2018-04-23 | Synchronization control circuit for display |
| TW107113705 | 2018-04-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110390909A true CN110390909A (en) | 2019-10-29 |
| CN110390909B CN110390909B (en) | 2021-03-12 |
Family
ID=67764640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810578438.6A Active CN110390909B (en) | 2018-04-23 | 2018-06-07 | Synchronous control circuit for display |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110390909B (en) |
| TW (1) | TWI663591B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113194347A (en) * | 2020-01-14 | 2021-07-30 | 海信视像科技股份有限公司 | Display device and multi-channel image content synchronization method |
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| JP3526019B2 (en) * | 1999-11-30 | 2004-05-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Image display system, image display device, and image display method |
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| TWI585741B (en) * | 2016-08-04 | 2017-06-01 | 友達光電股份有限公司 | Driving deice and driving method |
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| CN1728208A (en) * | 2004-07-30 | 2006-02-01 | 夏普株式会社 | Display device and driving method thereof |
| US20080111925A1 (en) * | 2006-11-14 | 2008-05-15 | Eiji Kato | Signal processing circuit and method |
| US20090322661A1 (en) * | 2008-06-25 | 2009-12-31 | Samsung Electronics Co., Ltd. | Display apparatus |
| CN103871344A (en) * | 2012-12-18 | 2014-06-18 | 三星显示有限公司 | Display device and driving method thereof |
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| CN113194347A (en) * | 2020-01-14 | 2021-07-30 | 海信视像科技股份有限公司 | Display device and multi-channel image content synchronization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110390909B (en) | 2021-03-12 |
| TWI663591B (en) | 2019-06-21 |
| TW201944389A (en) | 2019-11-16 |
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