CN102074205B - Liquid crystal display (LCD) controller and control method thereof - Google Patents
Liquid crystal display (LCD) controller and control method thereof Download PDFInfo
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- CN102074205B CN102074205B CN200910237490A CN200910237490A CN102074205B CN 102074205 B CN102074205 B CN 102074205B CN 200910237490 A CN200910237490 A CN 200910237490A CN 200910237490 A CN200910237490 A CN 200910237490A CN 102074205 B CN102074205 B CN 102074205B
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Abstract
The invention provides a liquid crystal display (LCD) controller and a control method thereof. The LCD controller comprises a microprocessor and an LCD control logic, wherein the LCD control logic is connected with the microprocessor through a serial peripheral interface (SPI) to realize the control of an LCD; and the LCD control logic is a programmable logic device. The microprocessor transmits display data to a complex programmable logic device (CPLD) through the SPI interface in a direct memory access (DMA) control mode; and the CPLD device generates required pixel clock signals, line synchronizing signals and frame synchronizing signals according to a timing sequence requirement of the LCD by using data signals and clock signals of the SPI interface so as to drive the LCD to display.
Description
Technical field
The invention relates to LCD (LCD) controller, particularly a kind of lcd controller and control method thereof.
Background technology
LCD is realized that graphic interface shows because the characteristics of its ultra-thin size, high brightness and high definition are applied in commercial unit and consumer products field widely.Especially in the application of embedded system, because most of embedded system has strict requirement to volume, so the LCD of ultra-thin size becomes the only choosing of most of embedded system.
For embedded system, existing LCD shows that the solution of control mainly contains:
1) uses special-purpose LCD control chip.Like the SED1335 of the fluffy display technique far away of the smart electricity in Beijing company limited, the SID13774 of Japanese Seiko Epson Corporation (EPSON) etc.These chips can be supported the LCD Presentation Function of multiple signal, but also abundant control device interface is provided, but the setting of these chips and all more complicated of programming receive hardware enclosure, volume, especially the constraint of cost simultaneously.
2) use the SOC chip of being with lcd controller, like the S 3C2410ARM chip of Korea S Samsung (SUMSANG), though this type chip integrated level is higher; Feature richness; But the interface type of the liquid crystal display of supporting is less, and to a large amount of wastes of other resources in the chip, has strengthened system cost.Define the range of choice of chip simultaneously.
Therefore, how above-mentioned prior art being solved, design the lcd controller that a kind of cost is low, volume is little, is the direction place of those skilled in the art institute desire research.
Summary of the invention
Fundamental purpose of the present invention provides a kind of lcd controller and control method thereof; It overcomes existing higher, the inflexible defective of control mode of LCD display part cost; The cost of the LCD part of tax control machine is reduced; Improve stability, the reliability of this part simultaneously, and possess control mode more flexibly.
Another object of the present invention provides a kind of lcd controller and control method thereof, though to processor A T91SAM9260 do not have built-in lcd controller, have the SPI interface of DMA transmission mode, and the speed of SPI interface has reached 100MHz.Owing to have the DMA transmission mode, this makes and through the SPI Data transmission time, needn't take a large amount of system resource.
A purpose more of the present invention provides a kind of lcd controller and control method thereof, and it has performance configurable, highly integrated, high scalability through the controller of PLD as LCD, can reduce the cost of system.
In order to achieve the above object, the present invention provides a kind of lcd controller, and it comprises a microprocessor and a LCD steering logic; Described LCD steering logic links to each other with said microprocessor through the SPI interface; Realization is to the control of LCD, and wherein, described LCD steering logic is a PLD.
In the preferable embodiment, described PLD is the CPLD device.
In the preferable embodiment; Described CPLD device links to each other with described microprocessor through three signal line; The data signal line MOS I that this three signal line is respectively the SPI interface, clock cable SPCK and video data frame synchronizing signal FRAMESYNC; Wherein, video data frame synchronizing signal FRAMESYNC is connected on a certain I/O mouth of said microprocessor 1.
In the preferable embodiment, described microprocessor is the microprocessor that has the SPI interface of DMA transmission mode.
In the preferable embodiment, the model of described microprocessor is AT91SAM9260.
In the preferable embodiment, described LCD screen is monochromatic screen or color line screen.
In the preferable embodiment, the model of described CPLD device is EPM240.
In order to achieve the above object, the present invention provides a kind of control method of lcd controller, is to realize through above-mentioned lcd controller, and it comprises the steps,
A: in the internal memory of microprocessor, open up one with the corresponding internal storage location of LCD as video memory;
B: the interruption and the DMA parameter of initiation parameter and this interface of said microprocessor SPI interface are set, start the DMA transmission;
C: after the DMA transmission first time of accomplishing the SPI interface, get into the interrupt service routine of SPI;
D: in the reference position of each frame, produce a rising edge signal, begin to inform the new frame data of CPLD in the video data frame synchronizing signal;
E: in CPLD, the video data frame synchronizing signal is caught;
F: in CPLD; Rising edge of clock signal at the SPI interface is gathered the data-signal of SPI interface; Simultaneously move into shift register to the data that get access to, and the clock signal of SPI interface is counted, on the data bus of the LCD that the data that receive are sent; Produce a pixel clock rising edge again, video data is sent to LCD;
G:CPLD counts pixel clock, produces line synchronizing signal;
H:CPLD counts line synchronizing signal, produces frame synchronizing signal.
In the preferable embodiment, said microprocessor is opened up one 526 * 286 internal storage location as video memory.
In the preferable embodiment, in step b, when the initiation parameter of SPI interface is set, make SPI be operated in top speed.
In the preferable embodiment, in step b, the SPI interface is produced after the DMA data transmission finishes interrupt; The start address that the DMA transmission is set simultaneously is the start address of video memory; The transmission byte number of DMA is the 64KB that the maximum of DMA transmission allows, and after setting finishes, starts the DMA transmission.
In the preferable embodiment; In the interrupt service routine of step c; Reset the address pointer and transmission counter of DMA transmission, and judge and currently need which part in the transmission one frame video data and when frame data begin, make the video data frame synchronizing signal produce rising edge.
In the preferable embodiment, each frame data is divided into three times to be transmitted, 65536 bytes of preceding twice transmission, and it transmits 526 * 286-2 * 65536=19364 byte for the last time for the greatest measure that the DMA transmission of each SPI interface is allowed.
In the preferable embodiment; In step e, when video data frame synchronizing signal rising edge, represent the beginning of a frame video data; All inner counter resets of CPLD this moment; Comprise pixel clock counter, line synchronizing signal counter, the frame synchronizing signal counter is promptly carried out the preparation that receives new frame data after resetting.
In the preferable embodiment, in step f, when using 8 looks, count down to 8, expression receives a byte; When using 16 looks, count down to 16, expression receives a byte.
Compared with prior art, beneficial effect of the present invention is:
1, through dma mode transmitting and displaying data, owing to have the DMA transmission mode, this makes and through the SPI Data transmission time, needn't take a large amount of system resource through the SPI interface of microprocessor in the present invention.
2, through dma mode transmitting and displaying data, CPLD utilizes the data-signal MOS I of SPI interface and clock signal SPCK to produce required data-signal and the control signal of LCD through the SPI interface of microprocessor in the present invention.Can support multiple TFT-LCD display resolution and color figure place; The resolution that can support is relevant with the transmission speed of microprocessor SPI interface with the color figure place; Like AT91SAM9260 for atmel corp; The SPI maximal rate of this chip is 100MHz, and can make resolution is that 4.3 cun LCD displays of 480 * 272 are operated in 16 looks.
3, the present invention designs the LCD display controller and only needs need not external any SRAM or SDRAM as video memory, and all logics only to have taken 79 logical blocks of CPLD in the external piece of CPLD of microprocessor again.Therefore this lcd controller possesses lower cost, and reliability is also higher.
4, owing to only need 3 signal wires between lcd controller that the present invention designed and the microprocessor, be convenient to PCB layout, be convenient to the control of electromagnetic interference (EMI).
5, can be through revising the LCD that CPLD program and microprocessor program adapt to different resolution and color.
Description of drawings
Fig. 1 forms synoptic diagram for lcd controller of the present invention;
Fig. 2 is the Organization Chart of lcd controller control LCD of the present invention;
Fig. 3 is lcd controller one an embodiment synoptic diagram of the present invention;
Fig. 4 A and Fig. 4 B are the process flow diagram of microprocessor of the present invention.
Description of reference numerals: 1-microprocessor; The 2-LCD controller; 3-LCD; The 4-LCD socket.
Embodiment
Below in conjunction with accompanying drawing, do more detailed explanation with other technical characterictic and advantage to the present invention is above-mentioned.
As shown in Figure 1; Form synoptic diagram for lcd controller of the present invention, lcd controller of the present invention comprises a microprocessor 1, one LCD steering logic 2; Described LCD steering logic 2 links to each other with said microprocessor 1 through the SPI interface; Realization is to the control of LCD3, and wherein, described LCD steering logic 2 is a PLD.
Wherein, Described LCD steering logic 2 links to each other with described microprocessor 1 through three signal line; The data signal line MOSI that this three signal line is respectively the SPI interface, clock cable SPCK and video data frame synchronizing signal FRAMESYNC; Wherein, video data frame synchronizing signal FRAMESYNC is connected on a certain I/O mouth of said microprocessor 1.Described LCD steering logic 2 links to each other with microprocessor 1 through the SPI interface; Obtain clock signal SPCK, data-signal MOSI and the video data frame synchronizing signal FRAMESYNC of SPI; Described LCD steering logic 2 makes up above-mentioned three signals according to the desired sequential of LCD; Produce required control signal and the data-signal of LCD, and these signals are sent on the LCD3, LCD3 can realize the demonstration of picture and literal.
Wherein, the microprocessor of the SPI interface that described microprocessor 1 is a kind of DMA of having transmission mode, preferable, can select AT91SAM9260 for use.
Described LCD steering logic 2 is a CPLD device or FPGA device, and is preferable, and can selecting for use cheaply, EPM240 realizes.
Described LCD control flow can be monochromatic screen and color line screen, and its model can be selected LR043JC211 for use.
As shown in Figure 2; For the Organization Chart of lcd controller control LCD of the present invention, can find out that by figure microprocessor 1 links to each other with LCD steering logic 2; LCD steering logic 2 adopts the CPLD device in the present embodiment; Microprocessor 1 usefulness DMA control mode sends to the CPLD device with video data through the SPI interface, and the data-signal and the clock signal of CPLD devices use SPI interface are according to the sequential requirement of LCD; Produce required pixel clock signal, line synchronizing signal and frame synchronizing signal, drive LCD with this and show.Wherein, the CPLD device is responsible for analyzing data-signal, the clock signal of SPI interface, and the demonstration that will generate output control signal connection LCD, realizes the control to LCD.
As shown in Figure 3; Be lcd controller one embodiment synoptic diagram of the present invention; Can know that by figure described CPLD device can be connected with LCD3 through a LCD socket 4, wherein connecting signal has: each 8 of RGB data-signals; Totally 24, pixel clock PCLK, line synchronizing signal HSYNC, frame synchronizing signal VSYNC, data allow control signals such as signal DE.These data-signals and control signal are by data-signal and the clock signal of CPLD according to the SPI interface, according to the sequential chart that the LCD that is adopted requires, realize through the internal logic of writing CPLD.Wherein, the CPLD device is responsible for analyzing the data-signal signal clock signal of SPI interface, and the demonstration that will generate output control signal connects the control that LCD socket 4 is realized LCD3.The lcd controller that the present invention realized only needs the piece of CPLD chip, need not add video memory.
Shown in Fig. 4 A and 4B, be the process flow diagram of microprocessor end of the present invention, the present invention provides a kind of control method of lcd controller, and it comprises the steps:
S1: in the internal memory of microprocessor 1, open up one with LCD 3 corresponding internal storage locations as video memory; Method for designing of the present invention can adapt to the LCD of multiple resolution, is example with these 4.3 cun LCD displays of 480 * 272 of strange letter electronics LR043JC211 here; Microprocessor adopts AT91SAM9260.Because this display screen requires in the process of the every row of scanning; Except the display pixel clock cycle in 480 cycles; The Front-Porch that also needs 2 pixel clock cycles, the Pulse Width in 41 pixel clock cycles, the Back-Porch in 2 pixel clock cycles.Amount to every row and need 525 pixel clock cycles.Simultaneously, in each frame data, except 272 row valid data, also need the Pulse Width of 10 capable synchronizing cycles, the Front-Porch of 2 capable synchronizing cycles, the Back-Porch of 2 capable synchronizing cycles.Need 286 capable synchronizing cycles altogether.Because the design's pixel clock signal, line synchronizing signal, frame synchronizing signal all are to be produced according to the clock signal of SPI interface by CPLD, so need open up one 526 * 286 internal storage location as video memory.
S2: the initiation parameter of microprocessor (AT91SAM9260) SPI interface is set, and the interruption of this interface and DMA parameter.Make SPI be operated in top speed,, the transmission data baud rate of SPI and major clock are equated, i.e. 100MHz as concerning the microprocessor that makes AT91SAM9260; The SPI interface is produced after the DMA data transmission finishes interrupt, the start address that the DMA transmission is set simultaneously is the start address of video memory, and the transmission byte number of DMA is the 64KB of the maximum permission of DMA transmission.After setting finishes, start the DMA transmission.
S3: behind the first time of SPI interface DMA end of transmission; Get into the interrupt service routine of SPI; In interrupt service routine; Reset the address pointer and transmission counter of DMA transmission, in addition, in interrupt service routine, also need judge currently needs to transmit which part in the frame video data and makes video data frame synchronizing signal (FRAMESYNC) produce rising edge at first at frame data.
S4: each frame data is divided into three times to be transmitted, 65536 bytes of preceding twice transmission, and this is the greatest measure that the DMA transmission of each SPI interface is allowed, and transmits 526 * 286-2 * 65536=19364 byte for the last time.In the reference position of each frame, produce a rising edge signal at FRAMESYNC (for being connected to a certain IO on the CPLD), begin to inform the new frame data of CPLD.
S5: in CPLD, FRAMESYNC catches to the video data frame synchronizing signal, when the FRAMESYNC rising edge; Represent the beginning of a frame video data; All inner counter resets of CPLD this moment comprise pixel clock counter, line synchronizing signal counter, the frame synchronizing signal counter; Promptly carry out the preparation that receives new frame data after resetting, the major function of this signal is to prevent that the demonstration of LCD can not received interference when receiving unexpected the interference.
S6: in CPLD, adopt, move into shift register to the data that get access to simultaneously at the rising edge of clock signal of SPI interface data-signal to the SPI interface; Simultaneously the clock signal of SPI interface is counted, (this moment, 8 looks were used in expression, adopted 16 looks like need when counting down to 8; Then count down to 16), expression receives a byte, on the data bus of the LCD that the data that receive are sent; Produce a pixel clock rising edge again, video data is sent to LCD.
S7:CPLD counts pixel clock, produces line synchronizing signal (HSYNC).
S8:CPLD counts line synchronizing signal (HSYNC), produces frame synchronizing signal (VSYNC).
Above-mentioned microprocessor is to adopt AT91SAM9260, and the also available microprocessor that other have the SPI interface of DMA transmission mode of said microprocessor replaces.Described LCD can be monochromatic screen and color line screen.
Though the processor A T91SAM9260 that is directed against among the present invention does not have built-in lcd controller, have the SPI interface of DMA transmission mode, and the speed of SPI interface has reached 100MHz.Owing to have the DMA transmission mode, this makes and through the SPI Data transmission time, needn't take a large amount of system resource.
In sum, the present invention's advantage compared with prior art is:
1, through dma mode transmitting and displaying data, owing to have the DMA transmission mode, this makes and through the SPI Data transmission time, needn't take a large amount of system resource through the SPI interface of microprocessor in the present invention.
2, through dma mode transmitting and displaying data, CPLD utilizes the data-signal MOSI of SPI interface and clock signal SPCK to produce required data-signal and the control signal of LCD through the SPI interface of microprocessor in the present invention.Can support multiple TFT-LCD display resolution and color figure place; The resolution that can support is relevant with the transmission speed of microprocessor SPI interface with the color figure place; Like AT91SAM9260 for atmel corp; The SPI maximal rate of this chip is 100MHz, and can make resolution is that 4.3 cun LCD displays of 480 * 272 are operated in 16 looks.
3, the present invention designs the LCD display controller and only needs need not external any SRAM or SDRAM as video memory, and all logics only to have taken 79 logical blocks of CPLD in the external piece of CPLD of microprocessor again.Therefore this lcd controller possesses lower cost, and reliability is also higher.
4, owing to only need 3 signal wires between lcd controller that the present invention designed and the microprocessor, be convenient to PCB layout, be convenient to the control of electromagnetic interference (EMI).
5, can be through revising the LCD that CPLD program and microprocessor program adapt to different resolution and color.
More than explanation is just illustrative for the purpose of the present invention, and nonrestrictive, those of ordinary skills understand; Under the situation of spirit that does not break away from following accompanying claims and limited and scope, can make many modifications, change; Or equivalence, but all will fall in protection scope of the present invention.
Claims (8)
1. the control method of a lcd controller realizes through a kind of lcd controller, and this lcd controller comprises a microprocessor and a LCD steering logic; Described LCD steering logic links to each other with said microprocessor through the SPI interface, realizes the control to LCD, wherein; Described LCD steering logic is a PLD; It is characterized in that the control method of lcd controller comprises the steps
A: in the internal memory of microprocessor, open up one with the corresponding internal storage location of LCD as video memory;
B: the interruption and the DMA parameter of initiation parameter and this interface of said microprocessor SPI interface are set, start the DMA transmission;
C: after the DMA transmission first time of accomplishing the SPI interface, get into the interrupt service routine of SPI;
D: in the reference position of each frame, produce a rising edge signal, begin to inform the new frame data of CPLD in the video data frame synchronizing signal;
E: in CPLD, the video data frame synchronizing signal is caught;
F: in CPLD; Rising edge of clock signal at the SPI interface is gathered the data-signal of SPI interface; Move into shift register to the data that get access to simultaneously, and the clock signal of SPI interface is counted, the data that receive are sent on the data bus of LCD; Produce a pixel clock rising edge again, video data is sent to LCD;
G:CPLD counts pixel clock, produces line synchronizing signal;
H:CPLD counts line synchronizing signal, produces frame synchronizing signal.
2. the control method of a kind of lcd controller according to claim 1 is characterized in that, in step a, said microprocessor is opened up one 526 * 286 internal storage location as video memory.
3. the control method of a kind of lcd controller according to claim 1 is characterized in that, in step b, when the initiation parameter of SPI interface is set, makes SPI be operated in top speed.
4. according to the control method of claim 1 or 3 described a kind of lcd controllers; It is characterized in that, in step b, the SPI interface is produced after the DMA data transmission finishes interrupt; The start address that the DMA transmission is set simultaneously is the start address of video memory; The transmission byte number of DMA is the 64KB that the maximum of DMA transmission allows, and after setting finishes, starts the DMA transmission.
5. the control method of a kind of lcd controller according to claim 1; It is characterized in that; In the interrupt service routine of step c; Reset the address pointer and transmission counter of DMA transmission, and judge and currently need which part in the transmission one frame video data and when frame data begin, make the video data frame synchronizing signal produce rising edge.
6. the control method of a kind of lcd controller according to claim 1; It is characterized in that; Each frame data is divided into three times to be transmitted; 65536 bytes of preceding twice transmission, it transmits 526 * 286-2 * 65536=19364 byte for the last time for the greatest measure that the DMA transmission of each SPI interface is allowed.
7. the control method of a kind of lcd controller according to claim 1; It is characterized in that, in step e, when video data frame synchronizing signal rising edge; Represent the beginning of a frame video data; All inner counter resets of CPLD this moment comprise pixel clock counter, line synchronizing signal counter, frame synchronizing signal counter, promptly carry out the preparation that receives new frame data after resetting.
8. the control method of a kind of lcd controller according to claim 1 is characterized in that, in step f, when using 8 looks, count down to 8, and expression receives a byte; When using 16 looks, count down to 16, expression receives a byte.
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| CN102509538A (en) * | 2011-11-17 | 2012-06-20 | 朱敦尧 | T-CON realization method based on CPLD |
| CN103176931B (en) * | 2011-12-26 | 2016-03-09 | 安凯(广州)微电子技术有限公司 | A kind of DMA communication means of improvement and device |
| CN103311928A (en) * | 2012-03-16 | 2013-09-18 | 上海利思电气有限公司 | Low-voltage dynamic active power filter |
| CN103870264A (en) * | 2012-12-18 | 2014-06-18 | 苏州工业园区新宏博通讯科技有限公司 | Programmable liquid crystal display module |
| CN103970708B (en) * | 2014-03-18 | 2017-01-04 | 中国航天科工信息技术研究院 | Communication means between a kind of FPGA and general processor and system |
| CN104810000A (en) * | 2015-05-14 | 2015-07-29 | 武汉华星光电技术有限公司 | Control circuit and control method used for liquid crystal display |
| CN109684718A (en) * | 2018-12-24 | 2019-04-26 | 成都华微电子科技有限公司 | Low-power consumption may be programmed SoC device and design method |
| CN113642345B (en) * | 2020-05-11 | 2023-12-08 | 北京君正集成电路股份有限公司 | Method for improving effective data transmission rate for two-dimensional code equipment |
| DE102022119130B3 (en) * | 2022-07-29 | 2023-09-07 | Achim Döbler | Method for driving active matrix displays, associated control device and computer program product |
| CN117809542A (en) * | 2022-09-23 | 2024-04-02 | 施耐德电器工业公司 | Method and device for transmitting signals to RGB interface of display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2828952Y (en) * | 2005-10-26 | 2006-10-18 | 江苏大唐电子产品有限公司 | Tax rate control casher of supporting USB interface and download applied program |
| CN2836112Y (en) * | 2005-10-31 | 2006-11-08 | 成都卫士通信息产业股份有限公司 | Financial tax-controlled cash register |
| CN101021551A (en) * | 2006-10-27 | 2007-08-22 | 东莞理工学院 | Intelligent comprehensive electronic measuring instrument |
| CN101405716A (en) * | 2006-03-24 | 2009-04-08 | Nxp股份有限公司 | Rapid creation and configuration of microcontroller products with configurable logic devices |
| CN201522841U (en) * | 2009-11-19 | 2010-07-07 | 航天信息股份有限公司 | Lcd controller |
-
2009
- 2009-11-19 CN CN200910237490A patent/CN102074205B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2828952Y (en) * | 2005-10-26 | 2006-10-18 | 江苏大唐电子产品有限公司 | Tax rate control casher of supporting USB interface and download applied program |
| CN2836112Y (en) * | 2005-10-31 | 2006-11-08 | 成都卫士通信息产业股份有限公司 | Financial tax-controlled cash register |
| CN101405716A (en) * | 2006-03-24 | 2009-04-08 | Nxp股份有限公司 | Rapid creation and configuration of microcontroller products with configurable logic devices |
| CN101021551A (en) * | 2006-10-27 | 2007-08-22 | 东莞理工学院 | Intelligent comprehensive electronic measuring instrument |
| CN201522841U (en) * | 2009-11-19 | 2010-07-07 | 航天信息股份有限公司 | Lcd controller |
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