CN101404145B - LCD control system - Google Patents
LCD control system Download PDFInfo
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- CN101404145B CN101404145B CN2008100933978A CN200810093397A CN101404145B CN 101404145 B CN101404145 B CN 101404145B CN 2008100933978 A CN2008100933978 A CN 2008100933978A CN 200810093397 A CN200810093397 A CN 200810093397A CN 101404145 B CN101404145 B CN 101404145B
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Abstract
The present invention discloses a liquid crystal display controlling system, which comprises an output clock generating unit, a synchronous signal buffer memory unit, a synchronous signal reading unit, N video signal buffer memory units and an video signal output unit, wherein, the output clock generating unit can generate an output clock signal with a specific scaling according to the working mode of the liquid crystal display controlling system, the synchronous signal buffer memory unit is used for storing a data enabling signal and the like, which are capable of carrying out the signal synchronization on a row or a plurality of rows of video signals, the synchronous signal reading unit is used for reading the data enabling signal and the like, from the synchronous signal buffer memory unit according to the control time sequence requirement of liquid crystal display, and processing the data enabling signal and the like, in a scaling mode according to the specific scaling; the N video signal buffer memory units are used for storing 1/N parts of a row or a plurality of rows of video signals; the video signal output unit is used for reading 1/N parts of a row or a plurality of rows of video signals from the N video signal buffer memory units according to the output clock signal, the control time sequence of the liquid crystal display, and the data enabling signal and the like, processed in a scaling mode, processing each 1/N part in a scaling mode according to the specific scaling, and outputting the signals processed in a scaling mode to outside.
Description
Technical field
The present invention relates to field of video displaying, relate more specifically to a kind of LCD control system.
Background technology
In existing LCD Controller chip (TCON),, be respectively single port output, dual-port output and three kinds of output modes of four ports output according to the size of support liquid crystal display display size.Under the dual-port pattern, two ports are exported the preceding hemistich and the back hemistich of delegation respectively.Under four port modes, each port is exported four/part of delegation's correspondence respectively.When supporting the multiport pattern, the LCD Controller chip has an independent row buffering unit that the video data of delegation is divided into two hemistich or four 1/4th line outputs.
Need support the video input of different resolution form equally for the liquid crystal display of fixed physical resolution.This function realizes by Zoom module (Scalor).During the convergent-divergent of support level and vertical direction, Zoom module will have independent storage unit to realize zoom function at the same time, and storage unit needs the above video data of storing one row.
Prior art adopts row buffering unit and the unit for scaling that separates, and needs bigger storer to deposit video data respectively, causes chip area excessive.
Summary of the invention
The object of the present invention is to provide a kind of new LCD control system, to utilize the row buffering unit (line buffer) in the LCD control system, make the liquid crystal display of fixed physical resolution support the video input of different resolution form by scalable manner (Scale).
LCD control system according to the embodiment of the invention comprises: output clock generation unit is used for generating the clock signal with specific scaling according to the mode of operation of LCD control system; The synchronizing signal buffer unit, be used to store be used for to one or the multi-line video signal carry out data enable signal, line synchronizing signal and the field sync signal of signal Synchronization; The synchronizing signal reading unit, be used for control timing requirement according to liquid crystal display, reading of data enable signal, line synchronizing signal and field sync signal from the synchronizing signal buffer unit, and data enable signal, line synchronizing signal and field sync signal are carried out convergent-divergent according to specific scaling handle; N vision signal buffer unit is respectively applied for the storage one or the 1/N part of multi-line video signal; And vision signal output unit, be used for according to the control timing of clock signal, liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the convergent-divergent processing, from N vision signal buffer unit, read one or the 1/N part of multi-line video signal respectively, to one or N 1/N part of multi-line video signal carry out convergent-divergent according to specific scaling and handle, and N 1/N of one or multi-line video signal after convergent-divergent handled partly exports the outside simultaneously to.
Wherein, the vision signal output unit comprises: the vision signal reading unit, be used for according to the control timing of clock signal, liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the convergent-divergent processing, from N vision signal buffer unit, read one or the 1/N part of multi-line video signal respectively, to one or each 1/N part of multi-line video signal carry out convergent-divergent according to specific scaling and handle; The vision signal map unit, be used for each 1/N of one or multi-line video signal after the convergent-divergent processing is partly shone upon, and the mapping result of N 1/N part of one or multi-line video signal after by N output port convergent-divergent being handled respectively exports the outside simultaneously to.
Wherein, the synchronizing signal reading unit is realized the convergent-divergent of data enable signal, line synchronizing signal and field sync signal is handled by synchronous convergent-divergent counter.The vision signal reading unit by data convergent-divergent counter realize to one or the convergent-divergent of each 1/N part of multi-line video signal handle.The frequency of the frequency of the clock signal that output clock generation unit generates and the source clock of LCD control system has strict proportionate relationship.Alternatively, the frequency of the clock signal of output clock generation unit generation is independent of the frequency of the source clock of LCD control system.
By the present invention, can save the line buffer unit of video data, thereby can reduce the area requirements in the chip design.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the structured flowchart according to the LCD control system of the first embodiment of the present invention; And
Fig. 2 is the logic diagram of LCD control system according to a second embodiment of the present invention.
Embodiment
Below with reference to accompanying drawing, describe the specific embodiment of the present invention in detail.
Fig. 1 is the structured flowchart according to the LCD control system of the first embodiment of the present invention.As shown in Figure 1, this LCD control system comprises: synchronizing signal buffer cell, synchronizing signal read pointer, synchronizing signal write pointer, data buffer unit, data read pointer, data write pointer, output clock generator and output data map unit.
Wherein, the synchronizing signal buffer cell is used to preserve video synchronization signal, and data buffer unit is used to preserve video data.Under the dual-port mode of operation, hemistich data before the data buffer unit a storage, data buffer unit b stores later half line data, hemistich and later half line data before the output clock that output clock generator generates is read simultaneously, and export respectively at two ports after the mapping through the output data map unit.Wherein, output clock generator is according to the output clock of mode of operation (as single port or dual-port, scaling) generation suitable frequency, and the frequency of output clock can have strict proportionate relationship with the source clock, also can be independent of the frequency values of source clock.
For non-convergent-divergent (Scalor) pattern: the synchronizing signal read pointer requires to read successively video synchronization signal in the synchronizing signal buffer cell according to the sequential of LCD Controller, and the video synchronization signal of output is used for the control of data read pointer simultaneously.The data read pointer is equally according to the sequential requirement of LCD Controller, and under the control of video synchronization signal the video data in the sense data buffer cell successively.
When supporting convergent-divergent (Scalor) pattern: the synchronizing signal after the synchronizing signal read pointer also need require according to the synchro control of convergent-divergent to recover convergent-divergent.This process can be realized by the control of synchronous convergent-divergent counter.The convergent-divergent of image also needs the data read pointer to finish under zoom mode control, and this process also can be realized by the control of data convergent-divergent counter.Alternatively, after the data read pointer is read the video data of respective pixel successively, also can realize the scaled data processing by the data map unit.Wherein, as long as data buffer unit can be preserved the above data (not passing through the data of convergent-divergent) of two row, just can the while support level and the zoom function of vertical direction according to the LCD Controller unit of the embodiment of the invention.
Fig. 2 is the logic diagram of LCD control system according to a second embodiment of the present invention.As shown in Figure 2, this LCD control system comprises: output clock generation unit is used for generating the clock signal with specific scaling according to the mode of operation of LCD control system; The synchronizing signal buffer unit, be used to store be used for to one or the multi-line video signal carry out data enable signal, line synchronizing signal and the field sync signal of signal Synchronization; The synchronizing signal reading unit, be used for control timing requirement according to liquid crystal display, reading of data enable signal, line synchronizing signal and field sync signal from the synchronizing signal buffer unit, and data enable signal, line synchronizing signal and field sync signal are carried out convergent-divergent according to specific scaling handle; N vision signal buffer unit is respectively applied for the storage one or the 1/N part of multi-line video signal; And vision signal output unit, be used for according to the control timing of clock signal, liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the convergent-divergent processing, from N vision signal buffer unit, read one or the 1/N part of multi-line video signal respectively, to one or each 1/N part of multi-line video signal carry out convergent-divergent according to specific scaling and handle, and N 1/N of one or multi-line video signal after convergent-divergent handled partly exports the outside to.
Wherein, the vision signal output unit comprises: the vision signal reading unit, be used for according to the control timing of clock signal, liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the convergent-divergent processing, from N vision signal buffer unit, read one or the 1/N part of multi-line video signal respectively, to one or each 1/N part of multi-line video signal carry out convergent-divergent according to specific scaling and handle; The vision signal map unit is used for each 1/N of one or multi-line video signal after the convergent-divergent processing is partly shone upon, and the mapping result of each 1/N part of one or multi-line video signal after by N output port convergent-divergent being handled respectively exports the outside to.
Wherein, the synchronizing signal reading unit is realized the convergent-divergent of data enable signal, line synchronizing signal and field sync signal is handled by synchronous convergent-divergent counter.The vision signal reading unit by data convergent-divergent counter realize to one or the convergent-divergent of each 1/N part of multi-line video signal handle.The frequency of the frequency of the clock signal that output clock generation unit generates and the source clock of LCD control system has strict proportionate relationship.Alternatively, the frequency of the clock signal of output clock generation unit generation is independent of the frequency of the source clock of LCD control system.
By the present invention, can save the line buffer unit of video data, thereby can reduce the area requirements in the chip design.
The above is embodiments of the invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (5)
1. a LCD control system is characterized in that, comprising:
Output clock generation unit is used for generating the clock signal with specific scaling according to the mode of operation of described LCD control system;
The synchronizing signal buffer unit, be used to store be used for to one or the multi-line video signal carry out data enable signal, line synchronizing signal and the field sync signal of signal Synchronization;
The synchronizing signal reading unit, be used for control timing requirement according to liquid crystal display, from described synchronizing signal buffer unit, read described data enable signal, line synchronizing signal and field sync signal, and described data enable signal, line synchronizing signal and field sync signal are carried out convergent-divergent according to described specific scaling handle;
N vision signal buffer unit is respectively applied for the storage described one or the 1/N part of multi-line video signal; And
The vision signal output unit, be used for according to the control timing of described clock signal, described liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the convergent-divergent processing, from described N vision signal buffer unit, read described one or the 1/N part of multi-line video signal respectively, by data convergent-divergent counter to described one or N 1/N part of multi-line video signal carry out convergent-divergent according to described specific scaling and handle, and N 1/N of one or multi-line video signal after convergent-divergent handled partly exports the outside simultaneously to.
2. LCD control system according to claim 1 is characterized in that, described vision signal output unit comprises:
The vision signal reading unit, be used for according to the control timing of described clock signal, described liquid crystal display and data enable signal, line synchronizing signal and the field sync signal after the processing of described convergent-divergent, from described N vision signal buffer unit, read described one or each 1/N part of multi-line video signal respectively, to described one or each 1/N part of multi-line video signal carry out convergent-divergent according to described specific scaling and handle;
The vision signal map unit, be used for each 1/N of one or multi-line video signal after the described convergent-divergent processing is partly shone upon, and the mapping result of each 1/N part of one or multi-line video signal after by N output port described convergent-divergent being handled respectively exports the outside simultaneously to.
3. LCD control system according to claim 2 is characterized in that, described synchronizing signal reading unit is realized the convergent-divergent of described data enable signal, line synchronizing signal and field sync signal is handled by synchronous convergent-divergent counter.
4. according to each described LCD control system in the claim 1 to 3, it is characterized in that the frequency of the frequency of the described clock signal that described output clock generation unit generates and the source clock of described LCD control system has strict proportionate relationship.
5. according to each described LCD control system in the claim 1 to 3, it is characterized in that the frequency of the described clock signal that described output clock generation unit generates is independent of the frequency of the source clock of described LCD control system.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100933978A CN101404145B (en) | 2008-04-17 | 2008-04-17 | LCD control system |
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| CN2008100933978A CN101404145B (en) | 2008-04-17 | 2008-04-17 | LCD control system |
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| CN101404145A CN101404145A (en) | 2009-04-08 |
| CN101404145B true CN101404145B (en) | 2010-07-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103647918B (en) * | 2013-12-20 | 2017-04-12 | 广东威创视讯科技股份有限公司 | Video synchronization method and device |
| CN109906607A (en) * | 2016-10-26 | 2019-06-18 | Nec显示器解决方案株式会社 | Video signal output apparatus, display system and vision signal output method |
| CN109935220B (en) * | 2019-04-17 | 2022-01-25 | Tcl华星光电技术有限公司 | Drive circuit and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2613020Y (en) * | 2003-04-22 | 2004-04-21 | 海信集团有限公司 | Data validity signal generating circuit for display digital image zooming |
| CN1746923A (en) * | 2004-09-10 | 2006-03-15 | 上海杰得微电子有限公司 | Contraction of digital image circuit with adjustable proportion and accuracy |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2613020Y (en) * | 2003-04-22 | 2004-04-21 | 海信集团有限公司 | Data validity signal generating circuit for display digital image zooming |
| CN1746923A (en) * | 2004-09-10 | 2006-03-15 | 上海杰得微电子有限公司 | Contraction of digital image circuit with adjustable proportion and accuracy |
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