CN109935220B - Drive circuit and display device - Google Patents
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- CN109935220B CN109935220B CN201910310501.2A CN201910310501A CN109935220B CN 109935220 B CN109935220 B CN 109935220B CN 201910310501 A CN201910310501 A CN 201910310501A CN 109935220 B CN109935220 B CN 109935220B
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Abstract
The application provides a drive circuit and a display device, wherein the drive circuit has high working efficiency and saves the storage space required by the drive circuit by enabling a receiving module and an image data processing module to be connected with a control signal generating module so as to enable the time sequence adjustable range of the drive control signal output by the drive circuit to be wider.
Description
Technical Field
The application relates to the technical field of display, in particular to a driving circuit and a display device.
Background
A Gate Driver On Array (GOA), that is, a Gate line scan driving signal circuit is fabricated On an Array substrate by using an Array process in a conventional thin film transistor liquid crystal display to realize a driving method of scanning a Gate line by line, and the Gate driving circuit omits a Gate driving chip (IC) originally disposed On the Array substrate, thereby reducing the production cost and realizing a narrow frame.
As shown in fig. 1, it is a timing diagram of a gate driving circuit for 6 normal clock signals in a display. As shown in fig. 2, it is a frame diagram of a timing controller outputting gate start pulse signals (STV1 and STV2) and clock signals in fig. 1. Wherein, the Control Signal generating module (Control Signal) is used for receiving the enable Signal output by the line buffer module and outputting the clock Signal and the Control Signal (including the gate start pulse Signal) of the gate driving circuit according to the enable Signal, however, the depth (the size of the storage) of the line buffer module will affect the output of the enable Signal and thus the adjustment range of the timing between the gate start pulse signals (STV1 and STV2) and the clock Signal CK1, when the depth of the line buffer module is smaller, the adjustable range of the timing (the output time difference) between the gate start pulse signals (STV1 and STV2) and the clock Signal CK1 is smaller, when the depth of the line buffer module is larger, the adjustable range of the timing between the gate start pulse signals (STV1 and STV2) and the clock Signal CK1 is larger, however, the line buffer module is only used for adjusting the timing between the gate start pulse signals and the clock Signal CK1, the depth of the line cache module is large, which causes waste.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a driving circuit, which has a wide adjustable range of timing of driving control signals outputted from the driving circuit, high operating efficiency of the driving circuit, and reduced memory space required by the driving circuit.
In order to achieve the above object, the present application provides a driving circuit, which includes a receiving module, an image data processing module connected to the receiving module, and a control signal generating module connected to both the receiving module and the image data processing module, wherein the control signal generating module is configured to receive an enable signal to generate a driving control signal, and the enable signal is input to the control signal generating module by at least one of the receiving module and the image data processing module.
In the above driving circuit, the driving circuit further includes an aging control module located between the receiving module and the image processing module, the aging control module is connected to the control signal generating module, and the enable signal is input to the control signal generating module from at least one of the receiving module, the aging control module, and the image data processing module.
In the above driving circuit, the driving circuit further includes a line buffer module connected to the image data processing module, the line buffer module is connected to the control signal generating module, and the enable signal is input to the control signal generating module from at least one of the receiving module, the aging control module, the image data processing module, and the line buffer module.
In the above driving circuit, the image data processing module includes an overdrive unit and an image processing unit, the overdrive unit and/or the image processing unit is connected to the control signal generating module, and the enable signal is input to the control signal generating module from at least one of the receiving module, the overdrive unit and/or the image processing unit, the aging control module, and the line buffer module.
In the driving circuit, the driving control signal includes a gate start pulse signal and a gate clock shift signal.
In the above driving circuit, the control signal generating module includes a selecting unit for selecting at least one of the receiving module, the burn-in control module, the overdrive unit and/or the image processing unit and the line buffer module to input the enable signal to the control signal generating module based on a timing between the gate start pulse signal and the gate clock shift signal.
In the driving circuit, the control signal generating module further includes a gate start pulse signal generating unit, a gate clock shift signal generating unit, and a delay unit connected to the gate start pulse signal generating unit, where the gate start pulse signal generating unit and the gate clock shift signal generating unit are configured to output the gate start pulse signal and the gate clock shift signal respectively based on the input enable signal, and the delay unit is configured to delay the gate start pulse signal according to a delay parameter so as to adjust a timing between the gate start pulse signal and the gate clock shift signal.
In the above driving circuit, the enable signal includes a first enable signal, the control signal generating module is configured to receive the first enable signal, output the gate start pulse signal when detecting a first rising edge of the first enable signal, and generate the gate clock shift signal at a first preset time after the first rising edge of the first enable signal in an active period, where the first enable signal is output to the control signal generating module by any one of the receiving module, the aging control module, the overdrive unit and/or the image processing unit, and the line buffer module.
In the driving circuit, the enable signal includes a first enable signal and a second enable signal sequentially input to the control signal generating module, the control signal generating module is configured to receive the first enable signal and output the gate start pulse signal when detecting a first rising edge of the first enable signal, and output the gate clock shift signal when receiving the second enable signal, and the first enable signal and the second enable signal are output to the control signal generating module by different two of the receiving module, the aging control module, the overdrive unit and/or the image processing unit, and the line buffer module.
The application also provides a display device which comprises the driving circuit. The display device has wide adjustable time sequence range of the driving control signal output by the driving circuit, high working efficiency, saved storage space required by the driving circuit, improved working efficiency and reduced manufacturing cost.
Has the advantages that: the application provides a drive circuit and a display device, wherein the drive circuit has high working efficiency and saves the storage space required by the drive circuit by enabling a receiving module and an image data processing module to be connected with a control signal generating module so as to enable the time sequence adjustable range of the drive control signal output by the drive circuit to be wider.
Drawings
FIG. 1 is a timing diagram of a gate driving circuit with 6 normal clock signals in a display;
fig. 2 is a frame diagram of a timing controller outputting the gate start pulse signal and the gate shift clock signal shown in fig. 1;
FIG. 3 is a first block diagram of a driving circuit according to an embodiment of the present disclosure;
FIG. 4 is a second block diagram of a driving circuit according to an embodiment of the present application;
FIG. 5 is a third block diagram of a driving circuit according to an embodiment of the present application;
FIG. 6 is a block diagram of the image data processing module of FIG. 5;
fig. 7 is a block diagram of a control signal generating module in fig. 5.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Please refer to fig. 3, which is a first block diagram of a driving circuit according to an embodiment of the present disclosure, wherein the driving circuit includes a receiving module 10, an image data processing module 11, and a control signal generating module 13.
The receiving module 10 is configured to receive image data, a synchronization signal, and a source clock signal generated by a clock generator, which are provided from the outside, and output the image data signal, the synchronization signal, and the source clock signal. The synchronization signal includes at least an input enable signal, and may further include a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync.
The image data processing module 11 is configured to receive and process the image data signal, the synchronization signal and the source clock signal output by the receiving module 10 to output the processed image data signal and the source clock signal.
The control signal generating module 13 is configured to receive the enable signal to generate a driving control signal, and output the driving control signal to the gate driving circuit and the source driving circuit, where the driving control signal includes a gate start pulse signal, a gate clock shift signal, a source start pulse signal, and a source clock shift signal. The receiving module 10 and the image data processing module 11 are both connected to the control signal generating module 13, and the enable signal is input to the control signal generating module 13 from at least one of the receiving module 10 and the image data processing module 11.
Specifically, after the receiving module 10 receives the input enable signal, the receiving module outputs a first enable signal based on the input enable signal, where the first enable signal is different from the input enable signal only in that a first phase difference exists between the first enable signal and the input enable signal, and the first phase difference is a time difference between the receiving module 10 receiving the input enable signal and outputting the first enable signal. The receiving module 10 outputs the first enable signal to the image data module 11, the image data processing module 11 outputs a second enable signal based on the first enable signal, the second enable signal is different from the first enable signal only in that a second phase difference exists between the first enable signal and the second enable signal, and the second phase difference is a time difference between the first enable signal received by the image data processing module 11 and the second output enable signal output by the image data processing module 11. The enable signal is a first enable signal output by the receiving module 10 and/or a second enable signal output by the image data processing module 11.
The receiving module and the image data processing module are connected with the control signal generating module, and the time sequence of the enabling signal input to the control signal generating module is adjusted by utilizing the phase difference generated in the transmission process of the input enabling signal between the receiving module and the image data processing module, so that the time sequence of the control signal generating module for generating the driving control signal is adjusted. Compared with the prior art, the driving control signal generation module adopts a separate line buffer module to store the enable signal and outputs the enable signal to the control signal generation module by the line buffer module to generate the driving control signal. The drive circuit widens the adjustable range of the time sequence of the drive control signal, can reduce the storage space used by the drive circuit, and has the characteristic of high efficiency.
Please refer to fig. 4, which is a second block diagram of a driving circuit according to an embodiment of the present disclosure. The driving circuit shown in fig. 4 is substantially similar to the driving circuit shown in fig. 3, except that the driving circuit further includes an Aging Controller (Aging Controller)14 located between the receiving module 10 and the image data processing module 11, and the Aging Controller 14 is connected to the control signal generating module 13. The enable signal is input to the control signal generation module 13 from at least one of the reception module 10, the aging control module 14, and the image data processing module 11.
The aging control module 14 is configured to receive and test the first enable signal, the image data signal, and the source clock signal output by the receiving module 10, and output the received first enable signal, the image data signal, and the source clock signal to the image data processing module 11 if the received first enable signal, the received image data signal, and the received source clock signal are normal; if any one of the received first enable signal, the image data signal and the source clock signal is abnormal, the aging control module 15 generates a normal corresponding signal and outputs a normal related signal. The aging control module 14 is connected to a latch (not shown), the latch is connected to an internal oscillation circuit (not shown), and after the internal oscillation circuit outputs a clock signal to the latch, the latch adjusts the frequency of the input clock signal and outputs the clock signal to the aging control module 14.
After receiving the input enable signal, the receiving module 10 outputs a first enable signal based on the input enable signal, where the first enable signal is different from the input enable signal only in that a first phase difference exists between the first enable signal and the input enable signal, and the first phase difference is a time difference from when the receiving module 10 receives the input enable signal to when the first enable signal is output. The aging control module 14 outputs a third enable signal based on the received first enable signal, the third enable signal being different from the first enable signal only in that a third phase difference exists therebetween, the third phase difference being a time difference from the receiving of the first enable signal to the outputting of the third enable signal by the aging control module 14; the image data processing module 11 outputs a fourth enable signal based on the received third enable signal, the fourth enable signal being different from the third enable signal only in that a fourth phase difference exists therebetween, the fourth phase difference being a time difference from the receiving of the third enable signal to the outputting of the fourth enable signal by the image data processing module 11. The enable signal is at least one of a first enable signal output by the receiving module 10, a third enable signal output by the aging control module 14, and a fourth enable signal output by the image data processing module 11.
Please refer to fig. 5, which is a third block diagram of a driving circuit according to an embodiment of the present application. It is basically similar to the driving circuit shown in fig. 4, except that the driving circuit further includes a line buffer module 12, a mirror control module 16, and an output module 15.
The line cache module 12 mainly includes a Random Access Memory (RAM) and a First-in First-out buffer (FIFO). The line buffer module 12 is configured to receive the fourth enable signal and the processed image data signal output by the image data processing module 11 and output the processed image data signal and a fifth enable signal, where the fifth enable signal is different from the fourth enable signal only in that a fifth phase difference exists between the fourth enable signal and the processed image data signal, and the fifth phase difference is a time difference between the line buffer module 12 inputting the fourth enable signal and outputting the fifth enable signal. The enable signal is at least one of a first enable signal output by the receiving module 10, a third enable signal output by the aging control module 15, a fourth enable signal output by the image data processing module 11, and a fifth enable signal output by the line buffer module 12. The timing adjustment range of the driving control signal output from the control signal generation block 13 is further increased by adding the line buffer block 12. Although the line cache module 12 is added, compared with the framework of the traditional driving circuit, the block RAM or FIFO used by the line cache module 121 can be reduced, and the manufacturing cost is saved.
The line buffer module 12 is further configured to store the processed image data signal and output the processed image data signal to the mirror control module 16. The mirror image control module 16 is configured to process the image data signal output by the line buffer module 12 to control the polarity of the data voltage of each pixel to be opposite to that of the adjacent pixel.
The output module 15 is used for outputting the image data signal processed by the mirror image control module 16 and the source clock signal to the source driver.
Please refer to fig. 6, which is a block diagram of the image data processing module shown in fig. 5. The image data processing module 11 includes an overdrive unit 111 and an image processing unit 112. The overdrive unit 111 and/or the image processing unit 112 are connected to the control signal generation module 13. The overdrive unit 111 and the image processing unit 112 may delay the input enable signal input into the image data processing block 11 and output the input enable signal having a phase difference. The enable signal is input to the control signal generation module 13 by at least one of the reception module, the overdrive unit and/or the image processing unit, the burn-in control module, and the line buffer module.
The overdrive unit 111 is used for processing the image data signal to improve the gray scale response time when displaying the image, and the image processing unit 112 is used for processing the image data signal to improve the effect when displaying the image. The image data processing module 11 further includes a gamma voltage control unit 113, and the gamma voltage control unit 113 is configured to process the image data to adjust a white balance of the display image.
Please refer to fig. 7, which is a block diagram of the control signal generating module in fig. 5. The control signal generation module 13 includes a selection unit 131. Since a phase difference is generated in the process of the external input enable signal passing through the receiving module 10, the aging control module 14, the overdrive unit 111 and/or the image processing unit 112 and the line buffer module 12, different units or modules can output input enable signals with different timings, the phase difference between the input enable signal output by the receiving module 10 and the input enable signal output by the line buffer module 12 is the largest, and the time difference between the input enable signal output by the receiving module 10 and the input enable signal output by the aging control module 14 is the smallest. The input enable signals of different timings can control the signal generation module 13 to output the driving control signals having different timings. When the driving control signals are the gate start pulse signal and the gate clock shift signal, the selection unit 131 is configured to select at least one of the receiving module 10, the aging control module 14, the overdrive unit 111 and/or the image processing unit 112, and the line buffer module 12 to input the enable signal to the control signal generation module 13 based on the timing between the gate start pulse signal and the gate clock shift signal.
The selection unit 131 counts buffers (line buffers) used by the receiving module 10, the aging control module 14, the overdrive unit 111, the image processing unit 112, and the line buffer module 12, and times (including enable and disable) required by the modules or units in the process of processing the input enable signal, and selects a corresponding enable signal output module or unit to output the enable signal to the control signal generation module 13 based on the timing T between the gate start pulse signal and the gate clock shift signal. For example, the buffers used by the receiving module 10, the aging control module 14, the overdrive unit 111, the image processing unit 112, and the line buffer module 12 are n buffers, each buffer makes the phase difference generated by the input enable signal the same, that is, each buffer makes the delay generated by the input enable signal the same, and the maximum delay generated by the input enable signal is n × t. The selection unit 131 selects an input unit of the enable signal based on the timing T between the gate start pulse signal and the gate clock shift signal and the delay T of each buffer. Specifically, an integer value M obtained by dividing T by T is the number of cache bars to be used, an input module or unit of an enable signal is determined based on the number of cache bars, a remainder a obtained by dividing T by T is a delay parameter, and the timing sequence between a gate start pulse signal and a gate clock shift signal is finely adjusted by the delay parameter a.
The control signal generating module 13 further includes a gate start pulse signal generating unit 132, a gate clock shift signal generating unit 133, and a delay unit 134 connected to the gate start pulse generating unit 132, wherein the gate start pulse generating unit 132 and the gate clock shift signal generating unit 133 are configured to output a gate start pulse signal and a gate clock shift signal respectively based on an input enable signal, and the delay unit is configured to delay the gate start pulse signal according to a delay parameter so as to adjust a timing between the gate start pulse signal and the gate clock shift signal.
The enable signal includes a first enable signal, the control signal generating module 13 is configured to receive the first enable signal and output a gate start pulse signal when a first rising edge of the first enable signal of a frame of video is detected, and generate a gate clock shift signal at a first preset time after the first rising edge of the first enable signal in an effective period, where the first enable signal is output to the control signal generating module 13 by any one of the receiving module 10, the aging control module 14, the overdrive unit 111, the image processing unit 112, and the line buffer module 12.
The enable signal includes a first enable signal and a second enable signal sequentially input to the control signal generating module 13, the control signal generating module is configured to receive the first enable signal and output a gate start pulse signal when detecting a first rising edge of the first enable signal of a frame of video, and output a gate clock shift signal when receiving the second enable signal, and the first enable signal and the second enable signal are output to the control signal generating module 13 from different two of the receiving module 10, the aging control module 14, the overdrive unit 111 and/or the image processing unit 112, and the line buffer module 12.
The application also provides a display device, which comprises the drive circuit and a display panel. The display device has wide adjustable time sequence range of the driving control signal output by the driving circuit, high working efficiency, saved storage space required by the driving circuit, improved working efficiency and reduced manufacturing cost.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A driving circuit is characterized by comprising a receiving module, an image data processing module connected with the receiving module, and a control signal generating module directly connected with the receiving module and the image data processing module, wherein the control signal generating module is used for receiving an enable signal to generate a control signal for driving, the enable signal is input to the control signal generating module through the receiving module and the image data processing module, and a phase difference exists between the enable signal output by the receiving module and the enable signal output by the image data processing module.
2. The driving circuit according to claim 1, further comprising an aging control module located between the receiving module and the image data processing module, wherein the aging control module is directly connected to the control signal generation module, a third phase difference exists between a first enable signal output by the receiving module and a third enable signal output by the aging control module, a fourth phase difference exists between a fourth enable signal output by the image data processing module and a third enable signal output by the aging control module, and the enable signals are input to the control signal generation module by the receiving module, the aging control module, and the image data processing module.
3. The driving circuit according to claim 2, further comprising a line buffer module connected to the image data processing module, wherein the line buffer module is directly connected to the control signal generation module, a fifth phase difference exists between a fifth enable signal output by the line buffer module and a fourth enable signal output by the image data processing module, and the enable signals are input to the control signal generation module by the receiving module, the aging control module, the image data processing module, and the line buffer module.
4. The driving circuit according to claim 3, wherein the image data processing module further comprises an overdrive unit and an image processing unit, the overdrive unit and/or the image processing unit is directly connected to the control signal generation module, and the enable signal is input to the control signal generation module by the receiving module, the overdrive unit and/or the image processing unit, the aging control module, and the line buffer module.
5. The driving circuit according to claim 4, wherein the driving control signal comprises a gate start pulse signal and a gate clock shift signal.
6. The driving circuit according to claim 5, wherein the control signal generation module comprises a selection unit configured to select at least one of the receiving module, the aging control module, the overdrive unit and/or the image processing unit, and the line buffer module to input the enable signal to the control signal generation module based on a timing between the gate start pulse signal and the gate clock shift signal.
7. The driving circuit according to claim 6, wherein the control signal generating module further comprises a gate start pulse signal generating unit, a gate clock shift signal generating unit, and a delay unit connected to the gate start pulse signal generating unit, the gate start pulse signal generating unit and the gate clock shift signal generating unit are configured to output the gate start pulse signal and the gate clock shift signal respectively based on the input enable signal, and the delay unit is configured to delay the output of the gate start pulse signal according to a delay parameter so as to adjust a timing between the gate start pulse signal and the gate clock shift signal.
8. The driving circuit according to claim 5, wherein the enable signal comprises a first enable signal, the control signal generating module is configured to receive the first enable signal and output the gate start pulse signal when detecting a first rising edge of the first enable signal, and generate the gate clock shift signal at a first preset time after the first rising edge of the first enable signal in an active period, where the first enable signal is output to the control signal generating module by any one of the receiving module, the aging control module, the overdrive unit and/or the image processing unit, and the line buffer module.
9. The driving circuit of claim 5, wherein the enable signal comprises a first enable signal and a second enable signal sequentially input to the control signal generating module, the control signal generating module is configured to receive the first enable signal and output the gate start pulse signal when detecting a first rising edge of the first enable signal, and output the gate clock shift signal when receiving the second enable signal, and the first enable signal and the second enable signal are output to the control signal generating module by different two of the receiving module, the aging control module, the overdrive unit and/or the image processing unit, and the line buffer module.
10. A display device characterized in that the display device comprises a driver circuit according to any one of claims 1 to 9.
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Denomination of invention: Drive circuit and display device Effective date of registration: 20231113 Granted publication date: 20220125 Pledgee: Industrial and Commercial Bank of China Limited Shenzhen Guangming Sub branch Pledgor: TCL Huaxing Photoelectric Technology Co.,Ltd. Registration number: Y2023980065368 |