KR20090096999A - Display device capable of reducing a transmission channel frequency - Google Patents

Abstract

A display device capable of reducing a transmission channel frequency is provided to reduce current consumption and heat by reducing a channel frequency in transmitting data between a timing controller and a source driver. In a display device capable of reducing a transmission channel frequency, a timing controller(100) receives data from the outside in response to a first clock(CLK1) having a first frequency, and it stores input data temporarily. A source driver(120) drives a panel by receiving the data from the timing controller. The timing controller generates a second clock(CLK2) having a second frequency lower than the first frequency. The timing controller supplies data which is temporarily stored to the source driver by using the second clock.

Description

Display device capable of reducing the transmission channel frequency between the timing controller and the display driving circuit

The present invention relates to a display apparatus, and more particularly, to a display apparatus having a reduced transmission channel frequency between a timing controller and a display driving circuit.

In recent years, the development direction of the liquid crystal panel display device is typically the high resolution display and the enlargement of the panel size. According to the development direction of the display device as described above, since more data is required to be transmitted within the same time, a transmission channel between a timing controller (TCON) and a driver IC included in the display device is provided. In this case, the transmission frequency is required to be increased when data is transmitted through the transmission channel.

Due to the characteristics of the data transmission channel between the driving integrated circuit and the timing controller, the characteristics of the signal may be degraded due to impedance mismatch. Therefore, there is a limit in increasing the data transmission speed by increasing the frequency of the channel. In order to overcome this problem, the number of transmission channels can be increased, but in this case, an increase in electromagnetic interference (EMI) may occur, and the overall cost increases due to an increase in complexity on the PCB board. Done.

1 is a block diagram illustrating some components of a general display apparatus. As shown, the general display apparatus 10 may include a timing controller 11, a source driver 12, and a panel 13. In addition, in order to perform other functions of the apparatus, the display apparatus 10 may include other functional blocks such as a gate driver, a driving voltage generator, and a gray voltage generator, and detailed illustration and description thereof will be omitted.

The timing controller 11 generates and provides a control signal for controlling an operation of the source driver unit 12 and the like, and also provides externally provided data to the panel 13 so that an image is implemented on the panel driver unit 12. To provide the operation. As shown in FIG. 1, the timing controller 11 receives video data Data, a clock signal CLK, and the like from an external graphic controller (not shown). In addition, the provided data Data is provided to the source driver unit 12 without any change.

In general, the timing controller 11 uses the clock signal CLK provided from an external graphic controller as an overall operation clock signal. That is, in providing the data (Data) received from an external graphic controller to the source driver unit 12, the data (data) is the source driver unit 12 using the clock signal CLK as the transmission clock of the channel. To provide.

The source driver 12 receives data Data as a speed corresponding to the frequency of the clock signal CLK. As a transmission method of the data Data and the clock signal CLK between the timing controller 11 and the source driver unit 12, a point-to-point method, a multi-drop method, and the like. Several methods can be applied. The source driver 12 may include a plurality of source drivers S / D1 to S / Dn to drive the source lines of the panel 13. The source driver unit 12 causes an image to be implemented on the panel 13 with a gray level corresponding to the provided data.

A data transmission operation between the timing controller 11 and the source driver unit 12 will be described with reference to FIG. 2 as follows.

2 is a waveform diagram illustrating a data transfer characteristic between a timing controller and a source driver unit according to a conventional scheme. FIG. 2 shows a section in which the vertical sync signal Vsync, the horizontal sync signal Hsync, and valid data are transmitted to show data transmission characteristics. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be provided to the timing controller 11 from an external graphic controller, or may be generated in the timing controller 11 in response to a predetermined data enable signal. .

As an example, when the frame refresh rate is 60 hertz (Hz) and the panel is driven at a resolution of SXGA (1280 * 1024), data is transmitted from the external graphic controller to the timing controller 11. The frequency of the clock is determined to be 108 megahertz (Mhz) corresponding to 60 * Horizontal_total * Vertical_total, and the frequency of the clock determined as described above is determined by the timing controller 11 and the source driver unit 12. It is used as the clock frequency at the time of data transfer between the data. However, at the SXGA-class resolution, the effective pixel bandwidth is 78 megapixels / sec (MPixel / Sec) corresponding to 60 * horizontal resolution (Horizontal_res) * vertical resolution (Vertical_res). Therefore, as the horizontal blank section and the vertical blank section are applied to the horizontal section and the vertical section, respectively, in addition to the valid section in which valid data is provided, the frequency of the transmission channel increases by about 38%. Will result.

As shown in FIG. 2, a vertical blank section is applied to each period of the vertical sync signal Vsync, and the vertical blank section is a section in which valid data starts to be input after a transition of the vertical sync signal Vsync (for example, , A section including a vertical back porch (VBP) and a vertical front porch (VFP) section. Also, as shown, each period of the horizontal sync signal Hsync is also applied with a horizontal blank section, and the horizontal blank section is a section in which valid data starts to be input after the transition of the horizontal sync signal Hsync (for example, Section including a horizontal back porch (HBP) and a horizontal front porch (HFP) section.

In the case of the Reduced Swing Differential Signaling (RSDS) method, which is generally used as a data transmission method between the timing controller 11 and the source driver unit 12, the limit of the frequency of a stable transmission channel due to physical limitations is approximately 80 megahertz. In the case of driving the panel in the SXGA class as described above, the frequency of the transmission channel becomes 108 megahertz (Mhz), which exceeds the limit. The increase in channel frequency affects the consumption current, heat generation, and EMI emission in the display device. In order to prevent this, a method of extending the number of data buses BUS between the timing controller 11 and the source driver unit 12 may be considered, but this causes a problem of increasing the cost of the display device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a display device capable of improving problems such as increase in current consumption and heat generation caused by an increase in channel frequency during data transmission between a timing controller and a source driver. do.

In order to achieve the above object, the display device according to an embodiment of the present invention, the timing controller for receiving data from the external in response to the first clock having a first frequency, and temporarily storing the input data; A source driver for driving the panel by receiving the data from the timing controller, wherein the timing controller generates a second clock having a frequency lower than that of the first clock, and converts the temporarily stored data into the second clock. It is characterized in that provided to the source driver.

Preferably, the timing controller receives and stores corresponding line data of a frame in response to the first clock during a first period corresponding to a part of each period of a horizontal sync signal Hsync, During the second period having a width greater than the first period, the stored data is provided to the source driver using the second clock.

Also preferably, the timing controller may be configured to convert the line data received in the first section of the previous period of the horizontal synchronization signal Hsync during the second section of the subsequent period of the horizontal synchronization signal Hsync. It is characterized by providing a source driver.

Also preferably, the second section may be a section corresponding to one period of the horizontal synchronization signal Hsync.

The timing controller may include a first interface unit which sequentially receives line data provided from the outside in response to the first clock, a memory unit including at least one line memory for storing the line data, and the And a second interface unit which sequentially supplies the line data stored in the line memory to the source driver unit using a second clock.

The timing controller may further include a frequency converter configured to receive the first clock and generate a second clock having a frequency lower than that of the first clock.

Preferably, the frequency converter is down-scaling the first clock to a value corresponding to a ratio of a valid period in which actual valid data is transmitted from the outside of the period of the horizontal sync signal Hsync. To generate the second clock.

Meanwhile, the memory unit may include a first line memory for storing first line data input corresponding to a first period of the horizontal synchronization signal Hsync and a second of the horizontal synchronization signal Hsync adjacent to the first period. And a second line memory for storing second line data input corresponding to the period, wherein any one of the first line memory and the second line memory is configured for any one period of the horizontal synchronization signal Hsync. The line memory stores line data provided from the outside, and the line data stored in the other line memory is read and provided to the source driver.

Preferably, during some period of one period of the horizontal synchronization signal (Hsync), the line data is stored in any one line memory in response to the first clock, and one of the horizontal synchronization signal (Hsync) During the entire period of the period, the line data stored in the other line memory is read in response to the second clock.

The display device may be a liquid crystal display.

According to the display device of the present invention as described above, since the channel frequency can be reduced during data transmission between the timing controller and the source driver, problems such as increase in current consumption and heat generation can be reduced, and the data bus Since there is no need to increase the number of), the overall cost can be prevented from rising.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating some components of a display apparatus according to an exemplary embodiment. As illustrated, the display apparatus 100 may include a timing controller 110 and a source driver 120. In addition, in order to perform other functions of the apparatus, the display apparatus 100 may include other functional blocks such as a gate driver, a driving voltage generator, and a gray voltage generator, and detailed illustration and description thereof will be omitted.

The timing controller 110 receives data Data and a first clock CLK1 from an external graphic controller (not shown), and also other signals, although not shown, for example, a vertical synchronization signal Vsync, The horizontal synchronization signal Hsync and the data enable signal DE may be input. The timing controller 110 generates control signals for controlling the gate driver unit (not shown) and the source driver unit 120 included in the display apparatus 100 based on the input signals. The source driver 120 drives a source line of a panel (not shown) using data and various control signals provided from the timing controller 110. Meanwhile, as mentioned above, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be generated directly by the timing controller 110 using a data enable signal DE provided from the outside.

The timing controller 110 receives the data Data in response to the first clock CLK1 having the first frequency and stores the input data in a predetermined memory unit. Preferably, the predetermined memory unit may include a line memory for storing line data corresponding to one horizontal line of one frame embodied as an image in the display apparatus 100. At least two may be provided.

On the other hand, the timing controller 110 performs down-scaling on the first clock CLK1 provided from the outside, so that the second clock CLK2 having a frequency lower than that of the first clock CLK1 can be obtained. Create The generated second clock CLK2 is used as a transmission clock for transmitting data Data between the timing controller 110 and the source driver unit 120. That is, the timing controller 110 does not use a transmission clock used to receive data from an external graphic controller, but transmits data to the source driver unit 120 using a clock having a lower frequency than this. Therefore, the transmission channel frequencies of the timing controller 110 and the source driver 120 are not increased.

The timing controller 110 receives data corresponding to one frame during one period of the vertical synchronization signal Vsync from an external graphic controller, and also receives the data for one period of the horizontal synchronization signal Hsync. Data corresponding to one horizontal line of a frame is received. One period of the vertical synchronization signal Vsync includes a valid period Vertical_val for providing actual valid data and a blank period for which no valid data is provided. In addition, one period of the horizontal synchronization signal Hsync also includes a valid period (Horizental_val) where actual valid data is provided and a blank period where no valid data is provided.

When the panel is driven, the effective pixel bandwidth (Band-width) has a value corresponding to Frame refresh rate * H_res * V_res pixels / sec (Frame refresh rate is frame refresh rate, H_res is horizontal resolution, and V_res is Vertical resolution). Meanwhile, the frequency of the clock for data transmission between the external graphic controller and the timing controller 110 is determined as a value corresponding to Frame refresh rate * V_res (1 + V_blank) * H_res (1 + H_blank) (V_blank is Vertical blank interval, H_blank is the horizontal blank interval).

In general, according to the Video Electronics Standards Association (VESA) standard, the vertical blank section (V_blank) and about 30% of the horizontal blank section (H_blank) is included, and the timing controller 110 is 60 hertz (60 Hz). When driven at a frame refresh rate of Hz, the effective pixel band-width corresponds to 78 MPixels / Sec, and the frequency of the first clock CLK1 is about 108 MHz. It is determined by (Mhz). As the blank period exists, the frequency of the first clock CLK1 has a larger value than the effective pixel bandwidth.

A detailed operation of the timing controller 110 for reducing the transmission channel frequencies of the timing controller 110 and the source driver 120 will be described below.

As shown in FIG. 3, the timing controller 110 may include a first interface unit I / F1 and 111 and a second interface unit I / F2 and 112. In addition, the timing controller 110 may further include a line memory unit 112 and a memory controller 113 as a memory unit for storing data provided from the outside, and a first clock provided from the outside. The frequency converter 115 may further include a second clock CLK2 having a lower frequency than the first clock CLK1 using the CLK1. As the frequency converter 115, a phase locked loop (PLL), a delay locked loop (DLL), or the like may be applied.

The first interface unit 111 receives data Data provided from the outside in response to the first clock CLK1 having a high frequency. Data provided through the first interface unit 111 is stored in the line memory unit 112 under the control of the memory controller 113. The line memory unit 112 may include a plurality of line memories for storing line data corresponding to one line of a frame. Preferably, a first line memory and a second line memory for storing the previous line data and the subsequent line data may be provided.

Meanwhile, the first clock CLK1 input through the first interface unit 111 is provided to the frequency converter 115. The frequency converter 115 down-scales the first clock CLK1 having a high frequency to generate a second clock CLK2 having a lower frequency. Down-scaling may be performed such that the frequency of the second clock CLK2 is lower than the frequency of the first clock CLK1. Preferably, the period of the horizontal synchronization signal Hsync (the entire period including the blank period) Down-scaling the first clock CLK1 to a value corresponding to a ratio of the horizontal resolution (interval) to the horizontal resolution (interval at which valid line data is transmitted). As an example, when the horizontal blank section occupies about 30% in one period of the horizontal sync signal Hsync, the frequency of the second clock CLK2 may lower the frequency by about 30% compared to the first clock CLK1. Can be.

 Meanwhile, the line data stored in the line memory unit 112 is read and provided to the second interface unit 112, and the second interface unit 112 supplies the second clock CLK2 having a relatively low frequency. The read line data is provided to the source driver unit 120 by using the read line data. The second clock CLK2 generated by the frequency converter 115 may be provided to the memory controller 113, and a line stored in the line memory unit 112 as a speed corresponding to the frequency of the second clock CLK2. Data is read.

4 is a block diagram illustrating in detail the line memory unit 112 illustrated in FIG. 3. As shown, the line memory unit 112 may include a plurality of line memories for storing line data, and may preferably include a first line memory 112_1 and a second line memory 112_2. . In addition, one or more multiplexers 112_3 and 112_4 for switching addresses, data, and the like provided to the first line memory 112_1 and the second line memory 112_2, and the first line memory 112_1 and the second line memory. A multiplexer 112_5 for selecting the line data output from the 112112 may be further provided.

First, when line data w-data corresponding to the first line of a frame is provided corresponding to the first period of the horizontal synchronization signal Hsync, a line for storing the line data w-data is provided. The line unit w-data and the write address Write_addr are provided to the memory unit 112. The line data w-data and the write address Write_addr may be provided to the first line memory 112_1 by the operations of the multiplexers 112_3 and 112_4. One or more control signals CON1 and CON2 may be provided to the line memory unit 112 to control the multiplexers 112_3, 112_4 and 112_5 illustrated in FIG. 4, and the one or more control signals CON1 and CON2. May be generated in the memory controller 113.

Accordingly, the line data w-data is stored in the first line memory 112_1 at a speed corresponding to a relatively high frequency of the first clock CLK1. In addition, the line data w-data is not stored in the first line memory 112_1 over the entire period of the first period of the horizontal synchronization signal Hsync, but the horizontal synchronization signal Hsync in which actual valid data is provided. The line data w-data is stored in the first line memory 112_1 only during the valid period of.

Meanwhile, line data w-data corresponding to the second line of the frame is provided corresponding to the second period of the horizontal synchronization signal Hsync. During the second period of the horizontal synchronization signal Hsync, the line data w-data corresponding to the second line is stored in the line memory unit 112 and is also stored in the first line stored in the line memory unit 112. The corresponding line data w-data is provided to the source driver unit 120.

To this end, in response to the control signals CON1 and CON2, line data w-data corresponding to the second line and a write address Write_addr corresponding thereto are provided to the second line memory 112_2. The line data w-data corresponding to the second line is stored in the second line memory 112_2 according to the write address Write_addr. As described above, the first clock CLK1 provided from the outside is used as a clock signal for the write operation of the line memory unit 112, and a partial section (valid data) of the second period of the horizontal synchronization signal Hsync is The line data w-data is stored in the second line memory 112_2 only during the provided period).

Meanwhile, the line data w-data corresponding to the first line stored in the first line memory 112_1 is read during the second period of the horizontal synchronization signal Hsync and provided to the source driver 120. To this end, a read address Read_addr is provided to the first line memory 112_1 in response to the control signals CON1 and CON2. As the clock signal for the read operation of the line memory unit 112, a second clock CLK2 having a relatively low frequency generated by the frequency converter 115 is used. The line data w-data is read from the first line memory 112_1 at a speed corresponding to the frequency of the second clock CLK2, and under the control of the control signal CON2, the line data corresponding to the first line ( w-data) is provided to the source driver unit 120 through the multiplexer 112_5. When reading line data w-data, a read operation may be performed over the entire period of the second period of the horizontal synchronization signal Hsync.

Subsequently, during the third period of the horizontal synchronization signal Hsync, the line data w-data corresponding to the third line is stored in the first line memory 112_1 and also stored in the second line memory 112_2. The line data w-data corresponding to the second line is read and provided to the source driver 120. That is, during one period of the horizontal synchronization signal Hsync, one of the first line memory 112_1 and the second line memory 112_2 is used for data storage, and the other memory is used for reading. use. By repeating the above operation, data corresponding to one or more frames is provided from the timing controller 110 to the source driver unit 120.

5 is a waveform diagram illustrating characteristics of line data provided to the timing controller 110 and line data provided to the source driver unit 120. As shown, one period of the horizontal synchronization signal Hsync includes a valid section DE and a blank section. The blank period may include a pulse width of the horizontal sync signal Hsync, a horizontal back porch HBP, and a horizontal front porch HFP.

The timing controller 110 receives the first line data 1st Line in response to the first clock CLK1 and stores it in the line memory unit 112. The timing controller 110 receives the first line data 1st Line during a portion of the one period of the horizontal synchronization signal Hsync (the valid period DE) and has a relatively high transmission channel frequency.

On the other hand, in the line data transmission between the timing controller 110 and the source driver unit 120, the data is transmitted for a period larger than the valid period DE of the horizontal synchronization signal Hsync, and thus, relatively low. It may have a transmission channel frequency. Preferably, the line data may be transmitted over one period of the horizontal sync signal Hsync.

6 is a graph illustrating transmission frequency characteristics between the timing controller 110 and the source driver 120 according to the present invention in comparison with the related art. In FIG. 6A, a bandwidth of a channel when bypassing the input line data without performing buffering using a memory is shown. As shown in the drawing, an overhead corresponding to the blank period is transferred to the channel between the timing controller 110 and the source driver 120 to have a large transmission frequency of the channel.

On the other hand, in FIG. 6B, the bandwidth of the channel when buffering the input line data and downscaling the transmission frequency of the channel is shown. By efficiently using the blank period, the transmission frequency of the channel can be lowered by a ratio corresponding to the overhead of the horizontal synchronization signal Hsync.

On the other hand, based on the above-described description, by using the blank period existing in the vertical synchronizing signal (Vsync) efficiently it is also possible to apply the lower the transmission frequency of the channel. In this case, a memory for buffering frame data corresponding to one period of the vertical synchronization signal Vsync is needed, and the ratio corresponds to the overhead of the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. The transmission frequency of the channel can be lowered further.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram illustrating some components of a general display apparatus.

2 is a waveform diagram illustrating a data transfer characteristic between a timing controller and a source driver unit according to a conventional scheme.

3 is a block diagram illustrating some components of a display apparatus according to an exemplary embodiment.

4 is a block diagram illustrating in detail the line memory unit illustrated in FIG. 3.

5 is a waveform diagram illustrating characteristics of line data provided to a timing controller and line data provided to a source driver unit.

6 is a graph illustrating transmission frequency characteristics between a timing controller and a source driver unit according to the present invention in comparison with the related art.

  Explanation of symbols on the main parts of the drawings

100: display device

110: timing controller

111: first interface unit

112: line memory section

113: memory controller

114: second interface unit

115: frequency converter

120: source driver

Claims (10)

A timing controller configured to receive data in response to a first clock having a first frequency from an external source and temporarily store the input data; And A source driver for driving the panel by receiving the data from the timing controller; The timing controller generates a second clock having a frequency lower than that of the first clock, and provides the temporarily stored data to the source driver using the second clock. The method of claim 1, wherein the timing controller, During the first period corresponding to a part of each period of the horizontal sync signal Hsync, the corresponding line data of the frame is received in response to the first clock and stored therein, And displaying the stored data to the source driver unit by using the second clock during a second section having a width greater than the first section. The method of claim 2, wherein the timing controller, And displaying the line data received in the first section of the previous period of the horizontal synchronization signal Hsync to the source driver during the second section of the subsequent period of the horizontal synchronization signal Hsync. Device. The method of claim 3, And the second section is a section corresponding to one period of the horizontal sync signal (Hsync). The method of claim 1, wherein the timing controller, A first interface unit which sequentially receives line data provided from the outside in response to the first clock; A memory unit including at least one line memory for storing the line data; And And a second interface unit which sequentially supplies the line data stored in the line memory to the source driver unit by using the second clock. The method of claim 5, wherein the timing controller, And a frequency converter configured to receive the first clock and generate a second clock having a frequency lower than that of the first clock. The method of claim 6, wherein the frequency converter, The second clock is generated by down-scaling the first clock to a value corresponding to a ratio of a valid period in which actual valid data is transmitted from the outside with respect to a period of a horizontal sync signal Hsync. Display device. The method of claim 6, wherein the memory unit, A first line memory for storing first line data input corresponding to a first period of the horizontal synchronization signal Hsync; And And a second line memory configured to store second line data input corresponding to a second period of the horizontal synchronization signal Hsync adjacent to the first period. For any one period of the horizontal synchronization signal Hsync, either one of the first line memory and the second line memory stores line data provided from the outside and is stored in another line memory. Is read and provided to the source driver. The method of claim 8, During some period of one period of the horizontal synchronization signal (Hsync), the line data is stored in any one line memory in response to the first clock, And displaying line data stored in the other line memory in response to the second clock during the entire period of one period of the horizontal synchronization signal (Hsync). The method of claim 1, The display device is a liquid crystal display (Liquid Crystal Display) characterized in that the display device.

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