CN103676493B - Hybrid photoetching method for reducing line roughness - Google Patents

Abstract

The invention discloses a hybrid photolithography method for reducing line roughness, comprising: forming a structural material layer and a first hard mask layer on a substrate; performing first photolithography/etching on the first hard mask layer forming a first photoresist pattern, etching the first hard mask layer to form a first hard mask pattern; forming a second hard mask layer on the first hard mask pattern; performing a second photolithography/etching, Form a second photoresist pattern on the second hard mask layer, etch the second hard mask layer to form a second hard mask pattern; continue to etch the second hard mask layer and the first hard mask layer, forming a third hard mask pattern; using the third hard mask pattern as a mask, etching the structural material layer to form required lines. According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the roughness of the side wall of the electron beam photoresist from being transmitted to the lower structural material layer, effectively reduces the roughness of the lines, and improves the process. The stability of the device reduces the fluctuation of device performance.

Description

Hybrid lithography approach to reduce line roughness

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, more specifically, to a hybrid photolithography method for reducing line roughness.

Background technique

With the gradual reduction of VLSI feature size, the technical limit of ordinary optical exposure has come after entering the 22nm technology generation in the manufacturing method of semiconductor devices. At present, after the 45nm process node, i193nm immersion lithography technology combined with double exposure and double etching technology is generally used to prepare smaller lines. Fine patterning at nodes below 22nm typically requires exposure and lithography using e-beam or EUV.

Regarding EUV lithography technology, it is still in the research and development stage, and there are still several key technologies that need to be overcome and improved, and it cannot be applied to large-scale integrated circuit manufacturing. In contrast, after years of development, the electron beam exposure technology is relatively mature, and the electron beam exposure has high precision, the resolution can reach several nanometers, and the lines of ultra-fine graphics can be written, but the efficiency is low, so The contradiction between scanning accuracy and scanning efficiency has become the main contradiction in electron beam lithography. The key technology to solve this problem is to solve the problem of matching and mixing lithography technology between the electron beam lithography system and the current optical lithography system with high production efficiency. A feasible method is that most of the processes are exposed by projection lithography machines or contact exposures, and ultra-fine graphics and graphic layers that require particularly high overlay accuracy are exposed by electron beam direct writing.

On the other hand, after entering the 32nm node process, line roughness has become a key issue that must be considered, including line edge roughness (LER) and line width roughness (LWR). For EUV or electron beam technology, the problem of line roughness is encountered. In particular, when the electron beam exposure technology is used, the requirements on the photoresist (resist) are higher, and there is often a contradiction between the line resolution and the thickness of the photoresist. The thinner the photoresist, the smaller the lines can be exposed. However, such a thin photoresist is often lost early in the etching process due to the insufficient selectivity of the etching process, and thus cannot produce the desired , and have severe line roughness issues.

Contents of the invention

In view of this, the purpose of the present invention is to be independent of photoresist, combined with a new hard mask technology, so that the roughness of the line is greatly reduced, the process is more stable, and the variation of the threshold voltage is also reduced.

The above object of the present invention is achieved by providing a hybrid photolithography method for reducing line roughness, comprising: forming a structural material layer and a first hard mask layer on a substrate; performing the first photolithography/etching, and Form a first photoresist pattern on the first hard mask layer, etch the first hard mask layer to form a first hard mask pattern; form a second hard mask layer on the first hard mask pattern; perform the second 2. Photolithography/etching, form a second photoresist pattern on the second hard mask layer, etch the second hard mask layer to form a second hard mask pattern; continue to etch the second hard mask layer and The first hard mask layer forms a third hard mask pattern; using the third hard mask pattern as a mask, the structural material layer is etched to form required lines.

Wherein, the first hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride and combinations thereof.

Wherein, the first hard mask layer is a laminated structure of silicon oxide and silicon nitride.

Wherein, the second hard mask layer includes polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous carbon and combinations thereof.

Wherein, the etching of the first hard mask layer and/or the second hard mask layer and/or the structural material layer adopts plasma dry etching technology.

Wherein, plasma dry etching adopts CCP, ICP or TCP equipment.

Wherein, after etching, dry stripping and/or wet etching cleaning are also included.

Among them, wet corrosion cleaning adopts SPM+APM.

Wherein, the structural material layer is one of a dummy gate electrode layer, a metal gate electrode layer, and a local interconnection layer.

Wherein, the first and/or second hard mask layer is prepared by LPCVD, PECVD, HDPCVD, MBE, ALD method.

One of the first photolithography and the second photolithography is a common optical exposure technique, and the other is an electron beam exposure technique.

Among them, ordinary optical exposure technology includes i-line 365nm exposure, DUV248nm exposure, and electron beam exposure is used to prepare lines with a graphic size of 22nm and below.

According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the transfer of the side wall roughness of the electron beam photoresist to the underlying structural material layer, effectively reduces the roughness of the lines, and improves The stability of the process is improved, and the fluctuation of device performance is reduced.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 is a schematic diagram of an electron beam lithography layout;

2 to 7 are schematic cross-sectional views of various steps of the method according to the present invention; and

Fig. 8 is a flowchart of a method according to the present invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower", "thick", "thin" and the like used in this application can be used for Modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.

First of all, referring to attached drawing 1, it is the combined diagram of the first graphic and the second graphic and their disassembled diagrams respectively, that is, the graphics with large line width prepared by ordinary optical exposure technology and the graphics with small line width prepared by electron beam technology, such as grids. Electrode layers, local interconnect layers, etc. Ordinary optical exposure referred to in the present invention refers to a pattern transfer method that uses light to change the properties of photoresist commonly used at present. The electron beam lithography technology does not require a mask, but the exposure time is longer, resulting in low productivity. In the present invention, the first pattern 11 is defined as a pattern within the capability of ordinary optical exposure, that is, a large line pattern in general, and conventional optical exposure techniques such as i-line 365nm exposure and DUV248nm exposure can be used. The second pattern 12 is defined as a pattern beyond the capability of ordinary optical exposure, which needs to be exposed by electron beams, and lines with a pattern size of less than 22nm can be prepared.

Before the overall process is carried out, the graphics are split according to the exposure capability, such as common large line graphics 11 and small line graphics 12, which are used for electron beam fine exposure. Next, the fabrication of grids is taken as an example, and the hybrid exposure technology combining ordinary optics and electron beams is described in detail.

Referring to FIG. 2 , a substrate 1 is provided, and a structural material layer (consisting of a gate insulating layer 2 and a gate conductive layer 3 ) and a hard mask layer 4 are sequentially formed on the substrate 1 and coated with photoresist. The substrate 1 is reasonably selected according to the application requirements of the device, and may include single crystal silicon (Si), SOI, single crystal germanium (Ge), GeOI, strained silicon (Strained Si), silicon germanium (SiGe), or compound semiconductor materials, such as nitrogen Gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, etc. In consideration of compatibility with the CMOS process, the substrate 1 is preferably bulk Si or SOI. The gate insulating layer 2 is deposited on the substrate 1 by methods such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, MBE, ALD, etc., and its material can be silicon oxide, silicon oxynitride, and high-k materials, wherein the high-k materials include But not limited to hafnium-based oxides (such as HfO ₂ , HfSiON, HfLaON), metal oxides (mainly subgroup and lanthanide metal element oxides, such as Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), perovskite phase oxides (such as PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)). A gate conductive layer 3 is formed on the gate insulating layer 2 by deposition methods such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, and sputtering. In the gate-front process, the gate conductive layer 3 is doped polysilicon, metals and nitrides thereof, wherein the metals include Al, Cu, Ti, Ta, W, Mo and combinations thereof. In the gate-last process, the gate conductive layer 3 may be a dummy gate, including polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, etc. and combinations thereof. On the gate conductive layer 3, a hard mask layer 4 is deposited by LPCVD, PECVD, HDPCVD, etc., which can be a single layer or a multilayer stacked structure, and its material can include silicon oxide, silicon nitride, silicon oxynitride and their combinations. In one embodiment of the present invention, the hard mask layer 4 is a multilayer structure of ONO, that is, including a bottom layer of silicon oxide, a middle layer of silicon nitride, and a top layer of silicon oxide (the layered structure of the ONO is not shown in the figure ).

A photoresist 5 is coated on the hard mask 4, which is a photoresist suitable for common optical exposure. The gate conductive layer 3 is a layer to be finally patterned. The gate layer 3 is disassembled to extract the first pattern 11 exposed by ordinary optics, and a corresponding photolithography plate is made. Optical exposure techniques such as I-line 365nm exposure and DUV248nm exposure can be used. Due to the different exposure capabilities of different equipment, the size of the pattern that can be obtained by ordinary optical exposure is also different. For example, if I-line is used, the size of the first pattern 11 is above 350nm, while the size of the first pattern 11 can be obtained by using DUV248nm exposure technology. The size of the first pattern is above 130nm .

Referring to FIG. 3 , the first photoresist plate corresponding to the first pattern 11 is used and the first exposure is performed by ordinary optical exposure technology, and then the first photoresist 5 is patterned by developing and curing processes to form a pattern corresponding to the first pattern 11. A pattern 11 of photoresist pattern 5P.

Then, referring to FIG. 4 , using the photoresist pattern 5P as a mask, the hard mask layer 4 is etched to form a hard mask pattern 4P. Preferably, the etching stops on the middle layer of the silicon nitride material of the hard mask layer 4 of the ONO structure, that is, only the top layer of the silicon oxide material is etched away. Preferably, an anisotropic etching method, such as plasma etching, dry etching of reactive ion etching, is used to obtain vertical lines. The etching gas may be a fluorocarbon-based gas, and may also include an inert gas and an oxidizing gas to adjust an etching rate. The above dry etching equipment may be CCP, ICP or TCP equipment. After the pattern is formed, the photoresist pattern 5P is removed by dry and/or wet stripping process.

Next, referring to FIG. 5 , a second hard mask layer 6 is deposited on the hard mask layer 4 /hard mask pattern 4P by conventional methods such as LPCVD, PECVD, HDPCVD, MBE, and ALD. For example, the second hard mask layer 6 with different materials is deposited on the first hard mask layer 4 by conventional processes such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, and sputtering. The material of layer 6 is, for example, polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous carbon (DLC), etc. and combinations thereof. Optionally, the layer 6 is made of the same material as the gate conductive layer 3 serving as a dummy gate, for example, both are amorphous silicon. Preferably, layer 6 not only includes the above-mentioned polycrystalline or amorphous materials, but also can be stacked with conventional materials such as silicon oxide and silicon nitride, such as amorphous silicon + silicon oxide, amorphous silicon + silicon nitride, amorphous carbon + silicon oxide and so on.

Referring to FIG. 6 , a second photoresist 7 is coated on the second hard mask 6 , which is a photoresist suitable for electron beam direct writing technology, such as PMMA, epoxy 618, COP and so on. Exposure is carried out by electron beam direct writing technology, and developed in a developing solution such as isopropanone to obtain, for example, an ultra-fine pattern at or below the 22nm node, that is, the photoresist pattern 7P shown in the figure. In this process, due to the electron beam direct writing technology and the characteristics of the photoresist itself (such as the proximity effect, etc.), the side of the pattern 7P may not be aligned enough, and the line edge roughness (LER) and line width roughness (LWR) are relatively high. Large, so a hard mask layer, especially layer 6, is required for trim adjustment. The second photoresist pattern 7P in FIG. 6 corresponds to the fine line 12 in FIG. 1 .

Referring to FIG. 7, using the second photoresist pattern 7P as a mask, the hard mask layers 6, 4 are etched to form a hard mask pattern including thick lines and thin lines, and the lines forming the structural material layer are further etched. Specifically, dry etching techniques such as plasma etching and reactive ion etching (RIE) are used to etch the upper second hard mask layer 6 first, and stop on the first hard mask layer 4 (4P) to form A second hard mask pattern with a slightly steeper topography. The etching gas may be a fluorocarbon-based gas, and may also include an inert gas and an oxidizing gas to adjust an etching rate. Wherein, the dry etching equipment may be ICP, TCP, CCP equipment. Then, using the second hard mask pattern as a mask, the above-mentioned dry etching technique is also used to etch the first hard mask layer 4, stopping on the structural material layer (specifically, the gate conductive layer 3) to form a steeper layer. A straight third hard mask pattern 8P made of the material of the first hard mask layer 4 . During this process, the top second hard mask layer/pattern is etched away, leaving only the third hard mask pattern 8P composed of the lower first hard mask layer, where 8PA represents the Thick lines 11, while 8PB represent thin lines 12 corresponding to e-beam lithography. Due to the existence of the second hard mask layer, a preliminary steep pattern is obtained during dry etching, and then a steeper pattern is formed by further etching, thereby avoiding the downward roughness of the side wall of the photoresist pattern. Transferred to the structural material layer 2/3, effectively reducing the roughness of the lines (LER and LWR). Subsequently, preferably, the polymer and its particles generated during the etching process are removed by dry etching and/or wet etching, such as dry etching using fluorine-based plasma etching, wet etching such as SPM (such as Sulfuric acid: hydrogen peroxide = 4: 1)/APM (eg ammonia water: hydrogen peroxide: deionized water = 1: 1: 5 or 0.5: 1: 5) wet cleaning. Afterwards, using the hard mask pattern 8P as a mask, the structural material layer is etched to form final lines. For example, the above-mentioned anisotropic dry etching technique, such as plasma etching, RIE, etc., is used to etch the gate conductive layer 3 until the gate insulating layer 2 is exposed, forming a steep gate electrode pattern 3P. Finally, preferably, the above-mentioned wet etching process is used to remove the polymer formed during the etching process.

An embodiment of the present invention has been described above by taking the etching of gate lines as an example, but in fact, the hybrid photolithography method of the present invention can be applied to various semiconductor structures, and layers 2 and 3 can be any structural material layers, such as hypothetical Gate stack structures, local interconnect structures, top pad structures, and more.

In addition, although the optical lithography/etching is first followed by the electron beam lithography/etching in the embodiment of the present invention, the order can also be reversed, first the electron beam lithography/etching and then the optical lithography/etching.

According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the transfer of the side wall roughness of the electron beam photoresist to the underlying structural material layer, effectively reduces the roughness of the lines, and improves The stability of the process is improved, and the fluctuation of device performance is reduced.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in the method of forming the device structure without departing from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (9)

1. A hybrid photolithography method for reducing line roughness, comprising: forming a structural material layer and a first hard mask layer on the substrate, wherein the first hard mask layer is silicon oxide, silicon nitride, silicon oxynitride or a combination thereof; Performing first photolithography/etching using common optical exposure technology, forming a first photoresist pattern on the first hard mask layer, and etching the first hard mask layer to form a first hard mask pattern; A second hard mask layer is formed on the first hard mask pattern, and the second hard mask layer is polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous carbon or a combination thereof; Performing second photolithography/etching by electron beam exposure technology, forming a second photoresist pattern on the second hard mask layer, and etching the second hard mask layer to form a second hard mask pattern; Continue to etch the second hard mask layer and the first hard mask layer to form a third hard mask pattern; Using the third hard mask pattern as a mask, the structural material layer is etched to form required lines. 2. The method of claim 1, wherein the first hard mask layer is a stacked structure of silicon oxide and silicon nitride. 3. The method according to claim 1, wherein the etching of the first hard mask layer and/or the second hard mask layer and/or the structural material layer adopts plasma dry etching technology. 4. The method according to claim 3, wherein the plasma dry etching adopts CCP or ICP or TCP equipment. 5 . The method according to claim 3 , further comprising dry stripping and/or wet etching cleaning after etching. 6 . 6. The method according to claim 5, wherein the wet etching cleaning adopts SPM+APM. 7. The method according to claim 1, wherein the structural material layer is one of a dummy gate electrode layer, a metal gate electrode layer, and a local interconnection layer. 8. The method of claim 1, wherein the first and/or the second hard mask layer is prepared by LPCVD or PECVD or HDPCVD or MBE or ALD method. 9. The method according to claim 1, wherein the common optical exposure technique is i-line 365nm exposure or DUV248nm exposure, and electron beam exposure is used to prepare lines with a pattern size of 22nm or below.