CN103676493B - Mixed photolithography method capable of reducing line roughness - Google Patents
Mixed photolithography method capable of reducing line roughness Download PDFInfo
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- CN103676493B CN103676493B CN201210357244.6A CN201210357244A CN103676493B CN 103676493 B CN103676493 B CN 103676493B CN 201210357244 A CN201210357244 A CN 201210357244A CN 103676493 B CN103676493 B CN 103676493B
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Abstract
The invention discloses a mixed photolithography method capable of reducing line roughness. The mixed photolithography method comprises the steps of forming a structural material layer and a first hard mask layer on a substrate; carrying out first photolithography/etching to form a first photoresist pattern on the first hard mask layer, and etching the first hard mask layer to form a first hard mask pattern; forming a second hard mask layer on the first hard mask pattern; carrying out second photolithography/etching to form a second photoresist pattern on the second hard mask layer, and etching the second hard mask layer to form a second hard mask pattern; continuously etching the second hard mask layer and the first hard mask layer to form a third hard mask pattern; and with the third hard mask pattern as a mask, etching the structural material layer to form required lines. According to the method, multiple hard mask layers with different materials and multiple etching operations are adopted, and the roughness of the side wall of an electron-beam photoresist is prevented from being transmitted to the lower structural material layer, so that the line roughness is effectively reduced, the process stability is improved and the fluctuations of device performance are reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture field, more particularly, to a kind of the mixed of reduction line roughness
Closing light carving method.
Background technology
As super large-scale integration characteristic size is gradually reduced, in the manufacture method of semiconductor devices, enter
After 22nm technologies generation, the technological limit of common optical exposure has also arrived.At present, after 45nm process nodes, generally adopt
With i193nm immersion lithographies technology the double lithographic techniques of double-exposure are combined to prepare less lines.22nm is with the fine of lower node
Figure generally needs to be exposed using electron beam or EUV and photoetching.
With regard to EUV lithography technology, at present also in development, still there are some key technologies to need to capture and improve, also
Cannot be applied in the middle of large scale integrated circuit manufacture.By contrast, electron beam lithography compares into through development for many years
It is ripe, and electron beam exposure has very high precision, and resolution ratio can reach several nanometers, write out the lines of hyperfine figure
Come, but it is less efficient, thus the contradiction of scanning accuracy and scan efficiency becomes the principal contradiction of beamwriter lithography.Solve this to ask
The key technology of topic is exactly to solve the matching of the higher optical lithography system of electron-beam lithography system and current production efficiency and mix
Closing light lithography problem.A kind of feasible method is that most of technique is exposed or contact exposure by projection mask aligner, hyperfine
Figure and alignment precision require that extra high graph layer adopts e-beam direct-writing exposure.
On the other hand, into after 32nm node techniques, line roughness becomes the key issue that must take into, concrete bag
Include line edge roughness (LER) and line thickness roughness (LWR).For EUV or electron beam technology, all can run into
The problem of line roughness.Especially, when electron beam lithography is adopted, the requirement to photoresist (resist) is higher, often
There is contradiction between lines resolution ratio and photoresist thickness.Thinner photoresist more can expose less lines, however, this
The thin photoresist of sample often can be lost early due to the not high enough selectivity of etching technics in etching process, and then cannot
Required lines are obtained, and there are problems that serious line roughness.
The content of the invention
In view of this, it is an object of the invention to outside independently of photoresist, with reference to a kind of new hard mask technology so that
Line roughness is substantially reduced so that technique is more stable, and the change of threshold voltage is also minimized.
Realize the present invention above-mentioned purpose, be by provide it is a kind of reduce line roughness mixing photoetching method, including：
Structural material and the first hard mask layer are formed on substrate；The first photoetching/etching is performed, is formed on the first hard mask layer
One photoetching offset plate figure, etches the first hard mask layer, forms the first hard mask figure；Second is formed on the first hard mask figure hard
Mask layer；The second photoetching/etching is performed, the second photoetching offset plate figure is formed on the second hardmask layer, etch the second hard mask layer,
Form the second hard mask figure；Continue to etch the second hard mask layer and the first hard mask layer, form the 3rd hard mask figure；With
Three hard mask figures are mask, and etching structure material layer forms required lines.
Wherein, the first hard mask layer includes silica, silicon nitride, silicon oxynitride and combinations thereof.
Wherein, the first hard mask layer is the laminated construction of silica and silicon nitride.
Wherein, the second hard mask layer includes polysilicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium, SiC, SiGe, eka-gold
Hard rock amorphous carbon and combinations thereof.
Wherein, the etching using plasma of the first hard mask layer and/or the second hard mask layer and/or structural material is done
Method lithographic technique.
Wherein, plasma dry etch is using CCP or ICP or TCP equipment.
Wherein, also remove photoresist including dry method after etching and/or wet etching cleaning.
Wherein, wet etching cleaning adopts SPM+APM.
Wherein, structural material is the one kind in false gate electrode layer, metal gate electrode layer, local interlinkage layer.
Wherein, the first and/or second hard mask layer is prepared using LPCVD, PECVD, HDPCVD, MBE, ALD method.
One of first photoetching and the second photoetching are ordinary optical exposure technique, and another is electron beam lithography.
Wherein, ordinary optical exposure technique includes i lines 365nm exposures, DUV248nm exposures, and electron beam exposure is used to prepare
Dimension of picture is 22nm and the lines with lower node.
According to the method for the present invention, using the different multilayer hard mask layer of material and multiple etching, it is therefore prevented that electron beam
Photoresist sidewall roughness is delivered to the structural material of lower floor, effectively reduces the roughness of lines, improves the steady of technique
It is qualitative, reduce the fluctuation change of device performance.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 is the schematic diagram of beamwriter lithography domain；
Fig. 2 to Fig. 7 is the generalized section according to each step of the method for the present invention；And
Fig. 8 is according to the flow chart of the method for the present invention.
Specific embodiment
The feature and its skill of technical solution of the present invention are described in detail referring to the drawings and with reference to schematic embodiment
Art effect.It is pointed out that similar reference represents similar structure, term " first " use herein, " the
Two ", " on ", D score, " thickness ", " thin " etc. can be used to modify various device architectures.These modifications are not dark unless stated otherwise
Show space, order or the hierarchical relationship of modified device architecture.
First, the combination figure and its fractionation diagram of refer to the attached drawing 1, respectively the first figure and second graph, i.e., using general
Little live width figure such as gate electrode layer, local interlinkage that big live width figure prepared by thang-kng exposure technique is prepared with electron beam technology
Layer etc..Ordinary optical exposure alleged in the present invention, the figure that the change of photoresist property is caused with light generally adopted before feeling the pulse with the finger-tip
Shape transfering means.And electron beam lithography is then without mask plate, but the time for exposure is longer, causes production capacity low.In the present invention
In, the first figure 11 is defined as the figure in the limit of power of ordinary optical exposure, namely the big bargraphs generally said,
Can be using normal optical exposure techniques such as i lines 365nm exposures, DUV248nm exposures.Second graph 12 be defined as beyond
The limit of power of ordinary optical exposure, needs using the figure of electron beam exposure, can prepare dimension of picture less than below 22nm
The lines of node.
Before integrated artistic is carried out, inserting drawing is carried out according to exposure capability, such as common big bargraphs 11, and little line
Bar figure 12, finely exposes for electron beam.Next, by make grid as a example by illustrate, specifically describe ordinary optical with
The mixed exposure technology that electron beam combines.
With reference to Fig. 2, there is provided substrate 1, structural material is sequentially formed on substrate 1 (by gate insulator 2, Gate Electrode Conductive
Layer 3 is constituted) and hard mask layer 4, and coat photoresist.Substrate 1 needs and reasonable selection according to device application, it may include single
Crystalline silicon (Si), SOI, monocrystal germanium (Ge), GeOI, strained silicon (Strained Si), germanium silicon (SiGe), or compound half
Conductor material, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors
Such as Graphene, SiC, carbon nanotube etc..For the consideration compatible with CMOS technology, substrate 1 is preferably body Si or SOI.
Deposit to form gate insulator by the method such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, MBE, ALD on substrate 1
2, its material can be silica, silicon oxynitride, high-g value, and wherein high-g value includes but is not limited to hafnium base oxide (for example
HfO2, HfSiON, HfLaON), metal oxide (predominantly subgroup and lanthanide element oxide, such as Al2O3、Ta2O5、
TiO2、ZnO、ZrO2、CeO2、Y2O3、La2O3), Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3
(BST)).Formed by deposition process such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputterings on gate insulator 2
Grid conducting layer 3.In front grid technique, grid conducting layer 3 is DOPOS doped polycrystalline silicon, metal and its nitride, wherein the metal
Including Al, Cu, Ti, Ta, W, Mo and combinations thereof.In rear grid technique, grid conducting layer 3 can be false grid, including polysilicon,
Non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium etc. and combinations thereof.By LPCVD, PECVD, HDPCVD etc. on grid conducting layer 3
Method deposited hard mask layer 4, its can be individual layer can also be multilayer stepped construction, its material can include silica, nitrogen
SiClx, silicon oxynitride and combinations thereof.In an embodiment of the invention, hard mask layer 4 is the sandwich construction of ONO, namely including
The top layer (hierarchy of the ONO is not shown in figure) of the bottom of silica, the middle level of silicon nitride and silica.
Photoresist 5 is coated on hard mask 4, to be adapted to the photoresist of ordinary optical exposure.Grid conducting layer 3 is will be most
The layer being patterned eventually.Grid layer 3 is split, the first figure 11 of ordinary optical exposure is extracted, and is made corresponding
Reticle.Can be using optical exposure technologies such as I lines 365nm exposures, DUV248nm exposures.Due to the exposure capability of distinct device
Difference, the getable dimension of picture of ordinary optical exposure institute also has difference, such as adopts I lines, the size of the first figure 11 be 350nm with
On, and available first dimension of picture of DUV248nm exposure techniques is adopted for the size of more than 130nm.
With reference to Fig. 3, using the first reticle corresponding to the first figure 11 and using ordinary optical exposure technique the is carried out
One exposure, then by development and solid glue technique, the first photoresist 5 is patterned, and forms the photoetching corresponding to the first figure 11
Glue pattern 5P.
Then, with reference to Fig. 4, with photoetching agent pattern 5P as mask, etch hard mask layer 4 forms hard mask pattern 4P.It is preferred that
Ground, etching stopping is on the middle level of the silicon nitride material of the hard mask layer 4 of ONO structure, namely only etching eliminates silica material
The top layer of matter.Preferably, using anisotropic lithographic method, the dry method of such as plasma etching, reactive ion etching is carved
Erosion, to obtain vertical lines.Etching gas can be carbon fluorine base gas, and also can include inert gas and oxidation
Property gas is adjusting etch rate.Above-mentioned dry etching equipment can be CCP or ICP or TCP equipment.After forming figure, by
Dry method and/or wet method degumming process remove photoetching agent pattern 5P.
Next, with reference to Fig. 5, by conventional methods such as LPCVD, PECVD, HDPCVD, MBE, ALD, in hard mask layer 4/
Redeposited second hard mask layer 6 on hard mask pattern 4P.For example, by LPCVD, PECVD, HDPCVD, MBE, ALD, evaporate, splash
The common process such as penetrate, the second different hard mask layer 6 of material is deposited on the first hard mask layer 4.The material of layer 6 is, for example, polycrystalline
Silicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium, SiC, SiGe, DLC amorphous carbon (DLC) etc. and combinations thereof.It is optional
Ground, layer 6 is identical with the material of the grid conducting layer 3 as false grid, for example, be non-crystalline silicon.Preferably, layer 6 not only includes upper
Polycrystalline or non-crystalline material are stated, the lamination with the conventional material such as silica, silicon nitride is can also be, such as non-crystalline silicon+silica,
Non-crystalline silicon+silicon nitride, amorphous carbon+silica etc..
With reference to Fig. 6, the second photoresist 7 is coated on the second hard mask 6, to be adapted to the photoetching of direct electronic beam writing technology
Glue, such as PMMA, epoxy 618, COP etc..It is exposed using direct electronic beam writing technology, is developed in the developer solutions such as isopropyl acetone
Draw for example in 22nm nodes or following hyperfine figure, namely the photoetching offset plate figure 7P shown in figure.In the process, by
In the characteristic (such as kindred effect etc.) of direct electronic beam writing technology and photoresist itself, the side of figure 7P may be not accurate enough
Directly, line edge roughness (LER) and line thickness roughness (LWR) are larger, it is therefore desirable to which hard mask layer is particularly layer 6 to repair
Decorations adjustment.The second photoetching offset plate figure 7P in Fig. 6 is corresponding to the fine lines 12 in Fig. 1.
With reference to Fig. 7, with the second photoetching offset plate figure 7P as mask, etch hard mask layer 6,4, formation includes thick lines and fine rule
The hard mask figure of bar, and further etching forms the lines of structural material.Specifically, using plasma etching, anti-
The dry etching technologies such as ion etching (RIE) are answered, second hard mask layer 6 on upper strata is first etched, the first hard mask layer 4 is stopped at
(4P) on, the second hard mask figure with slightly steeper straight pattern is formed.Etching gas can be carbon fluorine base gas, and also can
To include inert gas and oxidizing gas to adjust etch rate.Wherein, dry etching equipment can be ICP, TCP, CCP
Equipment.Then with the second hard mask figure as mask, equally using above-mentioned dry etching technology, the first hard mask layer 4 is etched, is stopped
Only on structural material (specially grid conducting layer 3), form that the more steep material by the first hard mask layer 4 constitutes the
Three hard mask figure 8P.In the process, second hard mask layer at top/figure is etched removal, only the first of remaining lower floor
The 3rd hard mask figure 8P that hard mask layer is constituted, wherein 8PA represent the thick lines 11 corresponding to common photoetching, and 8PB is represented
Corresponding to the hachure 12 of beamwriter lithography.Due to the presence of the second hard mask layer so that first obtain preliminary steep during dry etching
Straight figure, then proceedes to deep etching and forms more steep figure, it is possible thereby to avoid photoetching offset plate figure sidewall roughness to
Under be transferred to structural material 2/3, effectively reduce the roughness (LER and LWR) of lines.Advantageously, then, carved using dry method
Erosion and/or wet corrosion technique remove the polymer and its particle produced in etching process, and dry etching is for example with fluorine-based etc.
Plasma etching, wet etching such as SPM (such as sulfuric acid: hydrogen peroxide=4: 1)/APM (such as ammoniacal liquor: hydrogen peroxide: deionized water
=1: 1: 5 or 0.5: 1: 5) wet-cleaning.Afterwards, with hard mask figure 8P as mask, etching structure material layer forms final
Lines.For example with above-mentioned anisotropic dry etching technology, such as plasma etching, RIE, etching grid conductive layer
3 until exposure gate insulator 2, defines steep gate electrode pattern 3P.Preferably, using above-mentioned wet corrosion technique finally
Remove the polymer formed in etching process.
Illustrate one embodiment of the present of invention by taking etching grid lines as an example above, but mixing actually of the invention
Photoetching method can apply to various semiconductor structures, and layer 2 and 3 can be any structural material, for example false grid stacking
Structure, local interlinkage structure, top welding pad structure etc..
In addition, although be beamwriter lithography/etching after first optical lithography/etching in the embodiment of the present invention, but actually
Order, first beamwriter lithography/etching and then optical lithography/etching can also be exchanged.
According to the method for the present invention, using the different multilayer hard mask layer of material and multiple etching, it is therefore prevented that electron beam
Photoresist sidewall roughness is delivered to the structural material of lower floor, effectively reduces the roughness of lines, improves the steady of technique
It is qualitative, reduce the fluctuation change of device performance.
Although with reference to one or more exemplary embodiments explanation present invention, those skilled in the art could be aware that need not
Depart from the scope of the invention and various suitable changes and equivalents are made to the method for formation device architecture.Additionally, public by institute
The teaching opened can make many and can be adapted to the modification of particular condition or material without deviating from the scope of the invention.Therefore, the present invention
Purpose do not lie in and be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, it is and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (9)
1. it is a kind of reduce line roughness mixing photoetching method, including：
Structural material and the first hard mask layer are formed on substrate, wherein, the first hard mask layer is silica, silicon nitride, nitrogen
Silica or its combination；
First photoetching/etching is performed using ordinary optical exposure technique, the first photoetching offset plate figure is formed on the first hard mask layer,
The first hard mask layer is etched, the first hard mask figure is formed；
Form the second hard mask layer on the first hard mask figure, the second hard mask layer is polysilicon, non-crystalline silicon, microcrystal silicon, non-
Brilliant carbon, amorphous germanium, SiC, SiGe, DLC amorphous carbon or its combination；
Second photoetching/etching is performed using electron beam lithography, the second photoetching offset plate figure is formed on the second hardmask layer, carved
The second hard mask layer is lost, the second hard mask figure is formed；
Continue to etch the second hard mask layer and the first hard mask layer, form the 3rd hard mask figure；
With the 3rd hard mask figure as mask, etching structure material layer, the lines required for being formed.
2. the method for claim 1, wherein the first hard mask layer is the laminated construction of silica and silicon nitride.
3. the method for claim 1, wherein the first hard mask layer and/or the second hard mask layer and/or structural material
Etching using plasma dry etching technology.
4. method as claimed in claim 3, wherein, plasma dry etch is using CCP or ICP or TCP equipment.
5. method as claimed in claim 3, wherein, also remove photoresist including dry method after etching and/or wet etching cleaning.
6. method as claimed in claim 5, wherein, wet etching cleaning adopts SPM+APM.
7. the method for claim 1, wherein structural material is false gate electrode layer, metal gate electrode layer, local interlinkage
One kind in layer.
8. the method for claim 1, wherein the first and/or second hard mask layer using LPCVD or PECVD or
It is prepared by HDPCVD or MBE or ALD methods.
9. the method for claim 1, wherein ordinary optical exposure technique is that i lines 365nm exposes or DUV248nm exposes
Light, electron beam exposure is used to prepare dimension of picture for 22nm and the lines with lower node.
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| US10026645B2 (en) * | 2016-08-31 | 2018-07-17 | Globalfoundries Inc. | Multiple patterning process for forming pillar mask elements |
| CN108227412A (en) * | 2016-12-15 | 2018-06-29 | Imec 非营利协会 | Photolithographic mask layer |
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| US7393613B2 (en) * | 2003-03-07 | 2008-07-01 | Infineon Technologies Ag | Set of at least two masks for the projection of structure patterns |
| CN101441979A (en) * | 2007-11-19 | 2009-05-27 | 上海华虹Nec电子有限公司 | Method for optimizing silicon chip etching condition |
| CN102096335A (en) * | 2010-12-31 | 2011-06-15 | 上海集成电路研发中心有限公司 | Double-exposure method |
| CN102543748A (en) * | 2010-12-31 | 2012-07-04 | 中国科学院微电子研究所 | Manufacturing method of semi-conductor device |
| CN102591139A (en) * | 2011-01-13 | 2012-07-18 | 中国科学院微电子研究所 | Photoetching method of superfine structure |
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| US7696057B2 (en) * | 2007-01-02 | 2010-04-13 | International Business Machines Corporation | Method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
| KR101105431B1 (en) * | 2010-03-29 | 2012-01-17 | 주식회사 하이닉스반도체 | Method for fabricating fine pattern |
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|---|---|---|---|---|
| US7393613B2 (en) * | 2003-03-07 | 2008-07-01 | Infineon Technologies Ag | Set of at least two masks for the projection of structure patterns |
| CN101441979A (en) * | 2007-11-19 | 2009-05-27 | 上海华虹Nec电子有限公司 | Method for optimizing silicon chip etching condition |
| CN102096335A (en) * | 2010-12-31 | 2011-06-15 | 上海集成电路研发中心有限公司 | Double-exposure method |
| CN102543748A (en) * | 2010-12-31 | 2012-07-04 | 中国科学院微电子研究所 | Manufacturing method of semi-conductor device |
| CN102591139A (en) * | 2011-01-13 | 2012-07-18 | 中国科学院微电子研究所 | Photoetching method of superfine structure |
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