CN102543748A - Manufacturing method of semi-conductor device - Google Patents
Manufacturing method of semi-conductor device Download PDFInfo
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- CN102543748A CN102543748A CN2010106205789A CN201010620578A CN102543748A CN 102543748 A CN102543748 A CN 102543748A CN 2010106205789 A CN2010106205789 A CN 2010106205789A CN 201010620578 A CN201010620578 A CN 201010620578A CN 102543748 A CN102543748 A CN 102543748A
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Abstract
The invention relates to a manufacturing method of a semi-conductor device, which is a mixed exposure method integrating ordinary optical exposure and electronic beam exposure; the method comprises the following steps that: the same layer comprising large lines and fine lines is patterned, wherein the large lines are exposed by ordinary optical exposure, the fine lines are exposed by electronic beam exposure; and consequently, while the forming quality of the fine lines is ensured, the exposure time is reduced, and the yield is improved.
Description
Technical field
The present invention relates to a kind of manufacturing approach of semiconductor device, especially, relate to the mixed exposure method that a kind of electron beam exposure combines with the ordinary optical exposure.
Background technology
Along with constantly dwindling of feature sizes of semiconductor devices, in the manufacturing approach of semiconductor device, the technological limit of common optical exposure also arrives gradually.At present; In the ordinary optical exposure technique that generally adopts; I line source 365nm can make public to the lines of 350nm and above size, and quasi-molecule laser source 248nm/193nm comprises immersion 193nm; Can be used for making characteristic size in 20nm and above semiconductor device, and be difficult to realize exposure the following fine pattern of 20nm with traditional ordinary optical exposure technique.Fine pattern below the 20nm need adopt electron beam or EUV to make public and photoetching usually.About the EUV exposure, still have some key technologies to capture at present, and immature, comparatively speaking, electron beam lithography is with regard to comparative maturity.Electron beam exposure does not need mask, but the time of electron beam exposure is longer, and this can cause production capacity low.
On the whole, the advantage of ordinary optical exposure be the to make public production capacity of big lines is high, and inferior position is the fine pattern that can't make public, and the advantage of electron beam exposure is to carry out the exposure of fine pattern, but the time for exposure is long, production capacity is low.Therefore, need develop a kind of new technology, can make public, thereby can significantly not increase the time for exposure again influences production capacity fine pattern.
Summary of the invention
The mixed exposure method that the present invention adopts electron beam exposure and ordinary optical exposure to combine; Same level figure is split by the lines size; Big lines adopt the ordinary optical exposure, and fine lines strip adoption electron beam exposure is under the prerequisite that does not influence the graph exposure quality; Significantly reduce the time for exposure, improve production capacity.
The present invention provides a kind of manufacturing approach of semiconductor device, comprising:
Substrate is provided, and is positioned at the patterned layer on the said substrate;
The mixed exposure method that adopts ordinary optical exposure and electron beam exposure to combine carries out patterning to said patterned layer, wherein:
The exposure limit of power of the exposure sources that exposure is adopted according to said ordinary optical; To said patterned layer the figure that will form analyze; Split out first figure and second graph; Wherein, said first figure is defined in the figure in the exposure limit of power of the exposure sources that the exposure of said ordinary optical adopts, and said second graph is defined as the exposure limit of power that exceeded the exposure sources that said ordinary optical exposure adopts and the figure of needs employing electron beam exposure;
On said patterned layer, apply first photoresist, adopt the ordinary optical exposure that said first photoresist is made public, through developing and solid adhesive process, with the said first photoresist patterning, said first photoresist of patterning is corresponding to said first figure;
On said patterned layer, apply second photoresist, adopt electron beam exposure that said second photoresist is made public, through developing and solid adhesive process, with the said second photoresist patterning, said second photoresist of patterning is corresponding to said second graph;
With first photoresist of patterning and second photoresist of patterning is mask, and said patterned layer is carried out etching, accomplishes the patterning to said patterned layer.
In the method for the invention, said patterned layer is the patterned layer in the fabrication of semiconductor device, and said patterned layer comprises said first figure and said second graph simultaneously; Said patterned layer is a kind of in polysilicon gate layer, metal gate layers, the interconnection layer;
In the method for the invention, said ordinary optical exposure is I line 365nm exposure, and the size of said first figure is greater than 350nm, and the size of said second graph is less than 350nm;
In the method for the invention, said ordinary optical exposure is the DUV248nm exposure, and the size of said first figure is greater than 130nm, and the size of said second graph is less than 130nm;
In the method for the invention, said ordinary optical exposure is non-immersion quasi-molecule laser source 193nm exposure, and the size of said first figure is greater than 65nm, and the size of said second graph is less than 65nm;
In the method for the invention, said ordinary optical exposure is immersion quasi-molecule laser source 193nm exposure, and the size of said first figure is greater than 20nm, and the size of said second graph is less than 20nm;
The invention has the advantages that: in production process of semiconductor device, the mixed exposure method that adopts ordinary optical exposure and electron beam exposure to combine carries out patterning to the same figure layer that comprises big lines and meticulous lines; Wherein, adopt the ordinary optical exposure that big lines are made public, adopt electron beam exposure that meticulous lines are made public; Like this; In the formation quality of guaranteeing meticulous lines simultaneously, reduce the time for exposure, improved production capacity.
Description of drawings
Comprise first figure and second graph in Fig. 1 patterned layer;
Fig. 2 splits out first figure in the patterned layer;
Fig. 3 splits out the second graph in the patterned layer;
Fig. 4 substrate and position gate oxide and polysilicon gate layer on it;
Fig. 5 applies first photoresist;
Fig. 6 patterning first photoresist;
Fig. 7 applies second photoresist;
Fig. 8 patterning second photoresist;
Fig. 9 patterned polysilicon grid layer;
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention.
At first, referring to accompanying drawing 1, the present invention to carry out patterning patterned layer comprise first figure 11 and second graph 12.Patterned layer can be any patterned layer in the process for fabrication of semiconductor device process; These patterned layers had not only comprised can with the big bargraphs of ordinary optical exposure but also have must be with the meticulous bargraphs of electron beam exposure, like polysilicon gate layer, metal gate layers, interconnection layer etc.Ordinary optical alleged among the present invention makes public, and what refer to the present generally employing of industry causes the figure transfer means that photoresist character changes with light.The limit of power of ordinary optical exposure is according to equipment that it adopted and different; For example: the I line 365nm exposure limit is 350nm; The DUV248nm exposure limit is 130nm; The non-immersion quasi-molecule laser source 193nm exposure limit is 65nm, and the immersion quasi-molecule laser source 193nm exposure limit is 20nm.From present technical merit, the extra fine wire bar that the ordinary optical exposure can make public is of a size of 20nm.In this area; Big lines are meant the lines that the ordinary optical exposure sources can make public; Meticulous lines be meant outside the ordinary optical exposure sources exposure ability must be with the lines of electron beam exposure, more than the concrete live width of two kinds of lines depend on the exposure ability of employed ordinary optical exposure sources.In general; The advantage of ordinary optical exposure be the to make public production capacity of big lines is high, but because the wavelength restriction, fine pattern can't make public; And the advantage of electron beam exposure is and can fine pattern be made public; And electron beam exposure does not need mask, but the time of electron beam exposure is longer, and this can cause production capacity low.In the present invention, first figure 11 is defined in the interior figure of limit of power of ordinary optical exposure, also is the big bargraphs on the ordinary meaning; Second graph 12 is defined as the limit of power that has exceeded the ordinary optical exposure and the figure of needs employing electron beam exposure also is meticulous bargraphs.
Before Patternized technique carries out; According to the exposure ability of employing ordinary optical exposure sources, patterned layer is analyzed, split out first figure 11 in the ordinary optical exposure limit of power; And process corresponding reticle and make public in order to ordinary optical, referring to accompanying drawing 2.Simultaneously, will split remaining graphic file, also promptly exceed limit of power and the second graph 12 of needs employing electron beam exposure of ordinary optical exposure, in order to electron beam exposure, referring to accompanying drawing 3.
Next, with the polysilicon gate layer be patterned layer as an example, specifically describe the mixed exposure technology of ordinary optical exposure and electron beam exposure.Referring to accompanying drawing 4, substrate 1 is provided, and is positioned at grid oxic horizon 2 and polysilicon gate layer 3 on the substrate 1, and polysilicon gate layer 3 for to carry out the patterned layer of patterning.3 figure that will form of polysilicon gate layer are analyzed, extracted first figure 11 that the ordinary optical exposure can make public, and process corresponding reticle.Can adopt ordinary optical exposures such as I line 365nm exposure, DUV248nm exposure, non-immersion quasi-molecule laser source 193nm exposure, immersion quasi-molecule laser source 193nm exposure; And different according to the exposure ability of ordinary optical exposure sources, need the dimension of picture of extraction also different, for example; When adopting the DUV248nm exposure; First figure 11 is of a size of more than the 130nm, and when adopting immersion quasi-molecule laser source 193nm exposure, first figure 11 is of a size of more than the 20nm.Must be ready to the graphic file of the second graph 12 of electron beam exposure polysilicon gate layer 3 is remaining, in order to electron beam exposure.Because the lines of second graph 12 all are meticulous lines, for example less than 130nm (adopting the exposure of DUV248nm ordinary optical) or less than 20nm (adopting the exposure of immersion quasi-molecule laser source 193nm ordinary optical), at this moment, the ordinary optical exposure can't be satisfied.
On polysilicon gate layer 3, apply first photoresist 4, referring to accompanying drawing 5.First photoresist 4 is for being applicable to the photoresist of ordinary optical exposure.The employing ordinary optical makes public and corresponding to the reticle of first figure 11 first photoresist 4 is made public; Then through developing and solid adhesive process; With first photoresist, 4 patternings, like this, first photoresist 4 of patterning is corresponding to first figure 11; Also be first photoresist 4 of patterning only cover the top of first figure 11 that will form, referring to accompanying drawing 6.
Then, after first photoresist 4 that forms patterning, on polysilicon gate layer 3, apply second photoresist 5 again, referring to accompanying drawing 7.Second photoresist 5 is for being applicable to the photoresist of electron beam exposure.On electron beam exposure apparatus; Adopt electron beam exposure; Second photoresist 5 is made public, and then through developing and solid adhesive process, second photoresist 5 that makes patterning is corresponding to second graph 12; Also be second photoresist 5 of patterning only cover the top of the second graph 12 that will form, referring to accompanying drawing 8.
Then; With first photoresist 4 of patterning and second photoresist 5 of patterning is mask, and polysilicon gate layer 3 is carried out etching, forms first figure 11 and second graph 12 in the polysilicon gate layer 3; Referring to accompanying drawing 9, thereby accomplish Patternized technique for polysilicon gate layer 3.
In mixed exposure method provided by the present invention, electron beam exposure and ordinary optical exposure be the figure of a speciality of making own all, under the prerequisite that does not influence meticulous lines quality, significantly reduces the time for exposure.This method is applicable to the big bargraphs that both comprises ordinary optical exposure, and comprising again must be with all patterned layer of the meticulous bargraphs of electron beam exposure, and is not limited in the polysilicon gate layer of mentioning among the embodiment in the above.
Claims (7)
1. method, semi-conductor device manufacturing method comprises:
Substrate is provided, and is positioned at the patterned layer on the said substrate;
The mixed exposure method that adopts ordinary optical exposure and electron beam exposure to combine carries out patterning to said patterned layer, it is characterized in that:
The exposure limit of power of the exposure sources that exposure is adopted according to said ordinary optical; To said patterned layer the figure that will form analyze; Split out first figure and second graph; Wherein, said first figure is defined in the figure in the exposure limit of power of the exposure sources that the exposure of said ordinary optical adopts, and said second graph is defined as the exposure limit of power that exceeded the exposure sources that said ordinary optical exposure adopts and the figure of needs employing electron beam exposure;
On said patterned layer, apply first photoresist, adopt the ordinary optical exposure that said first photoresist is made public, through developing and solid adhesive process, with the said first photoresist patterning, said first photoresist of patterning is corresponding to said first figure;
On said patterned layer, apply second photoresist, adopt electron beam exposure that said second photoresist is made public, through developing and solid adhesive process, with the said second photoresist patterning, said second photoresist of patterning is corresponding to said second graph;
With first photoresist of patterning and second photoresist of patterning is mask, and said patterned layer is carried out etching, accomplishes the patterning to said patterned layer.
2. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said patterned layer is the patterned layer in the fabrication of semiconductor device, and said patterned layer comprises said first figure and said second graph simultaneously.
3. method, semi-conductor device manufacturing method as claimed in claim 2 is characterized in that, said patterned layer is a kind of in polysilicon gate layer, metal gate layers, the interconnection layer.
4. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said ordinary optical exposure is I line 365nm exposure, and the size of said first figure is greater than 350nm, and the size of said second graph is less than 350nm.
5. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said ordinary optical exposure is the DUV248nm exposure, and the size of said first figure is greater than 130nm, and the size of said second graph is less than 130nm.
6. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said ordinary optical exposure is non-immersion quasi-molecule laser source 193nm exposure, and the size of said first figure is greater than 65nm, and the size of said second graph is less than 65nm.
7. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said ordinary optical exposure is immersion quasi-molecule laser source 193nm exposure, and the size of said first figure is greater than 20nm, and the size of said second graph is less than 20nm.
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| CN201010620578.9A CN102543748B (en) | 2010-12-31 | 2010-12-31 | Manufacturing method of semi-conductor device |
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| CN201010620578.9A CN102543748B (en) | 2010-12-31 | 2010-12-31 | Manufacturing method of semi-conductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103676493A (en) * | 2012-09-21 | 2014-03-26 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392593A (en) * | 2001-06-14 | 2003-01-22 | 中国科学院微电子中心 | Mixed exposure method of combining contact exposure and direct electronic beam writing technology |
| CN1535915A (en) * | 2003-04-09 | 2004-10-13 | 中国科学院微电子中心 | Method for making nano device |
| CN1847983A (en) * | 2005-04-04 | 2006-10-18 | 中国科学院微电子研究所 | Prepn process of exposure registering mark for mixing and matching between electron beam and optical device |
| US20080157260A1 (en) * | 2007-01-02 | 2008-07-03 | David Michael Fried | High-z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
| CN101573779A (en) * | 2007-01-02 | 2009-11-04 | 国际商业机器公司 | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392593A (en) * | 2001-06-14 | 2003-01-22 | 中国科学院微电子中心 | Mixed exposure method of combining contact exposure and direct electronic beam writing technology |
| CN1535915A (en) * | 2003-04-09 | 2004-10-13 | 中国科学院微电子中心 | Method for making nano device |
| CN1847983A (en) * | 2005-04-04 | 2006-10-18 | 中国科学院微电子研究所 | Prepn process of exposure registering mark for mixing and matching between electron beam and optical device |
| US20080157260A1 (en) * | 2007-01-02 | 2008-07-03 | David Michael Fried | High-z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
| CN101573779A (en) * | 2007-01-02 | 2009-11-04 | 国际商业机器公司 | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
Non-Patent Citations (2)
| Title |
|---|
| 刘明 等: "电子束和接触式曝光机的混合曝光技术", 《微细加工技术》, no. 1, 31 March 2002 (2002-03-31) * |
| 陈宝钦 等: "光学和电子束曝光系统之间的匹配与混合光刻技术", 《半导体学报》, vol. 27, 31 December 2006 (2006-12-31) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103676493A (en) * | 2012-09-21 | 2014-03-26 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
| CN103676493B (en) * | 2012-09-21 | 2017-05-03 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
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| CN102543748B (en) | 2014-09-24 |
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Effective date of registration: 20201214 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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Effective date of registration: 20220525 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |
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