CN101441979A - Method for optimizing silicon chip etching condition - Google Patents
Method for optimizing silicon chip etching condition Download PDFInfo
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- CN101441979A CN101441979A CNA2007100942489A CN200710094248A CN101441979A CN 101441979 A CN101441979 A CN 101441979A CN A2007100942489 A CNA2007100942489 A CN A2007100942489A CN 200710094248 A CN200710094248 A CN 200710094248A CN 101441979 A CN101441979 A CN 101441979A
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Abstract
The invention discloses a method for optimizing silicon chip etching condition, wherein observing of lengthwise topography of etching condition on the cut surface of the silicon chip comprises the following steps: gelatinizing the silicon chip; choosing any region for exposal; etching the exposed part; removing optical resist of the whole silicon chip; gelatinizing the same silicon chip; choosing any unexposed region of the silicon chip for exposal; etching the region exposed in the last step; removing the optical resist of the whole silicon chip; repeatedly gelatinizing the whole silicon chip, choosing any unexposed region for exposal, etching the region on the condition of etching needing to be observed, removing the optical resist of the whole silicon chip until the etching condition needing to be observed is completed; and slicing the silicon chip and observing the lengthwise topography of different etching conditions in the different zones of the silicon chip. The method can greatly save budget of the silicon chip and reduce the cost.
Description
Technical field
The present invention relates to the method for exploitation etching technique in the semiconductor device, relate in particular to the optimization method of silicon chip etching condition.
Background technology
In the technical field of semiconductors, etching technique is by frequent application.Because etching condition has very big influence to the etching precision, therefore often need be optimized etching condition.In the process of optimizing silicon chip etching condition, silicon chip is carried out gluing, exposure, etching, the section then of removing photoresist is observed etched vertical pattern and is widely used under electron microscope or high-resolution transmission electron microscope.These sections can cause the fragmentation of silicon chip, can not reuse.
Method for optimizing silicon chip etching condition in the prior art may further comprise the steps: the first step, gluing on whole silicon wafer; In second step, whole silicon wafer is exposed; In the 3rd step, remove photoresist; At last, sections observation is carried out in the exposure area.Existing common way is the process of only carrying out gluing on a slice silicon chip, exposing, removing photoresist and cutting into slices, thereby can only observe an etching condition on a slice silicon chip.Need utilize a plurality of silicon chips when a plurality of etching conditions are adjusted, the method for optimizing silicon chip etching condition of prior art can cause the loss of a large amount of silicon chips, has increased the technology cost, so under the budget condition of limited, limited the exploitation of etching condition.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method for optimizing silicon chip etching condition, realizes observing on a slice silicon chip the cross-section morphology of a plurality of etching conditions, thereby reduces the consumption of silicon chip in the etching condition optimizing process.
For solving the problems of the technologies described above, the technical scheme of method for optimizing silicon chip etching condition of the present invention is wherein to observe the vertical pattern of etching condition and may further comprise the steps on the silicon chip section: the first step, gluing on whole silicon wafer; In second step, selected arbitrary region exposes on above-mentioned silicon chip; In the 3rd step, the etching condition of observing with needs at exposed areas in second step 1 carries out etching; In the 4th step, remove the photoresist on the whole silicon wafer; The 5th step, gluing on same silicon chip; In the 6th step, the zone that was not exposed on above-mentioned silicon chip selects arbitrary region to expose; In the 7th step, the etching condition of observing with needs at exposed areas in the 6th step 2 carries out etching; In the 8th step, remove the photoresist on the whole silicon wafer; In the 9th step, repeated for the 5th step to the 8th step, gluing on whole silicon wafer, select arbitrarily the zone to expose in the zone that is not exposed, and the etching condition of observing with needs in this exposure area carries out etching, removes the photoresist on the whole silicon wafer, needs the etching condition observed until finishing; The tenth step, silicon chip is cut into slices, observe vertical pattern of different etching conditions in the zones of different of silicon chip.
Further improvement as method for optimizing silicon chip etching condition of the present invention is may further comprise the steps: the first step, gluing on whole silicon wafer; In second step, select above-mentioned silicon chip two exposing units middle and edge to expose; In the 3rd step, the etching condition of observing with needs at exposed areas in second step 1 carries out etching; In the 4th step, remove the photoresist on the whole silicon wafer; The 5th step, gluing on same silicon chip; In the 6th step, the zone that was not exposed on silicon chip selects two exposing units at middle and edge to expose; In the 7th step, the etching condition of observing with needs at exposed areas in the 6th step 2 carries out etching; In the 8th step, remove the photoresist on the whole silicon wafer; In the 9th step, repeated for the 5th step to the 8th step, gluing on whole silicon wafer, select arbitrarily the zone to expose in the zone that is not exposed, and the etching condition of observing with needs in this exposure area carries out etching, removes the photoresist on the whole silicon wafer, needs the etching condition observed until finishing; The tenth step, silicon chip is cut into slices, observe vertical pattern of different etching conditions in the zones of different of silicon chip.
Method for optimizing silicon chip etching condition of the present invention, by the different zone of definition on a slice silicon chip, carry out the repetition gluing, silicon chip to zones of different exposes respectively, etching and glue are peeled off, pattern at the corresponding etching condition of zones of different of exposure definition each time, remove photoresist at all etching conditions at last and finish to take out section more later, reach the purpose of on a slice silicon chip, seeing a plurality of etching condition cross-section morphologies.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 to Fig. 3 is the schematic diagram of the embodiment of the invention 1;
Fig. 4 to Fig. 6 is the schematic diagram of the embodiment of the invention 2;
Fig. 7 is a schematic flow sheet of the present invention.
Embodiment
At the embodiment 1 of method for optimizing silicon chip etching condition of the present invention, on the silicon chip section, observe in the step of the vertical pattern of etching condition, when carrying out the optimization of via etch condition, three condition needs assessments are arranged.To on a slice silicon chip, get the etching pattern of all three etching conditions.In conjunction with shown in Figure 7, at first, gluing on whole silicon wafer as shown in Figure 1, is selected regional Q to expose, and regional Q is carried out etching with condition one, removes the photoresist on the silicon chip, and this moment, the regional Q on silicon chip stayed the etched figure of etching condition one.Then again to the silicon chip gluing, as shown in Figure 2, select the regional P that does not repeat mutually with regional Q to expose, and regional P carried out etching with condition two, remove the photoresist on the silicon chip, this moment, the regional P on silicon chip stayed the etched figure of etching condition two, and regional Q stays the etched figure of etching condition one.As shown in Figure 3, the region R of selecting not repeat mutually with regional Q and regional P is exposed, and region R carried out etching with condition three, remove the photoresist on the silicon chip, this moment, the region R on silicon chip stayed the etched figure of etching condition three, zone Q stays the etched figure of etching condition one, and regional P stays the etched figure of etching condition two.Silicon chip is taken out section, obtain the pattern that the pattern of etching condition one, pattern that the P zone obtains etching condition two and Zone R territory obtain etching condition three respectively in the Q zone.Thereby when doing the optimization of through hole etching condition, realized on a silicon chip, obtaining three etching condition patterns, saved the silicon chip budget.
In conjunction with shown in Figure 7, embodiment 2 at method for optimizing silicon chip etching condition of the present invention, on the silicon chip section, observing in the step of the vertical pattern of etching condition therein, at first, gluing on whole silicon wafer as shown in Figure 4, selects two exposing unit A at middle and edge to expose on silicon chip, two exposing unit A with a pair of this centre of etching condition and edge carry out etching, remove photoresist then.This moment, the a-quadrant on silicon chip stayed the etching figure of etching condition one.Then silicon chip is carried out gluing, as shown in Figure 5, two exposing unit B exposures in the middle of on silicon chip, selecting and edge; two couples of these two exposing unit B carry out etching with etching condition; at this moment, a-quadrant and other zones are protected by photoresist, and etching condition two can not influence the pattern of etching condition one.Remove photoresist after the etching, this moment, the a-quadrant on silicon chip stayed the etching figure of etching condition one, stayed the etching figure of etching condition two in the B zone.Silicon chip is carried out gluing, as shown in Figure 6, two exposing unit C exposures in the middle of on silicon chip, selecting and edge; three couples of exposing unit C carry out etching with etching condition, at this moment, and A; B zone and other zones are protected by photoresist, and etching condition three can not influence the pattern of etching condition one and condition two.Etching is removed photoresist after finishing, and last a-quadrant on silicon chip stays the etching figure of etching condition one, stays the etching figure of etching condition two in the B zone, stays the etching figure of etching condition three in the C zone.At last silicon chip is taken out section, obtain the pattern of etching condition one in two zones of A, obtain the pattern of etching condition two in two zones of B, obtain the zone of etching condition three in two zones of C, thereby on same silicon chip, obtain etching pattern three etching conditions.
Method for optimizing silicon chip etching condition of the present invention is not only applicable to the medium holes etching, also is applicable to the etching polysilicon of low percent of pass and the metal etch of low percent of pass.And when zones of different is exposed, can adopt same light shield to expose, also can expose with different light shields.According to the demand of technology, the present invention can carry out on the silicon chip of various sizes such as 6 cun, 8 cun, 12 cun.And can on same silicon chip, repeat gluing of the present invention, to selection area exposure, with the special etch condition to the selection area etching, the technology of removing photoresist at last is up to using up a slice silicon chip.
By said method, method for optimizing silicon chip etching condition of the present invention can obtain the etch profile of a large amount of etching conditions on a slice silicon chip, thereby can save the silicon chip budget in a large number, reduces cost.
Claims (9)
1. a method for optimizing silicon chip etching condition is included in the step of observing the vertical pattern of etching condition on the silicon chip section, it is characterized in that, observes the vertical pattern of etching condition and may further comprise the steps on the silicon chip section: the first step, gluing on whole silicon wafer; In second step, selected arbitrary region exposes on above-mentioned silicon chip; In the 3rd step, the etching condition of observing with needs at exposed areas in second step 1 carries out etching; In the 4th step, remove the photoresist on the whole silicon wafer; The 5th step, gluing on same silicon chip; In the 6th step, the zone that was not exposed on above-mentioned silicon chip selects arbitrary region to expose; In the 7th step, the etching condition of observing with needs at exposed areas in the 6th step 2 carries out etching; In the 8th step, remove the photoresist on the whole silicon wafer; In the 9th step, repeated for the 5th step to the 8th step, gluing on whole silicon wafer, select arbitrarily the zone to expose in the zone that is not exposed, and the etching condition of observing with needs in this exposure area carries out etching, removes the photoresist on the whole silicon wafer, needs the etching condition observed until finishing; The tenth step, silicon chip is cut into slices, observe vertical pattern of different etching conditions in the zones of different of silicon chip.
2. method for optimizing silicon chip etching condition according to claim 1, it is characterized in that, second step selection silicon chip, two exposing units middle and edge expose, and the 6th step was selected two exposing units at middle and edge for the zone that was not exposed and exposes on silicon chip.
3. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, etching condition is the medium holes etching.
4. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, etching condition is the etching polysilicon of low percent of pass.
5. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, etching condition is the metal etch of low percent of pass.
6. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, adopts same light shield to expose in second step and the 6th step.
7. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, adopts the same area of same light shield to expose in second step and the 6th step.
8. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, adopts the zones of different of same light shield to expose in second step and the 6th step
9. method for optimizing silicon chip etching condition according to claim 1 and 2 is characterized in that, second the step and the 6th the step in the employing different light shields expose.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710094248A CN100576437C (en) | 2007-11-19 | 2007-11-19 | method for optimizing silicon chip etching condition |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710094248A CN100576437C (en) | 2007-11-19 | 2007-11-19 | method for optimizing silicon chip etching condition |
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| CN101441979A true CN101441979A (en) | 2009-05-27 |
| CN100576437C CN100576437C (en) | 2009-12-30 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479670A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and using method |
| CN103676493A (en) * | 2012-09-21 | 2014-03-26 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
| CN103855075A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for collecting etching conditions |
-
2007
- 2007-11-19 CN CN200710094248A patent/CN100576437C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479670A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and using method |
| CN102479670B (en) * | 2010-11-30 | 2015-11-25 | 中芯国际集成电路制造(北京)有限公司 | A kind of semiconductor device and using method |
| CN103676493A (en) * | 2012-09-21 | 2014-03-26 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
| CN103676493B (en) * | 2012-09-21 | 2017-05-03 | 中国科学院微电子研究所 | Mixed photolithography method capable of reducing line roughness |
| CN103855075A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method for collecting etching conditions |
| CN103855075B (en) * | 2012-12-04 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | The acquisition method of etching condition |
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| Publication number | Publication date |
|---|---|
| CN100576437C (en) | 2009-12-30 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |