CN102445834A - Optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension - Google Patents
Optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension Download PDFInfo
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- CN102445834A CN102445834A CN2011102727587A CN201110272758A CN102445834A CN 102445834 A CN102445834 A CN 102445834A CN 2011102727587 A CN2011102727587 A CN 2011102727587A CN 201110272758 A CN201110272758 A CN 201110272758A CN 102445834 A CN102445834 A CN 102445834A
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Abstract
The invention relates to the semiconductor manufacturing field, in particular to an optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension. The invention discloses an optical modeling proximity correction method of SRAM grid dimension, comprising a step of establishing an optical grid proximity effect model with substrate information through test reticle mask design and model data acquisition, thereby achieving the purpose of predicting spacing distances among grid line terminals precisly and ensuring a craft window big enough for a photoetching process of the grid.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the optical modeling that relates in particular to a kind of SRAM grid size closes on modification method.
Background technology
In the preparation process of semiconductor devices, along with developing rapidly of VLSI (very large scale integrated circuits), when the integrated level of chip was increasingly high, chip size was also more and more little.In the photoetching process, exposure figure is also constantly diminishing, and especially gets into after the 65nm technology, and is strict more to the control requirement of grid size, and photoetching process and optical approach correction are had higher requirement.The nuance of optical effect can have influence on the performance of the process window and the device of photoetching.
In advanced optical carving technology now; Because of dwindling of exposure figure size; Must carry out optical approach correction (Optical Proximity Correction, be called for short OPC) in advance to photomask pattern, be used for remedying the optical approach effect that the finite resolving power by optical system causes; And gate patterns is because its characteristic dimension in whole process flow is minimum, is the difficult problem of tool challenge in the optical approach effect correction always.So in existing OPC modification method to SRAM (Static Random Access Memory, be called for short SRAM) grid size, the modeling data of sample collection generally is based on the substrate of single planarization.And actual process for different SRAM grid structures, has different substrates, corresponding can the generation because model is forbidden the trickle round-off error that causes.In advanced optical carving technology now, because the nuance of optical effect, can reduce the performance of the process window and the device of photoetching.
Summary of the invention
The optical modeling that the invention discloses a kind of SRAM grid size closes on modification method, comprises a test wafer, wherein, may further comprise the steps:
Step S1: prepare first and second light shield, utilize first light shield on test wafer, to prepare active area, afterwards, be surrounded with the source region and prepare shallow channel isolation area at test wafer;
Step S2: utilize second light shield on active area and shallow channel isolation area, to prepare grid;
Step S3: carry out the data aggregation of optical approach correction model critical size, and utilize these data to set up the optical approach correction model.
The optical modeling of above-mentioned SRAM grid size closes on modification method, wherein, according to the live width size of process requirements design, spacing dimension, pitch, the size of line end spacing dimension and active area designs the figure of first and second light shield.
The optical modeling of above-mentioned SRAM grid size closes on modification method, and wherein, critical size includes intensive linear dimension, isolated line size, isolated spacing dimension, intensive spacing dimension, intensive line end spacing dimension and isolated line end spacing dimension etc.
The optical modeling of above-mentioned SRAM grid size closes on modification method; Wherein, the optical approach correction model includes the intensive linear dimension test structure that is positioned on the active area, is positioned at isolated line size measuring structure on the active area, is positioned at isolated spacing dimension test structure on the shallow channel isolation area, is positioned at staggered active area and the intensive spacing dimension test structure on the shallow channel isolation area that occurs, is positioned at the intensive line end spacing dimension test structure on the shallow channel isolation area and is positioned at isolated line end spacing dimension test structure on the shallow channel isolation area etc.
In sum; Owing to adopted technique scheme; The optical modeling that the present invention proposes a kind of SRAM grid size closes on modification method, through the design of test light shield and the collection of model data, sets up the grid optical approach effect model that includes substrate information; Thereby reach the purpose of accurate prediction grid line end spacing dimension, can obtain enough big process window with the photoetching process that guarantees grid.
Description of drawings
Fig. 1 is the intensive linear dimension test structure design layout that is positioned on the active area;
Fig. 2 is the isolated line size measuring structural design domain that is positioned on the active area;
Fig. 3 is the isolated spacing dimension test structure design layout that is positioned on the shallow channel isolation area;
Fig. 4 is positioned at staggered active area that occurs and the intensive spacing dimension test structure design layout on the shallow channel isolation area;
Fig. 5 is the isolated line end spacing dimension test structure design layout that is positioned on the shallow channel isolation area.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Shown in Fig. 1-5, the optical modeling of SRAM grid size of the present invention closes on modification method, at first; Prepare a test wafer, and according to the live width size of process requirements design, spacing dimension; Pitch, the size of line end spacing dimension and active area etc. is designed the figure of active area light shield and grid light shield; Secondly, on test wafer, utilize the active area light shield on test wafer, to carry out active area preparation technology, to be formed with source region 12; Afterwards; Continue shallow trench processes; After formation is surrounded with the shallow channel isolation area 11 in source region 12; Carry out grid technology, utilize the grid light shield to form respectively to be positioned at intensive linear dimension test structure design layout 13 (as shown in Figure 1) on the active area during to photoetching process, be positioned at isolated line size measuring structural design domain 23 (as shown in Figure 2) on the active area, be positioned at isolated spacing dimension test structure design layout 33 (as shown in Figure 3) on the shallow channel isolation area, be positioned at staggered active area and the intensive spacing dimension test structure design layout 43 (as shown in Figure 4) on the shallow channel isolation area that occurs and be positioned at isolated line end spacing dimension test structure design layout 53 (as shown in Figure 5) on the shallow channel isolation area; At last; Carry out the data aggregation of optical approach correction model critical size such as intensive linear dimension, isolated line size, isolated spacing dimension, intensive spacing dimension, intensive line end spacing dimension and isolated line end spacing dimension etc., the data in the above-mentioned domain are collected the back and utilized this data foundation to be positioned at the intensive linear dimension optical approach correction model on the active area.
In sum; Owing to adopted technique scheme; The optical modeling that the present invention proposes a kind of SRAM grid size closes on modification method, through the design of test light shield and the collection of model data, sets up the grid optical approach effect model that includes substrate information; Thereby reach the purpose of accurate prediction grid line end spacing dimension, can obtain enough big process window with the photoetching process that guarantees grid.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (4)
1. the optical modeling of a SRAM grid size closes on modification method, comprises a test wafer, it is characterized in that, may further comprise the steps:
Step S1: utilize first light shield on test wafer, to prepare active area, afterwards, be surrounded with the source region and prepare shallow channel isolation area at test wafer;
Step S2: utilize second light shield on active area and shallow channel isolation area, to prepare grid;
Step S3: carry out the data aggregation of optical approach correction model critical size, and utilize these data to set up the optical approach correction model.
2. the optical modeling of SRAM grid size according to claim 1 closes on modification method; It is characterized in that, according to the live width size of process requirements design, spacing dimension; Pitch, the size of line end spacing dimension and active area designs the figure of first and second light shield.
3. the optical modeling of SRAM grid size according to claim 1 closes on modification method; It is characterized in that critical size includes intensive linear dimension, isolated line size, isolated spacing dimension, intensive spacing dimension, intensive line end spacing dimension and isolated line end spacing dimension.
4. the optical modeling of SRAM grid size according to claim 1 closes on modification method; It is characterized in that the optical approach correction model includes the intensive linear dimension test structure that is positioned on the active area, be positioned at isolated line size measuring structure on the active area, be positioned at isolated spacing dimension test structure on the shallow channel isolation area, be positioned at staggered active area and the intensive spacing dimension test structure on the shallow channel isolation area that occurs, be positioned at the intensive line end spacing dimension test structure on the shallow channel isolation area and be positioned at the isolated line end spacing dimension test structure on the shallow channel isolation area.
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| CN2011102727587A CN102445834A (en) | 2011-09-15 | 2011-09-15 | Optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension |
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| CN2011102727587A CN102445834A (en) | 2011-09-15 | 2011-09-15 | Optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716068A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Optical proximity correction examination method capable of avoiding false error |
| CN112946994A (en) * | 2019-12-10 | 2021-06-11 | 中芯国际集成电路制造(北京)有限公司 | Optical proximity correction method and manufacturing method of mask |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1450411A (en) * | 2002-03-25 | 2003-10-22 | Asml蒙片工具有限公司 | Method and apparatus for porforming rule-based gate shrink utilizing dipole illumination |
| CN1926672A (en) * | 2004-02-07 | 2007-03-07 | 三星电子株式会社 | Multi-gate transistor formed with active patterns of uniform critical dimension and its making method |
| CN101127354A (en) * | 2006-08-18 | 2008-02-20 | 台湾积体电路制造股份有限公司 | Integrated circuit and mask set for forming integrated circuit |
| CN101192539A (en) * | 2006-11-28 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Device manufacture method and device electrical performance regulation method |
| CN102117012A (en) * | 2009-12-30 | 2011-07-06 | 上海微电子装备有限公司 | Method for increasing focal depth in lithography process |
-
2011
- 2011-09-15 CN CN2011102727587A patent/CN102445834A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1450411A (en) * | 2002-03-25 | 2003-10-22 | Asml蒙片工具有限公司 | Method and apparatus for porforming rule-based gate shrink utilizing dipole illumination |
| CN1926672A (en) * | 2004-02-07 | 2007-03-07 | 三星电子株式会社 | Multi-gate transistor formed with active patterns of uniform critical dimension and its making method |
| CN101127354A (en) * | 2006-08-18 | 2008-02-20 | 台湾积体电路制造股份有限公司 | Integrated circuit and mask set for forming integrated circuit |
| CN101192539A (en) * | 2006-11-28 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Device manufacture method and device electrical performance regulation method |
| CN102117012A (en) * | 2009-12-30 | 2011-07-06 | 上海微电子装备有限公司 | Method for increasing focal depth in lithography process |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716068A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Optical proximity correction examination method capable of avoiding false error |
| CN104716068B (en) * | 2015-03-20 | 2017-07-11 | 上海华力微电子有限公司 | The optics of false error is avoided to close on amendment inspection method |
| CN112946994A (en) * | 2019-12-10 | 2021-06-11 | 中芯国际集成电路制造(北京)有限公司 | Optical proximity correction method and manufacturing method of mask |
| CN112946994B (en) * | 2019-12-10 | 2022-12-16 | 中芯国际集成电路制造(北京)有限公司 | Optical proximity correction method and manufacturing method of mask |
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Application publication date: 20120509 |