CN103676491B - The method of photoresist roughness when reducing beamwriter lithography - Google Patents
The method of photoresist roughness when reducing beamwriter lithography Download PDFInfo
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- CN103676491B CN103676491B CN201210353546.6A CN201210353546A CN103676491B CN 103676491 B CN103676491 B CN 103676491B CN 201210353546 A CN201210353546 A CN 201210353546A CN 103676491 B CN103676491 B CN 103676491B
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Abstract
The invention discloses a kind of method of photoresist roughness when reducing beamwriter lithography, including: on substrate, form structural material and the first hard mask layer；First hard mask layer is formed the second hard mask layer；Form beamwriter lithography glue pattern on the second hardmask layer；With beamwriter lithography glue pattern as mask, etch the second hard mask layer and form the second hard mask figure；With the second hard mask figure as mask, etch the first hard mask layer and form the first hard mask figure；With the first and second hard mask figures as mask, etching structure material layer, the lines required for formation.Method according to the present invention, use multilamellar hard mask layer and multiple etching that material is different, it is therefore prevented that electron beam resist sidewall roughness is delivered to the structural material of lower floor, effectively reduces the roughness of lines, improve the stability of technique, reduce the fluctuation change of device performance.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, reduce the beamwriter lithography time more particularly, to one
The method of photoresist roughness.
Background technology
Along with super large-scale integration characteristic size is gradually reduced, in the manufacture method of semiconductor device, enter
After 22nm technology generation, the technological limit of common optical exposure has arrived.At present, after 45nm process node, generally adopt
The double lithographic technique of double-exposure is combined to prepare less lines by i193nm immersion lithography technology.Fine with lower node of 22nm
Figure typically requires employing electron beam or EUV is exposed and photoetching.
About EUV lithography technology, at present also in development, some key technologies are still had to need to capture and improve, also
Large scale integrated circuit cannot be applied to and manufacture central.By contrast, electron beam lithography, through development for many years, compares into
Ripe, and electron beam exposure has the highest precision, and resolution can reach several nanometer, writes out the lines of hyperfine figure
Come, but inefficient, thus the contradiction of scanning accuracy and scan efficiency becomes the principal contradiction of beamwriter lithography.
On the other hand, after entering 32nm node technique, line roughness becomes the key issue that must take into, and specifically wraps
Include line edge roughness (LER) and line thickness roughness (LWR).For EUV or electron beam technology, all can run into
The problem of line roughness.Especially, when using electron beam lithography, the requirement to photoresist (resist) is higher, often
Contradiction is there is between lines resolution and photoresist thickness.The thinnest photoresist more can expose the least lines, but, this
The thin photoresist of sample, due to the not high enough selectivity of etching technics, often can lose in etching process early, and then cannot
Prepare required lines, and there is serious line roughness problem.
Summary of the invention
In view of this, outside it is an object of the invention to independent of photoresist, in conjunction with a kind of new hard mask technology so that
Line roughness is substantially reduced so that technique is more stable, and the change of threshold voltage is also minimized.
Realize the above-mentioned purpose of the present invention, the side of photoresist roughness when being to reduce beamwriter lithography by offer is a kind of
Method, including: on substrate, form structural material and the first hard mask layer；First hard mask layer is formed the second hard mask
Layer；Form beamwriter lithography glue pattern on the second hardmask layer；With beamwriter lithography glue pattern as mask, etching second is covered firmly
Mold layer forms the second hard mask figure；With the second hard mask figure as mask, etch the first hard mask layer and form the first hard mask
Figure；With the first and second hard mask figures as mask, etching structure material layer, the lines required for formation.
Wherein, the first hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride and combinations thereof.
Wherein, the first hard mask layer is the laminated construction of silicon oxide and silicon nitride.
Wherein, the second hard mask layer includes polysilicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium, SiC, SiGe, eka-gold
Hard rock amorphous carbon and combinations thereof.
Wherein, the etching using plasma of the first hard mask layer and/or the second hard mask layer and/or structural material is done
Method lithographic technique.
Wherein, plasma dry etch uses CCP or ICP or TCP equipment.
Wherein, also include after etching that dry method is removed photoresist and/or wet etching cleans.
Wherein, wet etching cleans and uses SPM+APM.
Wherein, the one during structural material is false gate electrode layer, metal gate electrode layer, local interlinkage layer.
Wherein, the first and/or second hard mask layer uses LPCVD, PECVD, HDPCVD, MBE, ALD method to prepare.
According to the method for the present invention, use multilamellar hard mask layer and multiple etching that material is different, it is therefore prevented that electron beam
Photoresist sidewall roughness is delivered to the structural material of lower floor, effectively reduces the roughness of lines, improves the steady of technique
Qualitative, reduce the fluctuation change of device performance.
Accompanying drawing explanation
Describe technical scheme referring to the drawings in detail, wherein:
Fig. 1 is the schematic diagram of beamwriter lithography domain；
Fig. 2 to Fig. 5 is the section of each step of method of photoresist roughness when reducing beamwriter lithography according to the present invention
Schematic diagram；And
Fig. 6 is the flow chart of the method for photoresist roughness when reducing beamwriter lithography according to the present invention.
Detailed description of the invention
Referring to the drawings and combine schematic embodiment to describe feature and the skill thereof of technical solution of the present invention in detail
Art effect.It is pointed out that similar reference represents similar structure, term " first " use herein, "
Two ", " on ", D score, " thick ", " thin " etc. can be used for modifying various device architecture.These modifications are the darkest
Show the space of modified device architecture, order or hierarchical relationship.
With reference to accompanying drawing 1, for the schematic top plan view of little live width figure prepared by employing electron beam technology.Wherein, it is illustrated that in
Multiple parallel rectangle lines represent the figure needing to use electron beam exposure, can prepare dimension of picture and save less than below 22nm
The lines of point.The lines of the various structural material such as lines e.g. false grid layer, metal gate layers, local interlinkage layer.Below
Fig. 2 to Fig. 5 will illustrate as a example by grid manufacture.
With reference to Fig. 2, it is provided that substrate 1, sequentially form structural material 2/3 and the first hard mask layer 4A on substrate 1,
And on the first hard mask layer 4A, form the second hard mask layer 4B.Substrate 1 needs according to device application and rationally selects, it may include
Monocrystalline silicon (Si), SOI, monocrystal germanium (Ge), GeOI, strained silicon (Strained Si), germanium silicon (SiGe), or compound
Semi-conducting material, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon back are partly led
Body such as Graphene, SiC, carbon nanotube etc..For the consideration compatible with CMOS technology, substrate 1 be preferably body Si or
SSOI.As a example by making grid lines, structural material includes gate insulator 2 and grid conducting layer 3.Lead on substrate 1
Crossing the method formation of deposits gate insulators 2 such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, MBE, ALD, its material is permissible
Silicon oxide, silicon oxynitride, high-g value, wherein high-g value include but not limited to hafnio oxide (such as HfO2, HfSiON,
HfLaON), metal-oxide (predominantly subgroup and lanthanide element oxide, such as Al2O3、Ta2O5、TiO2、ZnO、
ZrO2、CeO2、Y2O3、La2O3), Perovskite Phase oxide (such as PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST)).At grid
On pole insulating barrier 2 by PECVD, HDPCVD, MOCVD, MBE, ALD, evaporate, the deposition process such as sputtering forms grid conducting layer 3.
In front grid technique, grid conducting layer 3 is DOPOS doped polycrystalline silicon, metal and nitride thereof, wherein said metal include Al, Cu, Ti,
Ta, W, Mo and combinations thereof.In rear grid technique, grid conducting layer 3 can be false grid, including polysilicon, non-crystalline silicon, crystallite
Silicon, amorphous carbon, amorphous germanium etc. and combinations thereof.By the method such as LPCVD, PECVD, HDPCVD deposition the on grid conducting layer 3
One hard mask layer 4A, its can be monolayer can also be the stepped construction of multilamellar, its material can include silicon oxide, silicon nitride,
Silicon oxynitride and combinations thereof.In an embodiment of the invention, hard mask layer 4A is the multiple structure of ONO, namely includes oxidation
The top layer (not showing the hierarchy of this ONO in figure) of the bottom of silicon, the middle level of silicon nitride and silicon oxide.By LPCVD,
PECVD, HDPCVD, MBE, ALD, evaporate, the common process such as sputtering, the first hard mask layer 4A of insulant deposits material
The second different hard mask layer 4B.Layer the material e.g. polysilicon of 4B, non-crystalline silicon, microcrystal silicon, amorphous carbon, amorphous germanium, SiC,
SiGe, diamond like carbon amorphous carbon (DLC) etc. and combinations thereof.Alternatively, layer 4B and the material of the grid conducting layer 3 as false grid
Matter is identical, such as, be non-crystalline silicon.
With reference to Fig. 3, hard mask 4A/4B coats photoresist 5, for being adapted to the photoresist of direct electronic beam writing technology, example
Such as PMMA, epoxy 618, COP etc..Employing direct electronic beam writing technology is exposed, and developing in the developer solutions such as isopropyl acetone draws
Such as at 22nm node or following hyperfine figure, namely the photoetching offset plate figure 5P shown in figure.In the process, due to electricity
Son bundle direct writing technology and the characteristic (such as kindred effect etc.) of photoresist self, the side of figure 5P may collimate not, line
Bar edge roughness (LER) and line thickness roughness (LWR) are bigger, it is therefore desirable to hard mask layer 4A particularly layer 4B modifies
Adjust.
With reference to Fig. 4, with photoetching offset plate figure 5P as mask, use anisotropic etching technology etch hard mask layer 4A/4B, shape
Become hard mask figure 4P.Specifically, the dry etching technology such as using plasma etching, reactive ion etching (RIE), first etch
The second hard mask layer 44B on upper strata, stops on the first hard mask layer 4A, forms second hard mask with slightly steeper straight pattern
Figure (the top 4PB of 4P in figure).Etching gas can be carbon fluorine base gas, and also can include noble gas and oxidation
Property gas is to regulate etch rate.Wherein, dry etching equipment can be ICP, TCP, CCP equipment.Then with the second hard mask
Figure is mask, the above-mentioned dry etching technology of same employing, etches the first hard mask layer 4A, stops at structural material (concrete
For grid conducting layer 3) on, form more steep the first hard mask figure (the bottom 4PA of 4P in figure).Due to the second hard mask layer
Existence so that first obtain the most steep figure during dry etching, then proceed to deep etching and form more steep figure, by
This can be avoided photoetching offset plate figure sidewall roughness to be transferred down to structural material 2/3, effectively reduces the roughness of lines
(LER and LWR).Advantageously, then, dry etching and/or wet corrosion technique is used to remove the polymerization produced in etching process
Thing and granule thereof, dry etching etches for example with fluorine-based plasma, wet etching such as SPM (such as sulphuric acid: hydrogen peroxide=
4: 1)/APM (such as ammonia: hydrogen peroxide: deionized water=1: 1: 5 or 0.5: 1: 5) wet-cleaning.
With reference to Fig. 5, with hard mask figure 4P as mask, etching structure material layer, form final lines.For example with respectively
Heterotropic dry etching technology, such as plasma etching, RIE etc., etching grid conductive layer 3 until exposing gate insulator 2,
Define steep gate electrode pattern 3P.Afterwards, above-mentioned wet corrosion technique is used to remove the polymer formed in etching process.
One embodiment of the present of invention is illustrated above as a example by etching grid lines, but the method for the actually present invention
Can apply to various semiconductor structure, layer 2 and 3 can be any structural material, such as false grid stacked structure, locally
Interconnection structure, top welding pad structure etc..
According to the method for the present invention, use multilamellar hard mask layer and multiple etching that material is different, it is therefore prevented that electron beam
Photoresist sidewall roughness is delivered to the structural material of lower floor, effectively reduces the roughness of lines, improves the steady of technique
Qualitative, reduce the fluctuation change of device performance.
Although with reference to one or more exemplary embodiments illustrate the present invention, those skilled in the art could be aware that without
Depart from the scope of the invention and the method forming device architecture is made various suitable change and equivalents.Additionally, it is public by institute
The teaching opened can make many can be adapted to the amendment of particular condition or material without deviating from the scope of the invention.Therefore, the present invention
Be not intended to be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and manufacture method will include all embodiments fallen within the scope of the present invention.
Claims (9)
1. a method for photoresist roughness when reducing beamwriter lithography, including:
Substrate is formed structural material and the first hard mask layer；
Forming the second hard mask layer on the first hard mask layer, the second hard mask layer includes polysilicon, non-crystalline silicon, microcrystal silicon, non-
Brilliant carbon, amorphous germanium, SiC, S iGe, diamond like carbon amorphous carbon and combinations thereof；
Form beamwriter lithography glue pattern on the second hardmask layer；
With beamwriter lithography glue pattern as mask, etch the second hard mask layer and form the second hard mask figure；
With the second hard mask figure as mask, etch the first hard mask layer and form the first hard mask figure；
With the first and second hard mask figures as mask, etching structure material layer, the lines required for formation.
The most the method for claim 1, wherein the first hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride and group thereof
Close.
3. method as claimed in claim 2, wherein, the first hard mask layer is the laminated construction of silicon oxide and silicon nitride.
The most the method for claim 1, wherein the first hard mask layer and/or the second hard mask layer and/or structural material
Etching using plasma dry etching technology.
5. method as claimed in claim 4, wherein, plasma dry etch uses CCP or ICP or TCP equipment.
6. method as claimed in claim 4, wherein, also includes after etching that dry method is removed photoresist and/or wet etching cleans.
7. method as claimed in claim 6, wherein, wet etching cleans and uses SPM+APM.
The most the method for claim 1, wherein structural material is false gate electrode layer, metal gate electrode layer, local interlinkage
One in Ceng.
The most the method for claim 1, wherein first and/or second hard mask layer use LPCVD, PECVD, HDPCVD,
Prepared by MBE, ALD method.
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| CN201210353546.6A CN103676491B (en) | 2012-09-20 | 2012-09-20 | The method of photoresist roughness when reducing beamwriter lithography |
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| CN105428317B (en) * | 2014-09-12 | 2018-09-18 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN106558485A (en) * | 2015-09-28 | 2017-04-05 | 中国科学院微电子研究所 | A kind of dielectric nanostructures preparation method compatible with CMOS technology |
| CN106553993A (en) * | 2015-09-28 | 2017-04-05 | 中国科学院微电子研究所 | The nanostructured preparation method compatible with CMOS technology |
| CN114815059A (en) * | 2022-03-08 | 2022-07-29 | 嘉兴微智光子科技有限公司 | Preparation method of film photonic chip with smooth and steep side wall |
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| US6696222B2 (en) * | 2001-07-24 | 2004-02-24 | Silicon Integrated Systems Corp. | Dual damascene process using metal hard mask |
| JP2004079901A (en) * | 2002-08-21 | 2004-03-11 | Nec Electronics Corp | Semiconductor device and method for manufacturing the same |
| KR100640657B1 (en) * | 2005-07-25 | 2006-11-01 | 삼성전자주식회사 | Method of forming fine pattern of semiconductor device |
| JP5698923B2 (en) * | 2009-06-26 | 2015-04-08 | ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． | Self-aligned spacer multiple patterning method |
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Effective date of registration: 20201229 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 No. 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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Effective date of registration: 20220525 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |