CN103676491B - Method for reducing roughness of photoresist in electron beam lithography - Google Patents

Abstract

The invention discloses a method for reducing the roughness of resist in electron beam lithography, comprising: forming a structure material layer and a first hard mask layer on a substrate; forming a second hard mask layer on the first hard mask layer mold layer; forming an electron beam photoresist pattern on the second hard mask layer; using the electron beam photoresist pattern as a mask, etching the second hard mask layer to form a second hard mask pattern; The mask pattern is a mask, and the first hard mask layer is etched to form the first hard mask pattern; the first and second hard mask patterns are used as masks to etch the structural material layer to form required lines. According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the transfer of the side wall roughness of the electron beam photoresist to the underlying structural material layer, effectively reduces the roughness of the lines, and improves The stability of the process is improved, and the fluctuation of device performance is reduced.

Description

Method for Reducing Resist Roughness in Electron Beam Lithography

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for reducing the roughness of resist during electron beam lithography.

Background technique

With the gradual reduction of VLSI feature size, the technical limit of ordinary optical exposure has come after entering the 22nm technology generation in the manufacturing method of semiconductor devices. At present, after the 45nm process node, i193nm immersion lithography technology combined with double exposure and double etching technology is generally used to prepare smaller lines. Fine patterning at nodes below 22nm typically requires exposure and lithography using e-beam or EUV.

Regarding EUV lithography technology, it is still in the research and development stage, and there are still several key technologies that need to be overcome and improved, and it cannot be applied to large-scale integrated circuit manufacturing. In contrast, after years of development, the electron beam exposure technology is relatively mature, and the electron beam exposure has high precision, the resolution can reach several nanometers, and the lines of ultra-fine graphics can be written, but the efficiency is low, so The contradiction between scanning accuracy and scanning efficiency has become the main contradiction in electron beam lithography.

On the other hand, after entering the 32nm node process, line roughness has become a key issue that must be considered, including line edge roughness (LER) and line width roughness (LWR). For EUV or electron beam technology, the problem of line roughness is encountered. In particular, when the electron beam exposure technology is used, the requirements on the photoresist (resist) are higher, and there is often a contradiction between the line resolution and the thickness of the photoresist. The thinner the photoresist, the smaller the lines can be exposed. However, such a thin photoresist is often lost early in the etching process due to the insufficient selectivity of the etching process, and thus cannot produce the desired , and have severe line roughness issues.

Contents of the invention

In view of this, the purpose of the present invention is to be independent of photoresist, combined with a new hard mask technology, so that the roughness of the line is greatly reduced, the process is more stable, and the variation of the threshold voltage is also reduced.

Achieving the above-mentioned purpose of the present invention is by providing a method for reducing the roughness of the resist during electron beam lithography, comprising: forming a structural material layer and a first hard mask layer on a substrate; Form a second hard mask layer on the second hard mask layer; form an electron beam photoresist pattern on the second hard mask layer; use the electron beam photoresist pattern as a mask, etch the second hard mask layer to form a second hard mask pattern; using the second hard mask pattern as a mask, etching the first hard mask layer to form a first hard mask pattern; using the first and second hard mask patterns as masks, etching the structural material layer to form required lines.

Wherein, the first hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride and combinations thereof.

Wherein, the first hard mask layer is a laminated structure of silicon oxide and silicon nitride.

Wherein, the second hard mask layer includes polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous carbon and combinations thereof.

Wherein, the etching of the first hard mask layer and/or the second hard mask layer and/or the structural material layer adopts plasma dry etching technology.

Wherein, plasma dry etching adopts CCP, ICP or TCP equipment.

Wherein, after etching, dry stripping and/or wet etching cleaning are also included.

Among them, wet corrosion cleaning adopts SPM+APM.

Wherein, the structural material layer is one of a dummy gate electrode layer, a metal gate electrode layer, and a local interconnection layer.

Wherein, the first and/or second hard mask layer is prepared by LPCVD, PECVD, HDPCVD, MBE, ALD method.

According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the transfer of the side wall roughness of the electron beam photoresist to the underlying structural material layer, effectively reduces the roughness of the lines, and improves The stability of the process is improved, and the fluctuation of device performance is reduced.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 is a schematic diagram of an electron beam lithography layout;

2 to 5 are schematic cross-sectional views of various steps of the method for reducing the roughness of the resist during electron beam lithography according to the present invention; and

FIG. 6 is a flowchart of a method for reducing the roughness of a resist during electron beam lithography according to the present invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower", "thick", "thin" and the like used in this application can be used for Modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.

Referring to accompanying drawing 1, it is a schematic top view of a pattern with a small line width prepared by electron beam technology. Wherein, a plurality of parallel rectangular lines in the illustration represent patterns that need to be exposed by electron beams, and lines with pattern sizes smaller than nodes below 22nm can be prepared. The lines are, for example, lines of various structural material layers such as a dummy gate layer, a metal gate layer, and a local interconnection layer. The following FIGS. 2 to 5 will be described by taking gate manufacturing as an example.

Referring to FIG. 2 , a substrate 1 is provided, and a structural material layer 2/3 and a first hard mask layer 4A are sequentially formed on the substrate 1, and a second hard mask layer 4B is formed on the first hard mask layer 4A. . The substrate 1 is reasonably selected according to the application requirements of the device, and may include single crystal silicon (Si), SOI, single crystal germanium (Ge), GeOI, strained silicon (Strained Si), silicon germanium (SiGe), or compound semiconductor materials, such as nitrogen Gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, etc. In consideration of compatibility with the CMOS process, the substrate 1 is preferably bulk Si or SSOI. Taking the fabrication of gate lines as an example, the structural material layer includes a gate insulating layer 2 and a gate conductive layer 3 . The gate insulating layer 2 is deposited on the substrate 1 by methods such as LPCVD, PECVD, HDPCVD, RTO, chemical oxidation, MBE, ALD, etc., and its material can be silicon oxide, silicon oxynitride, and high-k materials, wherein the high-k materials include But not limited to hafnium-based oxides (such as HfO2, HfSiON, HfLaON), metal oxides (mainly subgroup and lanthanide metal element oxides, such as Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), perovskite phase oxides (eg PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)). A gate conductive layer 3 is formed on the gate insulating layer 2 by deposition methods such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, and sputtering. In the gate-front process, the gate conductive layer 3 is doped polysilicon, metals and nitrides thereof, wherein the metals include Al, Cu, Ti, Ta, W, Mo and combinations thereof. In the gate-last process, the gate conductive layer 3 may be a dummy gate, including polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, etc. and combinations thereof. The first hard mask layer 4A is deposited on the gate conductive layer 3 by methods such as LPCVD, PECVD, HDPCVD, etc., which can be a single layer or a multi-layer stacked structure, and its material can include silicon oxide, silicon nitride, nitrogen Silicon oxide and combinations thereof. In one embodiment of the present invention, the hard mask layer 4A is a multilayer structure of ONO, that is, including a bottom layer of silicon oxide, a middle layer of silicon nitride, and a top layer of silicon oxide (the layered structure of the ONO is not shown in the figure ). A second hard mask layer 4B of different materials is deposited on the first hard mask layer 4A of insulating material by conventional processes such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, and sputtering. The material of layer 4B is, for example, polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous carbon (DLC), etc. and combinations thereof. Optionally, the layer 4B is made of the same material as the gate conductive layer 3 serving as a dummy gate, for example, both are amorphous silicon.

Referring to FIG. 3 , a photoresist 5 is coated on the hard mask 4A/4B, which is a photoresist suitable for electron beam direct writing technology, such as PMMA, epoxy 618, COP and so on. The electron beam direct writing technology is used for exposure, and the ultra-fine pattern at or below the 22nm node is obtained by developing in a developing solution such as isopropanone, that is, the photoresist pattern 5P shown in the figure. In this process, due to the electron beam direct writing technology and the characteristics of the photoresist itself (such as the proximity effect, etc.), the side of the pattern 5P may not be aligned enough, and the line edge roughness (LER) and line width roughness (LWR) are relatively high. Large, so the hard mask layer 4A, especially the layer 4B, is required for modification and adjustment.

Referring to FIG. 4 , using the photoresist pattern 5P as a mask, the hard mask layer 4A/4B is etched using an anisotropic etching technique to form a hard mask pattern 4P. Specifically, dry etching techniques such as plasma etching and reactive ion etching (RIE) are used to etch the upper second hard mask layer 44B first, and stop on the first hard mask layer 4A to form a slightly steep The second hard mask pattern of the straight topography (upper part 4PB of 4P in the figure). The etching gas may be a fluorocarbon-based gas, and may also include an inert gas and an oxidizing gas to adjust an etching rate. Wherein, the dry etching equipment may be ICP, TCP, CCP equipment. Then, using the second hard mask pattern as a mask, the above dry etching technique is also used to etch the first hard mask layer 4A, stopping on the structural material layer (specifically, the gate conductive layer 3) to form a steeper layer. Straight first hard mask pattern (lower part 4PA of 4P in the figure). Due to the existence of the second hard mask layer, a preliminary steep pattern is obtained during dry etching, and then a steeper pattern is formed by further etching, thereby avoiding the downward roughness of the side wall of the photoresist pattern. Transferred to the structural material layer 2/3, effectively reducing the roughness of the lines (LER and LWR). Subsequently, preferably, the polymer and its particles generated during the etching process are removed by dry etching and/or wet etching, such as dry etching using fluorine-based plasma etching, wet etching such as SPM (such as Sulfuric acid: hydrogen peroxide = 4: 1)/APM (eg ammonia water: hydrogen peroxide: deionized water = 1: 1: 5 or 0.5: 1: 5) wet cleaning.

Referring to FIG. 5 , using the hard mask pattern 4P as a mask, the structural material layer is etched to form final lines. For example, an anisotropic dry etching technique, such as plasma etching, RIE, etc., is used to etch the gate conductive layer 3 until the gate insulating layer 2 is exposed, forming a steep gate electrode pattern 3P. Afterwards, the above wet etching process is used to remove the polymer formed during the etching process.

An embodiment of the present invention has been described above by taking the etching of gate lines as an example, but in fact the method of the present invention can be applied to various semiconductor structures, and layers 2 and 3 can be any structural material layers, such as dummy gate stacks structures, local interconnect structures, top pad structures, and more.

According to the method of the present invention, multi-layer hard mask layers with different materials are used and etched multiple times, which prevents the transfer of the side wall roughness of the electron beam photoresist to the underlying structural material layer, effectively reduces the roughness of the lines, and improves The stability of the process is improved, and the fluctuation of device performance is reduced.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in the method of forming the device structure without departing from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (9)

1. A method for reducing the roughness of resist during electron beam lithography, comprising: forming a layer of structural material and a first hard mask layer on the substrate; A second hard mask layer is formed on the first hard mask layer, and the second hard mask layer includes polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, amorphous germanium, SiC, SiGe, diamond-like amorphous Carbon and its combinations; forming an electron beam photoresist pattern on the second hard mask layer; Using the electron beam photoresist pattern as a mask, etching the second hard mask layer to form a second hard mask pattern; Using the second hard mask pattern as a mask, etching the first hard mask layer to form the first hard mask pattern; Using the first and second hard mask patterns as masks, the structural material layer is etched to form required lines. 2. The method of claim 1, wherein the first hard mask layer comprises silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. 3. The method of claim 2, wherein the first hard mask layer is a stacked structure of silicon oxide and silicon nitride. 4. The method according to claim 1, wherein the etching of the first hard mask layer and/or the second hard mask layer and/or the structural material layer adopts plasma dry etching technology. 5. The method according to claim 4, wherein the dry plasma etching adopts CCP or ICP or TCP equipment. 6 . The method according to claim 4 , further comprising dry stripping and/or wet etching cleaning after etching. 7 . 7. The method according to claim 6, wherein SPM+APM is used for wet etching cleaning. 8. The method according to claim 1, wherein the structural material layer is one of a dummy gate electrode layer, a metal gate electrode layer, and a local interconnection layer. 9. The method according to claim 1, wherein the first and/or the second hard mask layer is prepared by LPCVD, PECVD, HDPCVD, MBE, ALD method.