CN103676485B - Thick epitaxy technique photoetching alignment mark structure - Google Patents
Thick epitaxy technique photoetching alignment mark structure Download PDFInfo
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- CN103676485B CN103676485B CN201210323838.5A CN201210323838A CN103676485B CN 103676485 B CN103676485 B CN 103676485B CN 201210323838 A CN201210323838 A CN 201210323838A CN 103676485 B CN103676485 B CN 103676485B
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- silicon
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- photoetching alignment
- deielectric
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- 238000001259 photo etching Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000000407 epitaxy Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- 239000013078 crystal Substances 0.000 claims abstract description 29
- 239000011248 coating agent Substances 0.000 claims abstract description 21
- 238000000576 coating method Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000001459 lithography Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000008034 disappearance Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention discloses a kind of thick epitaxy technique photoetching alignment mark structure, have silicon single crystal region, policrystalline silicon region and deielectric-coating region on a semiconductor substrate; Multiple groove is had, as photoetching alignment mark at deielectric-coating region etch.The problem that after the present invention can well solve thick epitaxial growth, photoetching alignment mark is out of shape.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit structure.
Background technology
Planar optical waveguide power splitter (PLCOpticalPowerSplitter), optical shunt device is made by semiconductor technology, light function along separate routes realizes in chip, the fiber array realization of chip two ends by encapsulation coupling input and output and the link of optical fiber.PLC technique has: one, insensitive to wavelength; Two, divide optical uniformity better; Three, the above light-splitting device in 1X32 road can be drawn, and the more unit costs of light splitting way are more cheap; The advantage such as four, device volume is less, wide market.The shortcoming of PLC: 1, technical threshold is higher, chip is by import along separate routes for current light, and there is laboratory level in domestic Jin Jijia university; 2, domestic current commercial production only has encapsulation manufacturer.
In actual production process, due to PLC device couples device means suitable different depth staircase structural model, total depth reaches 13 μm.This structure function is obvious by effect of depth, and the simple etching technics that uses cannot be met claimed structure, adopts conventional epitaxial and etches the technique combined.After forming difference in functionality device region by techniques such as successively etch-deposition, then via epitaxy technique, monocrystalline silicon thickness is added to 13 microns.In this process, silicon single crystal region growing epitaxy single-crystal, non-silicon crystal region growing epitaxial polycrystalline.Because extension needs higher temperature deposit 5 ~ 10 microns, cause the problem such as polycrystalline rough surface and extension blocked up photoetching alignment mark distortion disappearance.
Existing technique adopts silicon area etching groove as photoetching alignment mark usually, and after thick epitaxial growth, photoetching alignment mark is easy to that distortion occurs and disappears even completely, and then causes lithography alignment and have a strong impact on, and makes silicon chip continue subsequent process flow.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of thick epitaxy technique photoetching alignment mark structure, and it can solve the problems such as alignment mark distortion, disappearance.
In order to solve above technical matters, the invention provides a kind of thick epitaxy technique photoetching alignment mark structure, having silicon single crystal region, policrystalline silicon region and deielectric-coating region on a semiconductor substrate; Multiple groove is had, as photoetching alignment mark at deielectric-coating region etch.
Beneficial effect of the present invention is: the problem that after can well solving thick epitaxial growth, photoetching alignment mark is out of shape.
Described deielectric-coating is monox, silicon nitride, at least one in silicon oxynitride.
The ditch groove width 0.1-100 micron of described photoetching alignment mark, long 0.1-100 micron, the degree of depth is 0.05-5 micron.
The thickness of described deielectric-coating is greater than the gash depth of photoetching alignment mark.
Silicon epitaxy is 5-150 micron at the thickness of the silicon crystal that silicon single crystal or poly-region grow, and at silicon single crystal region growing silicon single crystal, policrystalline silicon region growing policrystalline silicon or amorphous, in deielectric-coating region, comprise photoetching alignment mark trench interiors not growing silicon crystal.
The distance of described photoetching alignment mark and silicon single crystal or poly-region is than silicon epitaxy at the silicon crystal thickness of this region growing large more than 50 microns.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is schematic diagram silicon substrate growing SIO2 layer;
Fig. 2 is the schematic diagram growing Poly on SIO2 layer;
Fig. 3 is the schematic diagram in Poly surface etch lithography alignment region;
Fig. 4 is the schematic diagram in SIO2 surface etch photoetching alignment mark;
Fig. 5 is the schematic diagram utilizing epitaxial selective to form the clear figure in lithography alignment district;
Fig. 6 is lithography alignment figure vertical view;
Fig. 7 is alignment mark provided by the invention and traditional alignment mark comparison diagram.
Embodiment
The invention provides the manufacture of novel lithography alignment icon, solve the problems such as alignment mark distortion, disappearance.
There is silicon single crystal region and poly-region in the present invention, deielectric-coating region on semiconductor-based egative film simultaneously, wherein becomes alignment mark in deielectric-coating region etch channel shaped.In follow-up growing epitaxial silicon process, regulate epitaxial growth technology to realize at crystal region growing epitaxial monocrystalline, poly-region growing epitaxial polycrystalline, deielectric-coating region comprises trench interiors all not growing silicon crystals, ensure that before and after growing epitaxial silicon, alignment mark does not affect by thick extension.At deielectric-coating region and silicon crystal region intersection due to silicon crystal cross growth, the deielectric-coating subregion adjacent with silicon crystal region has polycrystalline cross growth above, in order to photoetching signal is interference-free, this part polycrystalline must have enough distances with contraposition groove.
The problem that after the present invention can well solve thick epitaxial growth, photoetching alignment mark is out of shape.
A kind of method for making of thick epitaxy technique photoetching alignment mark:
1. on silica-based egative film, utilize boiler tube or chemical deposition mode to form thickness at 0.5-3.0 micron deielectric-coating (SIO2 SIN), as shown in Figure 1
2. utilize chemical deposition mode to form thickness in 0.1-1.0 micron silicon polycrystalline film on deielectric-coating surface, as shown in Figure 2
3. utilize etching technics remove lithography alignment region and treat monocrystalline silicon growing region place policrystalline silicon rete, as shown in Figure 3.
4. utilize photoetching, etching technics at lithography alignment region making photoetching alignment mark groove, as shown in Figure 4, slot trough is from deielectric-coating and silicon crystal interface 200 microns.
5. by regulating epitaxial diposition program, generate epitaxy single-crystal at single crystal surfaces, generate epi polysilicon at polysilicon surface, thickness, all at 5-20 micron, does not grow in deielectric-coating region, thus keeps etching groove pattern, as shown in Figure 5.This alignment mark schematic top plan view, as shown in Figure 6.
6. alignment mark provided by the invention and traditional alignment mark contrast: as shown in Figure 7.Tradition alignment mark is after experience after epitaxial growth, and alignment mark distortion is serious, hardly can identification under SEM, and alignment mark provided by the invention, because extension does not grow thereon, complete remaining accurately etches rear contraposition groove pattern, intactly can realize lithography alignment.
The invention provides the manufacture of novel lithography alignment icon, photoetching alignment mark is made at mask layer (SIO2 or SIN) by photoetching, etching technics, and regulate epitaxial diposition program, non-deposition region is formed on this surface, thus successfully keep photoetching alignment mark original appearance, solve the problems such as alignment mark distortion, disappearance.
The present invention is not limited to embodiment discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.
Claims (3)
1. a thick epitaxy technique photoetching alignment mark structure, is characterized by: have silicon single crystal region, policrystalline silicon region and deielectric-coating region on a semiconductor substrate;
Multiple groove is had, as photoetching alignment mark at deielectric-coating region etch;
Described deielectric-coating is monox, silicon nitride, at least one in silicon oxynitride;
The ditch groove width 0.1-100 micron of described photoetching alignment mark, long 0.1-100 micron, the degree of depth is 0.05-5 micron;
Described policrystalline silicon region is adjacent with photoetching alignment mark, and the distance in photoetching alignment mark and silicon single crystal or policrystalline silicon region is than silicon epitaxy at the silicon crystal thickness of this region growing large more than 50 microns.
2. thick epitaxy technique photoetching alignment mark structure as claimed in claim 1, is characterized by: the thickness of described deielectric-coating is greater than the gash depth of photoetching alignment mark.
3. thick epitaxy technique photoetching alignment mark structure as claimed in claim 1, it is characterized by: silicon epitaxy is 5-150 micron at the thickness of the silicon crystal that silicon single crystal or poly-region grow, and at silicon single crystal region growing silicon single crystal, policrystalline silicon region growing policrystalline silicon or amorphous, in deielectric-coating region, comprise photoetching alignment mark trench interiors not growing silicon crystal.
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| CN201210323838.5A CN103676485B (en) | 2012-09-04 | 2012-09-04 | Thick epitaxy technique photoetching alignment mark structure |
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| CN201210323838.5A CN103676485B (en) | 2012-09-04 | 2012-09-04 | Thick epitaxy technique photoetching alignment mark structure |
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| CN103676485B true CN103676485B (en) | 2016-04-13 |
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| CN103700649B (en) * | 2012-09-28 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | Photoetching mark applying epitaxial technology and method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314837A (en) * | 1992-06-08 | 1994-05-24 | Analog Devices, Incorporated | Method of making a registration mark on a semiconductor |
| CN1577895A (en) * | 2003-07-16 | 2005-02-09 | 株式会社液晶先端技术开发中心 | Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate,thin-film semiconductor device, and method of manufacture |
| CN1950542A (en) * | 2004-05-19 | 2007-04-18 | 国际商业机器公司 | Yield improvement in silicon-germanium epitaxial growth |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10312964A (en) * | 1997-05-13 | 1998-11-24 | Sony Corp | Manufacture of semiconductor device |
| JP5560931B2 (en) * | 2010-06-14 | 2014-07-30 | 富士電機株式会社 | Manufacturing method of super junction semiconductor device |
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- 2012-09-04 CN CN201210323838.5A patent/CN103676485B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5314837A (en) * | 1992-06-08 | 1994-05-24 | Analog Devices, Incorporated | Method of making a registration mark on a semiconductor |
| CN1577895A (en) * | 2003-07-16 | 2005-02-09 | 株式会社液晶先端技术开发中心 | Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate,thin-film semiconductor device, and method of manufacture |
| CN1950542A (en) * | 2004-05-19 | 2007-04-18 | 国际商业机器公司 | Yield improvement in silicon-germanium epitaxial growth |
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