CN103031598B - The processing method of growing epitaxial silicon - Google Patents

The processing method of growing epitaxial silicon Download PDF

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CN103031598B
CN103031598B CN201210291209.9A CN201210291209A CN103031598B CN 103031598 B CN103031598 B CN 103031598B CN 201210291209 A CN201210291209 A CN 201210291209A CN 103031598 B CN103031598 B CN 103031598B
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silicon
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CN103031598A (en
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刘继全
高杏
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention discloses a kind of processing method of growing epitaxial silicon, comprising: 1) on a silicon substrate, growthing silica or silicon nitride masking layer, or using the two superposition as masking layer; 2) silicon monocrystal growth window is formed; 3) to silicon monocrystal growth window turnover pre-treatment, anaerobism surface is formed; 4) the first silicon single-crystal epitaxy is carried out; 5) in the first silicon single-crystal extension, grow the second silicon single-crystal, masking layer grows the first policrystalline silicon; 6) growth regulation three silicon single-crystal on the second silicon single-crystal, the first policrystalline silicon grows the second policrystalline silicon.The present invention can realize multi-level epitaxial structure synchronous growth, under realizing equal groove width, and higher silicon single-crystal effective area, and reduce high temperature polysilicon layer thickness, realize lower policrystalline silicon surfaceness, can be applicable in the manufacture of planar optical waveguide power splitter.

Description

The processing method of growing epitaxial silicon
Technical field
The present invention relates to the epitaxial growth method in a kind of semiconductor applications, particularly relate to a kind of processing method of growing epitaxial silicon.
Background technology
Planar optical waveguide power splitter (PLC Optical Power Splitter), optical shunt device is made by semiconductor technology, light function along separate routes realizes in chip, the fiber array realization of chip two ends by encapsulation coupling input and output and the link of optical fiber.The technique of planar optical waveguide power splitter (PLC device) has: one, insensitive to wavelength; Two, divide optical uniformity better; Three, 1 × 32 above light-splitting device in road can be drawn, and the more unit costs of light splitting way are more cheap; The advantage such as four, device volume is less, wide market.But planar optical waveguide power splitter has following shortcoming: 1, technical threshold is higher, chip is by import along separate routes for current light, and there is laboratory level in domestic Jin Jijia university; 2, domestic current industrial production only has encapsulation manufacturer.
In actual production process, due to PLC device couples device means suitable different depths staircase structural model, total depth reaches 13 μm.This structure function is obvious by effect of depth, and the simple etching technics that uses cannot be met claimed structure, adopts conventional epitaxial and etches the technique combined.After forming difference in functionality device region by techniques such as successively etch-deposition, then via epitaxy technique, silicon single crystal thickness is added to 13 μm.In this process, silicon single-crystal region growing epitaxy single-crystal, non-silicon crystal region growing epitaxial polycrystalline.Because extension needs comparatively high temps deposit 5 ~ 10 μm, cause polycrystalline surfaceness seriously to impact photoetching and etching technics, easily produce the problem such as uneven bottom lithography alignment problem and etching groove.The usual high temperature epitaxy deposit of existing technique, after epitaxy, poly-region surface irregularity is serious, and photo-etching mark is easy to distort even completely dissolve, and then causes lithography alignment and have a strong impact on, and makes silicon chip continue subsequent process flow.Because silicon chip surface is seriously uneven, after etching, channel bottom has serious concavo-convex problem.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of processing method of growing epitaxial silicon.The method can realize multi-level epitaxial structure synchronous growth, therefore, can realize selective epitaxial and non-selective epitaxy synchronous growth, under realizing equal groove width, higher silicon single-crystal effective area, and reduce high temperature polysilicon layer thickness, realize lower policrystalline silicon surfaceness.
For solving the problems of the technologies described above, the processing method of growing epitaxial silicon of the present invention, comprises step:
1) on a silicon substrate, growthing silica or silicon nitride masking layer, or using the two superposition as masking layer;
2) by lithographic etch process, on a silicon substrate, silicon monocrystal growth window is formed;
3) to silicon monocrystal growth window turnover pre-treatment, anaerobism surface is formed;
4) at silicon monocrystal growth window, the first silicon single-crystal epitaxy is carried out, to realize selective epitaxial growth;
5) grown by epi polysilicon inculating crystal layer, make to grow the second silicon single-crystal in the first silicon single-crystal extension, masking layer grows the first policrystalline silicon;
6) on extension polysilicon seed layer, carry out complete outer layer growth, make continued growth the 3rd silicon single-crystal on the second silicon single-crystal, continued growth second policrystalline silicon on the first policrystalline silicon.
(processing condition related in each step please describe in detail)
Described step 1) in, the mode of growth comprises: thermooxidizing mode or deposit mode grow masking layer, and according to thermooxidizing mode, oxidizing temperature, between 700 ~ 1200 DEG C, adopts normal pressure mode; According to deposit mode, then can use the vapor deposition of ion enhanced chemical, temperature of reaction is between 350 ~ 800 DEG C; The thickness of described silicon-dioxide or silicon nitride masking layer is 0.2 ~ 10 μm.
Described step 2) lithographic etch process in, as adopted pure dry carving technology, need carry out boiler tube reparation before subsequently epitaxial growing, repairing temperature is 900 ~ 1100 DEG C, repair time is 10 ~ 30min, and is removed by the sacrificial oxide layer formed in boiler tube repair process by wet etching.
Described step 3) in, pretreated method is: adopt RCA standard cleaning method, and in this purging method, increases the last cleaning step of HF, silicon face dangling bonds are replaced to unstable H-Si key, stops surface silicon oxidation.
Described step 4) in, the silicon source in the first silicon single-crystal epitaxy comprises: SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; Etching gas in first silicon single-crystal epitaxy is for containing haloid element etchant gas, and comprising: the one in HCl or HBr etc., etchant gas flow is 0.01 ~ 5slm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; The epitaxially grown pressure of first silicon single-crystal is 20 ~ 760Torr, and the epitaxially grown thickness of the first silicon single-crystal is 0.1 ~ 10 μm.
Described step 5) in, when the superiors' masking layer is silicon nitride, the silicon source in the growth of epi polysilicon inculating crystal layer comprises: SiH 2cl 2or SiH (DCS) 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; When the superiors' masking layer is silicon-dioxide, the silicon source in the growth of epi polysilicon inculating crystal layer is SiH 4, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 950 DEG C; Growth pressure in the growth of epi polysilicon inculating crystal layer is 20 ~ 760Torr, and the thickness of epi polysilicon inculating crystal layer is 0.1 ~ 1 μm.
Described step 6) in, the silicon source in full outer layer growth comprises: SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; Growth pressure in full outer layer growth is 20 ~ 760Torr, and the thickness of full epitaxial film is 0.1 ~ 10 μm.
In the present invention, growthing silica or silicon nitride or the two superposition are as masking layer on a silicon substrate, epitaxial monocrystalline growth region is etched on a silicon substrate subsequently by lithographic etch process, eventually through special epitaxial growth technology, realize at silicon single-crystal region growing selective epitaxial silicon single crystal layer, and fill after raceway groove completes, growing silicon single crystal and policrystalline silicon respectively simultaneously in silicon single-crystal district and policrystalline silicon district, finally realize selective epitaxial, the multi-level synchronous growth of non-selective epitaxy.
Epitaxy technique of the present invention divides 3 one-step growths: the epitaxy of the first step selective silicon, second step multi-crystalline silicon seed crystal layer growth, the full epitaxy of the 3rd step.Its key problem in technology is under low temperature growth conditions, multi-crystalline silicon seed crystal growth conditions, and meeting as too low in temperature causes crystal region Quality Down, and defect increases; The too high meeting of temperature causes non-crystalline areas cannot form polycrystalline seed crystal in blocks, causes surface only to have part poly grains, forms high step, affect subsequent etching lithographic process.Meanwhile, polycrystalline thickness needs consistent with monocrystalline thickness.By reducing epitaxy pressure, can reduce the growth velocity of silicon single-crystal and policrystalline silicon, wherein, policrystalline silicon underspeeds faster simultaneously; Reduce epitaxial growth temperature, can reduce the growth velocity of silicon single-crystal and policrystalline silicon, wherein, silicon single-crystal underspeeds faster simultaneously.At lower temperatures, silicon single-crystal degradation, and progressively to policrystalline silicon transition, therefore extension temperature of reaction lower than 640 DEG C, otherwise had better not will increase defect probability of occurrence, increase process debugging difficulty, affect monocrystalline quality.Utilizing HCl polishing technology before epitaxial deposition, surface preparation is carried out to silicon substrate, form bright and clean epitaxy interface, subsequently by effectively regulating epitaxy pressure and temperature, obtaining identical silicon single-crystal and the deposition rate of policrystalline silicon.
Therefore, the present invention a kind ofly realizes the synchronous method of multilayer, selective epitaxial and non-selective epitaxial growth on a semiconductor substrate, under equal groove width can be realized, higher silicon single-crystal effective area, and reduce high temperature polysilicon layer thickness, realize lower policrystalline silicon surfaceness, can effectively reduce polycrystalline surface roughness.Meanwhile, method of the present invention, can be applicable in the manufacture of planar optical waveguide power splitter.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 be growth or deposit masking layer after schematic diagram;
Fig. 2 is the schematic diagram after etching silicon monocrystal growth window;
Fig. 3 is the schematic diagram after silicon monocrystal growth;
Fig. 4 is the schematic diagram after being grown by extension polycrystalline inculating crystal layer;
Fig. 5 is the schematic diagram after full epitaxy;
Fig. 6 is the schematic diagram of the full epitaxy epitaxial thickness same with the present invention of tradition.
In figure, description of reference numerals is as follows:
11 is silicon base, and 12 is silicon dioxide masking layer, and 13 is silicon monocrystal growth window, and 14 is the first silicon single-crystal, and 15 is silicon single-crystal extension, and 15a is the first policrystalline silicon, and 15b is the second silicon single-crystal, and 15c is the second policrystalline silicon, and 15d is the 3rd silicon single-crystal.
Embodiment
The processing method of growing epitaxial silicon of the present invention, is a kind of method of simultaneously growing silicon single crystal and policrystalline silicon on a semiconductor substrate, comprises step:
1) in silicon base 11, by thermooxidizing mode or deposit mode, according to thermooxidizing mode, oxidizing temperature, between 700 ~ 1200 DEG C, adopts normal pressure mode; According to deposit mode, then can use the vapor deposition of ion enhanced chemical, temperature of reaction between 350 ~ 800 DEG C, growthing silica or silicon nitride masking layer, or using the two superposition as masking layer; Wherein, the thickness of silicon-dioxide or silicon nitride masking layer is 0.2 ~ 10 μm;
Fig. 1 is for silicon dioxide masking layer 12, is illustrated.
2) by lithographic etch process, in silicon base 11, silicon monocrystal growth window 13 (as shown in Figure 2) is formed;
Wherein, in lithographic etch process, as adopted pure dry carving technology, boiler tube reparation need be carried out before subsequently epitaxial growing, repairing temperature is 900 ~ 1100 DEG C, and repair time is 10 ~ 30min, and is removed by the sacrificial oxide layer formed in boiler tube repair process by wet etching.
3) before epitaxy, adopt RCA standard cleaning method, and in this purging method, increase the last cleaning step of HF, silicon face dangling bonds are replaced to unstable H-Si key, stops surface silicon oxidation, to realize carrying out pre-treatment to silicon chip, namely pre-treatment is passed in and out to silicon monocrystal growth window 13, form anaerobism surface.
4) selective epitaxial growth
Carry out growing epitaxial silicon in the silicon single-crystal region of opening, then do not grow in other regions, namely carry out the first silicon single-crystal 14 epitaxy (as shown in Figure 3) at silicon monocrystal growth window 13;
Wherein, the silicon source in the first silicon single-crystal 14 epitaxy is SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; Etching gas in first silicon single-crystal epitaxy is for containing haloid element etchant gas, and as the one in HCl or HBr etc., etchant gas flow is 0.01 ~ 5slm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; The epitaxially grown pressure of first silicon single-crystal 14 is 20 ~ 760Torr, and the epitaxially grown thickness of the first silicon single-crystal 14 is 0.1 ~ 10 μm.
5) epi polysilicon inculating crystal layer growth
At a lower temperature, silicon single-crystal region growing silicon single-crystal, at other region growing policrystalline silicons, is namely grown by epi polysilicon inculating crystal layer, make to grow the second silicon single-crystal 15b in the first silicon single-crystal 14 extension, masking layer grows the first policrystalline silicon 15a (as shown in Figure 4);
Wherein, when the superiors' masking layer is silicon nitride, the silicon source in the growth of epi polysilicon inculating crystal layer is SiH 2cl 2or SiH (DCS) 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; When the superiors' masking layer is silicon-dioxide, the silicon source in the growth of epi polysilicon inculating crystal layer is SiH 4, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 950 DEG C; Growth pressure in the growth of epi polysilicon inculating crystal layer is 20 ~ 760Torr, and the thickness of epi polysilicon inculating crystal layer (polysilicon seed layer that the second silicon single-crystal 15b and the first policrystalline silicon 15a is formed) is 0.1 ~ 1 μm.
6) full outer layer growth
At silicon single-crystal region growing silicon single-crystal, at other region growing policrystalline silicons, namely on extension polysilicon seed layer, complete outer layer growth is carried out, make continued growth the 3rd silicon single-crystal 15d on the second silicon single-crystal 15b, continued growth second policrystalline silicon 15c (as shown in Figure 5) on the first policrystalline silicon 15a.
Wherein, the silicon source in full outer layer growth is SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4deng in one, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; Growth pressure in full outer layer growth is 20 ~ 760Torr, and the thickness of full epitaxial film (the full epitaxial film that the 3rd silicon single-crystal 15d and the second policrystalline silicon 15c is formed) is 0.1 ~ 10 μm.
The silicon epitaxy formed according to the method described above, compared with the same epitaxial thickness of the full epitaxy of tradition:
Under extension total thickness same case, effective sector width=channel width-2 × highly × cos γ of extension
In the single non-selective epitaxial growth situation of tradition, the effective sector width of extension is S1=L-2 × (a+b) × cos γ (as shown in Figure 6);
And the effective sector width of extension of the present invention is S2=L-2 × b × cos γ, many 2 × a × cos gamma widths (as shown in Figure 5), and due to non-selective high temperature process time shorten, can effectively reduce polycrystalline surface roughness.Therefore, while the invention solves in conventional epitaxial mode, growing silicon single crystal and policrystalline silicon easily produce the shaggy problem of polycrystalline, and the present invention can be applicable in the manufacture of planar optical waveguide power splitter, solve the problem existing for follow-up lithographic etch process existed in prior art.

Claims (5)

1. a processing method for growing epitaxial silicon, is characterized in that, comprises step:
1) on a silicon substrate, growthing silica or silicon nitride masking layer, or using the two superposition as masking layer;
2) by lithographic etch process, on a silicon substrate, silicon monocrystal growth window is formed;
3) pre-treatment is carried out to silicon monocrystal growth window, form anaerobism surface;
4) at silicon monocrystal growth window, the first silicon single-crystal epitaxy is carried out; Described step 4) in, the silicon source in the first silicon single-crystal epitaxy comprises: SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4in one, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; Etching gas in first silicon single-crystal epitaxy is for containing haloid element etchant gas, and comprising: the one in HCl or HBr, etchant gas flow is 0.01 ~ 5slm; The epitaxially grown pressure of first silicon single-crystal is 20 ~ 760Torr, and the epitaxially grown thickness of the first silicon single-crystal is 0.1 ~ 10 μm;
5) grown by epi polysilicon inculating crystal layer, make to grow the second silicon single-crystal in the first silicon single-crystal extension, masking layer grows the first policrystalline silicon; Described step 5) in, when the superiors' masking layer is silicon nitride, the silicon source in the growth of epi polysilicon inculating crystal layer comprises: SiH 2cl 2or SiH 4in one, the gas flow in silicon source is 50 ~ 5000sccm; When the superiors' masking layer is silicon-dioxide, the silicon source in the growth of epi polysilicon inculating crystal layer is SiH 4, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 950 DEG C; Growth pressure in the growth of epi polysilicon inculating crystal layer is 20 ~ 760Torr, and the thickness of epi polysilicon inculating crystal layer is 0.1 ~ 1 μm;
6) on extension polysilicon seed layer, carry out complete outer layer growth, make continued growth the 3rd silicon single-crystal on the second silicon single-crystal, continued growth second policrystalline silicon on the first policrystalline silicon; Described step 6) in, the silicon source in full outer layer growth comprises: SiCl 4, SiHCl 3, SiH 2cl 2or SiH 4in one, the gas flow in silicon source is 50 ~ 5000sccm; The deposition temperature in silicon source is 450 ~ 1250 DEG C; Growth pressure in full outer layer growth is 20 ~ 760Torr, and the thickness of full epitaxial film is 0.1 ~ 10 μm.
2. the method for claim 1, is characterized in that: described step 1) in, the mode of growth comprises: thermooxidizing mode or deposit mode grow masking layer;
The thickness of described silicon-dioxide or silicon nitride masking layer is 0.2 ~ 10 μm.
3. method as claimed in claim 2, is characterized in that: during described thermooxidizing mode, and oxidizing temperature, between 700 ~ 1200 DEG C, adopts normal pressure mode;
During described deposit mode, use the vapor deposition of ion enhanced chemical, temperature of reaction is between 350 ~ 800 DEG C.
4. the method for claim 1, it is characterized in that: described step 2) lithographic etch process in, as adopted pure dry carving technology, boiler tube reparation need be carried out before subsequently epitaxial growing, repairing temperature is 900 ~ 1100 DEG C, repair time is 10 ~ 30min, and is removed by the sacrificial oxide layer formed in boiler tube repair process by wet etching.
5. the method for claim 1, is characterized in that: described step 3) in, pretreated method is: adopt RCA standard cleaning method, and in this purging method, increase the last cleaning step of HF, silicon face dangling bonds are replaced to unstable H-Si key, stop surface silicon oxidation.
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AU2016270313A1 (en) 2015-05-30 2018-01-04 Alpha-En Corporation High purity lithium and associated products and processes
US9865730B1 (en) * 2016-10-31 2018-01-09 International Business Machines Corporation VTFET devices utilizing low temperature selective epitaxy
CN113322513A (en) * 2021-08-03 2021-08-31 南京国盛电子有限公司 Method for growing thin-layer high-resistance silicon epitaxial wafer and epitaxial wafer prepared by same

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